Microchip Technology dsPIC33 series User manual

2018 Microchip Technology Inc. DS70005340A-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CAN FD Message Frames................................................................................................ 5
3.0 Control Registers .............................................................................................................. 9
4.0 Modes of Operation ........................................................................................................ 51
5.0 Configuration................................................................................................................... 57
6.0 Message Transmission ................................................................................................... 67
7.0 Transmit Event FIFO – TEF ............................................................................................ 76
8.0 Message Filtering............................................................................................................81
9.0 Message Reception ........................................................................................................ 86
10.0 FIFO Behavior................................................................................................................. 92
11.0 Timestamping................................................................................................................103
12.0 Interrupts....................................................................................................................... 104
13.0 Error Handling................................................................................................................111
14.0 Related Application Notes............................................................................................. 113
15.0 Revision History ............................................................................................................114
CAN Flexible Data-Rate (FD) Protocol Module

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1.0 INTRODUCTION
CAN Flexible Data-Rate (FD) addresses the increasing demand for bandwidth on CAN buses.
The two major enhancements over CAN 2.0B consist of:
• Increased data field up to 64 data bytes (currently 8 bytes)
• Option to switch to faster bit rate after the arbitration field
Figure 1-1 shows the possible increase in net bit rate due to the higher Data Bit Rate (DBR) and
increased data bytes per frame (© Robert Bosch GmbH).
Figure 1-1: Net CAN FD Bit Rate
The CAN FD protocol is defined to allow CAN 2.0 messages and CAN FD messages to co-exist
on the same bus. This does not imply that non-CAN FD controllers can be mixed with CAN FD
controllers on the same bus. Non-CAN FD controllers will generate error frames while receiving
a CAN FD message.
1.1 Features
The CAN FD module has the following features:
General
• Nominal (Arbitration) Bit Rate up to 1 Mbps
• Data Bit Rate up to 8 Mbps
• CAN FD Controller modes:
- Mixed CAN 2.0B and CAN FD mode
- CAN 2.0B mode
• Conforms to ISO11898-1:2015
Message FIFOs
• 31 FIFOs Configurable as Transmit or Receive FIFOs
• One Transmit Queue (TXQ)
• Transmit Event FIFO (TEF) with 32-Bit Timestamp
Message Transmission
• Message Transmission Prioritization:
- Based on priority bit field and/or
- Message with lowest ID gets transmitted first using the TXQ
• Programmable Automatic Retransmission Attempts: Unlimited, 3 Attempts or Disabled
Frame ID: 11-Bit, Bit Rate Arbitration: 1 Mbit

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CAN FD Protocol Module
Message Reception
• 32 Flexible Filter and Mask Objects
• Each Object can be Configured to Filter either:
- Standard ID and first 18 data bits or
- Extended ID
• 32-Bit Timestamp
• The CAN FD Bit Stream Processor (BSP) implements the Medium Access Control of the
CAN FD protocol described in ISO11898-1:2015. It serializes and deserializes the bit
stream, encodes and decodes the CAN FD frames, manages the medium access,
Acknowledges frames, and detects and signals errors.
• The TX handler prioritizes the messages that are requested for transmission by the
transmit FIFOs. It uses the RAM interface to fetch the transmit data from RAM and provides
it to the BSP for transmission.
• The BSP provides received messages to the RX handler. The RX handler uses an
acceptance filter to filter the messages that shall be stored in the receive FIFOs. It uses the
RAM interface to store received data into RAM.
• Each FIFO can be configured either as a transmit or receive FIFO. The FIFO control keeps
track of the FIFO head and tail, and calculates the user address. In a TX FIFO, the user
address points to the address in RAM where the data for the next transmit message is
stored. In an RX FIFO, the user address points to the address in RAM where the data of the
next receive message will be read. The user notifies the FIFO that a message is written to
or read from RAM by incrementing the head/tail of the FIFO.
• The TXQ is a special transmit FIFO that transmits the messages based on the ID of the
messages stored in the queue.
• The TEF stores the message IDs of the transmitted messages.
• A free-running Time Base Counter (TBC) is used to timestamp received messages.
Messages in the TEF can also be timestamped.
• The CAN FD controller module generates interrupts when new messages are received or
when messages are transmitted successfully.

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Figure 1-2 shows the System Block Diagram.
Figure 1-2: System Block Diagram
TX Handler
TX Prioritization
RX Handler
Filter and Masks
Timestamping
Interrupt Control
Error Handling Diagnostics
CxTX
CxRX
Device RAM
TEF
Message
Object 0
Message
Object 31
•
•
•
TXQ
Message
Object 0
Message
Object 31
•
•
•
FIFO 1
Message
Object 0
Message
Object 31
•
•
•
FIFO 31
Message
Object 0
Message
Object 31
•
•
•
•••

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CAN FD Protocol Module
2.0 CAN FD MESSAGE FRAMES
The ISO11898-1:2015 describes the different CAN message frames in detail. Figure 2-1
through Figure 2-6 explain and summarize the construction of the messages and fields.
There are four different CAN data/remote frames (see Figure 2-2):
•CAN Base Frame: Classic CAN 2.0 frame using Standard ID
•CAN FD Base Frame: CAN FD frame using Standard ID
•CAN Extended Frame: Classic CAN 2.0 frame using Extended ID
•CAN FD Extended Frame: CAN FD frame using Extended ID
There are no remote frames in CAN FD frames; therefore, the RTR bit is replaced with the RRS
bit (see Figure 2-2). The RRS bit in the CAN FD base frame can be used to extend the SID to
12 bits. When enabled, it is referred to as SID11, it is the LSB of SID<11:0>.
Figure 2-3 specifies the control field of the different CAN messages. Before CAN FD was added
to the ISO11898-1:2015, the FDF bit was a reserved bit. Now the FDF bit selects between
Classic and CAN FD formats.
The BRS bit selects if the bit rate should be switched in the data phase of CAN FD frames.
Figure 2-6 illustrates the error and overload frames. These special frames do not change.
2.1 ISO vs. NON-ISO CRC
To support the system validation of non-ISO CRC ECUs, the CAN FD controller module sup-
ports both ISO CRC (according to ISO11898-1:2015) and non-ISO CRC (see Figure 2-4 and
Figure 2-5). The CRC field is selectable using the ISOCRCEN bit (C1CONL<5>). The ISO CRC
field contains the stuff count. This count was not included in the original CAN FD specification; It
was added to fix a minor issue in the error detection of the original specification.
CAN FD frames use two different lengths of CRC: 17-bit for up to 16 data bytes and 21-bit for
20 or more data bytes. Technically, there are a total of six different CAN data/remove frames in
the CAN FD.
Figure 2-1: General Data Frame
Note: If an error is detected during the data phase of a CAN FD frame, the bit rate will be
switched back to the Nominal Bit Rate (NBR). Error frames are always transmitted
at the arbitration bit rate.
IFS
(= 3b)
SOF
(1b) ARBITRATION (12/32b) CTRL (6/8/9b) DATA (0 to 64b)
CRC (16/18/22b)
CRC (16/22/26b) ACK (2b) EOF (7b) IFS (= 3b)
DATA FRAME

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Figure 2-2: Arbitration Field
Figure 2-3: Control Field
Figure 2-4: ISO CRC Field
ARBITRATION (12/32b)
SID<10:0> RTR
SID<10:0> RRS
SID11
EID<28:18> SRR IDE EID<17:0> RTR
EID<28:18> SRR IDE EID<17:0> RRS
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CTRL (6/8/9b)
IDE FDF
IDE ESI
FDF DLC<3:0>
FDF ESI DLC<3:0>
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
DLC<3:0>
FDF BRS DLC<3:0>
r0
res BRS
CRC (16/22/26b)
CRC (15b)
CRC (15b)
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CRC
CRC (17/21b)
BRS
DEL
CRC
DEL
STUFF
CNT (4b)
CRC
DEL
STUFF
CNT (4b)
CRC
DEL

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CAN FD Protocol Module
Figure 2-5: NON-ISO CRC Field
Figure 2-6: Error and Overload Frame
CRC (16/18/22b)
CRC (15b)
CRC (15b)
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CRC
CRC (17/21b)
CRC (17/21b)
DEL
CRC
DEL
CRC
DEL
CRC
DEL
ANYWHERE WITHIN DATA FRAME ERRFLAG (6b) ERRDEL (8b) IFS (= 3b) or OVL
EOF or ERRDEL or OVLDEL OVLFLAG (6b) OVLDEL (8b) IFS (= 3b) or OVL
ERROR
OVERLOAD

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2.1.1 DLC ENCODING
The Data Length Code (DLC) specifies the number of data bytes a message frame contains.
Table 2-1 illustrates the encoding.
Table 2-1: DLC Encoding
Frame DLC Number of Data Bytes
CAN 2.0 and CAN FD 0 0
11
22
33
44
55
66
77
88
CAN 2.0 9-15 8
CAN FD 9 12
10 16
11 20
12 24
13 32
14 48
15 64

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CAN FD Protocol Module
3.0 CONTROL REGISTERS
CAN FD operations are controlled using the following Special Function Registers (SFRs). The
following registers are described later in this section:
•Register 3-1: C1CONH
•Register 3-2: C1CONL
•Register 3-3: C1NBTCFGH
•Register 3-4: C1NBTCFGL
•Register 3-5: C1DBTCFGH
•Register 3-6: C1DBTCFGL
•Register 3-7: C1TDCH
•Register 3-8: C1TDCL
•Register 3-9: C1TBCH
•Register 3-10: C1TBCL
•Register 3-11: C1TSCONH
•Register 3-12: C1TSCONL
•Register 3-13: C1VECH
•Register 3-14: C1VECL
•Register 3-15: C1INTH
•Register 3-16: C1INTL
•Register 3-17: C1RXIFH
•Register 3-18: C1RXIFL
•Register 3-19: C1RXOVIFH
•Register 3-20: C1RXOVIFL
•Register 3-21: C1TXIFH
•Register 3-22: C1TXIFL
•Register 3-23: C1TXATIFH
•Register 3-24: C1TXATIFL
•Register 3-25: C1TXREQH
•Register 3-26: C1TXREQL
•Register 3-27: C1FIFOBAH
•Register 3-28: C1FIFOBAL
•Register 3-29: C1TXQCONH
•Register 3-30: C1TXQCONL
•Register 3-31: C1TXQSTA
•Register 3-32: C1FIFOCONxH
•Register 3-33: C1FIFOCONxL
•Register 3-34: C1FIFOSTAx
•Register 3-35: C1TEFCONH
•Register 3-36: C1TEFCONL
•Register 3-37: C1TEFSTA
•Register 3-38: C1FOUAxH
•Register 3-39: C1FOUAxL
•Register 3-40: C1TEFUAH
•Register 3-41: C1TEFUAL
•Register 3-42: C1TXQUAH
•Register 3-43: C1TXQUAL
•Register 3-44: C1TRECH
•Register 3-45: C1TRECL
•Register 3-46: C1BDIAG0H
•Register 3-47: C1BDIAG0L
•Register 3-48: C1BDIAG1H
•Register 3-49: C1BDIAG1L
•Register 3-50: C1FLTCONxH
•Register 3-51: C1FLTCONxL
•Register 3-52: C1FLTOBJxH
•Register 3-53: C1FLTOBJxL
•Register 3-54: C1MASKxH
•Register 3-55: C1MASKxL

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Register 3-1: C1CONH: CAN Control Register High
R/W-0 R/W-0 R/W-0 R/W-0 S/HC-0 R/W-1 R/W-0 R/W-0
TXBWS3 TXBWS2 TXBWS1 TXBWS0 ABAT REQOP2 REQOP1 REQOP0
bit 15 bit 8
R-1 R-0 R-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
OPMOD2 OPMOD1 OPMOD1 TXQEN
(1)
STEF
(1)
SERRLOM
(1)
ESIGM
(1)
RTXAT
(1)
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 TXBWS<3:0>: Transmit Bandwidth Sharing bits
1111-1100 = 4096
1011 = 2048
1010 = 1024
1001 = 512
1000 = 256
0111 = 128
0110 = 64
0101 = 32
0100 = 16
0011 = 8
0010 = 4
0001 = 2
0000 = No delay
bit 11 ABAT: Abort All Pending Transmissions bit
1= Signals all transmit buffers to abort transmission
0= Module will clear this bit when all transmissions are aborted
bit 10-8 REQOP<2:0>: Request Operation Mode bits
111 = Sets Restricted Operation mode
110 = Sets Normal CAN 2.0 mode; error frames on CAN FD frames
101 = Sets External Loopback mode
100 = Sets Configuration mode
011 = Sets Listen Only mode
010 = Sets Internal Loopback mode
001 = Sets Disable mode
000 = Sets Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
bit 7-5 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Restricted Operation mode
110 = Module is in Normal CAN 2.0 mode; error frames on CAN FD frames
101 = Module is in External Loopback mode
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Internal Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
bit 4 TXQEN: Enable Transmit Queue bit
(1)
1= Enables TXQ and reserves space in RAM
0= Does not reserve space in RAM for TXQ
Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> =
100 ).

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CAN FD Protocol Module
bit 3 STEF: Store in Transmit Event FIFO bit
(1)
1= Saves transmitted messages in TEF
0= Does not save transmitted messages in TEF
bit 2 SERRLOM: Transition to Listen Only Mode on System Error bit
(1)
1= Transitions to Listen Only mode
0= Transitions to Restricted Operation mode
bit 1 ESIGM: Transmit ESI in Gateway Mode bit
(1)
1= ESI is transmitted as recessive when the ESI of message is high or CAN controller is error passive
0= ESI reflects error status of the CAN controller
bit 0 RTXAT: Restrict Retransmission Attempts bit
(1)
1= Restricted retransmission attempts, uses TXAT<1:0> (C1FIFOCONxH<6:5>)
0= Unlimited number of retransmission attempts, TXAT<1:0> bits will be ignored
Register 3-1: C1CONH: CAN Control Register High (Continued)
Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100 ).

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Register 3-2: C1CONL: CAN Control Register Low
R/W-0 U-0 R/W-0 R/W-0 R-0 R/W-1 R/W-1 R/W-1
CON — SIDL BRSDIS BUSY WFT1 WFT0 WAKFIL
(1)
bit 15 bit 8
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLKSEL
(1)
PXEDIS
(1)
ISOCRCEN
(1)
DNCNT4 DNCNT3 DNCNT2 DNCNT1 DNCNT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: CAN Enable bit
1= CAN module is enabled
0= CAN module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: CAN Stop in Idle Control bit
1= Stops module operation in Idle mode
0= Does not stop module operation in Idle mode
bit 12 BRSDIS: Bit Rate Switching Disable bit (BRS)
1= Bit Rate Switching is disabled, regardless of BRS in the transmit message object
0= Bit Rate Switching depends on BRS in the transmit message object
bit 11 BUSY: CAN Module is Busy bit
1= The CAN module is active
0= The CAN module is inactive
bit 10-9 WFT<1:0>: Selectable Wake-up Filter Time bits
11 = T11
FILTER
10 = T10 FILTER
01 = T01 FILTER
00 = T00 FILTER
bit 8 WAKFIL: Enable CAN Bus Line Wake-up Filter bit
(1)
1= Uses CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 7 CLKSEL: Module Clock Source Select bit
(1)
1= Auxiliary clock is active when module is enabled
0= CAN clock is not active when module is enabled
bit 6 PXEDIS: Protocol Exception Event Detection Disabled bit
(1)
A recessive “reserved bit” following a recessive FDF bit is called a “Protocol Exception”.
1= Protocol exception is treated as a form error
0= If a protocol exception is detected, CAN will enter the bus integrating state
bit 5 ISOCRCEN: Enable ISO CRC in CAN FD Frames bit
(1)
1= Includes stuff bit count in CRC field and uses non-zero CRC initialization vector
0= Does not include
Stuff Bit Co unt in CRC field and uses CRC initialization vector with all zeros
bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10011-11111 = Invalid selection (compares up to 18 bits of data with EIDx)
10010 = Compares up to DATA Byte 2, bit 6 with EID17
...
00001 = Compares up to Data Byte 0, bit 7 with EID0
00000 = Does not compare data bytes
Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> =
100 ).

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CAN FD Protocol Module
Register 3-3: C1NBTCFGH: CAN Nominal Bit Time Configuration Register High
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BRP<7:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
TSEG1<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 BRP<7:0>: Baud Rate Prescaler bits
1111 1111 = T Q = 256/F SYS
...
0000 0000 = T
Q = 1/F SYS
bit 7-0 TSEG1<7:0>: Time Segment 1 bits (Propagation Segment + Phase Segment 1)
1111 1111 = Length is 256 x T Q
...
0000 0000 = Length is 1 x T
Q
Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100 ).
Register 3-4: C1NBTCFGL: CAN Nominal Bit Time Configuration Register Low
(1)
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
— TSEG2<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
—SJW<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 TSEG2<6:0>: Time Segment 2 bits (Phase Segment 2)
111 1111 = Length is 128 x T
Q
...
000 0000 = Length is 1 x T
Q
bit 7 Unimplemented: Read as ‘0’
bit 6-0 SJW<6:0>: Synchronization Jump Width bits
111 1111 = Length is 128 x T Q
...
000 0000 = Length is 1 x T
Q
Note 1: These bits can only be modified in Configuration mode (OPMOD<2:0> = 100 ).

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Register 3-5: C1DBTCFGH: CAN Data Bit Time Configuration Register High
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BRP<7:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
— — — TSEG1<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 BRP<7:0>: Baud Rate Prescaler bits
1111 1111 = T
Q = 256/F SYS
...
0000 0000 = T
Q = 1/F SYS
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TSEG1<4:0>: Time Segment 1 bits (Propagation Segment + Phase Segment 1)
1 1111 = Length is 32 x T
Q
...
0 0000 = Length is 1 x T
Q
Note 1: This register can only be modified in Configuration mode (OPMOD<2:0> = 100).
Register 3-6: C1DBTCFGL: CAN Data Bit Time Configuration Register Low
(1)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — — TSEG2<3:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — —SJW<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 TSEG2<3:0>: Time Segment 2 bits (Phase Segment 2)
1111 = Length is 16 x T
Q
...
0000 = Length is 1 x T
Q
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 SJW<3:0>: Synchronization Jump Width bits
1111 = Length is 16 x T
Q
...
0000 = Length is 1 x T
Q
Note 1: This register can only be modified in Configuration mode (OPMOD<2:0> = 100).

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CAN FD Protocol Module
Register 3-7: C1TDCH: CAN Transmitter Delay Compensation Register High
(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — EDGFLTEN SID11EN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
— — — — — — TDCMOD1 TDCMOD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9 EDGFLTEN: Enable Edge Filtering During Bus Integration State bit
1= Edge filtering is enabled according to ISO11898-1:2015
0= Edge filtering is disabled
bit 8 SID11EN: Enable 12-Bit SID in CAN FD Base Format Messages bit
1= RRS is used as SID11 in CAN FD base format messages: SID<11:0> = {SID<10:0>, SID11}
0= Does not use RRS; SID<10:0>
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 TDCMOD<1:0>: Transmitter Delay Compensation mode bits (Secondary Sample Point (SSP))
10-11 = Auto: Measures delay and adds TSEG1<4:0> (C1DBTCFGH<4:0>); add TDCO<6:0>
01 = Manual: Does not measure, uses TDCV<5:0> + TDCO<6:0> from register
00 = Disables
Note 1: This register can only be modified in Configuration mode (OPMOD<2:0> = 100).

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Register 3-8: C1TDCL: CAN Transmitter Delay Compensation Register Low
(1)
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
— TDCO<6:0>
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— TDCV<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 TDCO<6:0>: Transmitter Delay Compensation Offset bits (Secondary Sample Point (SSP))
111 1111 = -64 x T
CY
...
011 1111 = 63 x T
CY
...
000 0000 = 0 x T
CY
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TDCV<5:0>: Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP))
11 1111 = 63 x T CY
...
00 0000 = 0 x T
CY
Note 1: This register can only be modified in Configuration mode (OPMOD<2:0> = 100).

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CAN FD Protocol Module
Register 3-9: C1TBCH: CAN Time Base Counter Register High
(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBC<31:24>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBC<23:16>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TBC<31:16> CAN Time Base Counter bits
This is a free-running timer that increments every TBCPRE<9:0> clock when TBCEN is set.
Note 1: The Time Base Counter (TBC) will be stopped and reset when TBCEN = 0to save power.
2: The TBC prescaler count will be reset on any write to C1TBCH/L (TBCPREx will be unaffected).
Register 3-10: C1TBCL: CAN Time Base Counter Register Low
(1,2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TBC<15:0> CAN Time Base Counter bits
This is a free-running timer that increments every TBCPRE<9:0> clock when TBCEN is set.
Note 1: The TBC will be stopped and reset when TBCEN = 0to save power.
2: The TBC prescaler count will be reset on any write to C1TBCH/L (TBCPREx will be unaffected).

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 18 2018 Microchip Technology Inc.
Register 3-11: C1TSCONH: CAN Timestamp Control Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TSRES TSEOF TBCEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2 TSRES: Timestamp Reset bit (CAN FD frames only)
1= At sample point of the bit following the FDF bit
0= At sample point of Start-of-Frame (SOF)
bit 1 TSEOF: Timesstamp End-of-Frame (EOF) bit
1= Timestamp when frame is taken valid (11898-1 10.7):
- RX no error until last, but one bit of EOF
- TX no error until the end of EOF
0= Timestamp at “beginning” of frame:
- Classical Frame: At sample point of SOF
- FD Frame: see TSRES bit
bit 0 TBCEN: Time Base Counter (TBC) Enable bit
1= Enables TBC
0= Stops and resets TBC
Register 3-12: C1TSCONL: CAN Timestamp Control Register Low
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — TBCPRE<9:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBCPRE<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 TBCPRE<9:0>: CAN Time Base Counter Prescaler bits
1023 = TBC increments every 1024 clocks
...
0= TBC increments every 1 clock

2018 Microchip Technology Inc. DS70005340A-page 19
CAN FD Protocol Module
Register 3-13: C1VECH: CAN Interrupt Code Register High
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— RXCODE<6:0>
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— TXCODE<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 RXCODE<6:0>: Receive Interrupt Flag Code bits
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (RFIF<31> is set)
...
0000010 = FIFO 2 interrupt (RFIF<2> is set)
0000001 = FIFO 1 interrupt (RFIF<1> is set)
0000000 = Reserved; FIFO 0 cannot receive
bit 7 Unimplemented: Read as ‘0’
bit 6-0 TXCODE<6:0>: Transmit Interrupt Flag Code bits
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (TFIF<31> is set)
...
0000001 = FIFO 1 interrupt (TFIF<1> is set)
0000000 = FIFO 0 interrupt (TFIF<0> is set)

dsPIC33/PIC24 Family Reference Manual
DS70005340A-page 20 2018 Microchip Technology Inc.
Register 3-14: C1VECL: CAN Interrupt Code Register Low
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — —FILHIT<4:0>
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 FILHIT<4:0>: Filter Hit Number bits
11111 = Filter 31
11110 = Filter 30
...
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits
1001011-1111111 = Reserved
1001010 = Transmit attempt interrupt (any bit in C1TXATIF is set)
1001001 = Transmit event FIFO interrupt (any bit in C1TEFSTA is set)
1001000 = Invalid message occurred (IVMIF/IE)
1000111 = CAN module mode change occurred (MODIF/IE)
1000110 = CAN timer overflow (TBCIF/IE)
1000101 = RX/TX MAB overflow/underflow (RX: Message received before previous message was
saved to memory; TX: Can't feed TX MAB fast enough to transmit consistent data)
(SERRIF/IE)
1000100 = Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
1000011 = Receive FIFO overflow interrupt (any bit in C1RXOVIF is set)
1000010 = Wake-up interrupt (WAKIF/WAKIE)
1000001 = Error interrupt (CERRIF/IE)
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (TFIF31 or RFIF31 is set)
...
0000001 = FIFO 1 Interrupt (TFIF1 or RFIF1 is set)
0000000 = FIFO 0 Interrupt (TFIF0 is set)