2Chapter 1. Introduction
output stage (ARF421/XRF421 only). The RF signals are monitored to
check output power and to measure the reflection (VSWR).
The DDS chips are controlled by the FPGA. A microcontroller provides
external interface with TCP/IP and USB communications, and controls
the front-panel display, rotary encoders (knobs) and push-buttons.
The device allows analogue modulation through two analogue-to-
digital converters (ADC) with anti-aliasing filters. When modulation
is configured, the FPGA periodically reads the digital value of the
modulation signal and uses that value to reprogram the DDS fre-
quency, power and/or phase.
The ARF/XRF includes memory for storing complex waveform se-
quences, where each step in the sequence can include frequency,
power, phase, time delay, and more complex definitions of ramps
and other time-dependent functions. Complex capabilities can be
accessed via either TCP/IP or USB communications. See Chapter 3
for information on communications options and setup.
Once communications are established, the ARF/XRF can be controlled
with simple text commands. The commands can be very basic, for
example to define the frequency or power, or they can define complex
dynamic sequences. Chapter 4 describes some example python code
for communicating with the device and for establishing a sequence,
and Appendix B provides a summary of the available commands.
1.1 Operating modes
The ARF/XRF can be used at varying levels of complexity, defined
in terms of operating modes. In normal mode, the ARF/XRF acts as
a simple single-frequency high-power RF source, controlled by the
front panel or computer commands.
In table mode, the RF output is determined by a table of commands
preloaded into internal look-up tables and stepped through auto-
matically on the basis of pre-defined delays, in combination with
