Nabu 1100 System Quick start guide

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The NABU 1100 System:
ATechnical Guide

•
•
NOTICE
Copyright @1981, Nabu Manufacturing Corporation, Ottawa, Canada.
Sections
of this manual have been reproduced with the permission of the
manufacturers involved; Intel Corporation, NEC Information Systems Inc., NEC
Microcomputers, Volker~Craig ltd., Western Digital, and ZiJog Inc.
Because
of our policy of constantly searching for ways to improve our products, all
specifications are subject
to change without notice .

DIRECTORY
1. INTRODUCTION
2. SYSTEM MAINTENANCE
3. THE COMPUTER -Manufactured by Nabu Corporation
4. THE KEYBOARD/TERMINAL -Manufactured by Volker-Craig Limited
5. THE PRINTER -Manufactured by NEe Information Systems Inc.

INTRODUCTION
The following technical manual for the Nabu 1100 System is designed to familiarize
you with the components, internal hardware, and capabilities of your new system.
Basically, the manual contains documentation from the manufacturers of the
system's components; such as Nabu, Volker-Craig, NEC, etc. It has been written for
the knowledgeable user, with additional information included for those at an
engineering level.
The computer itself, the keyboard/terminal, and the optional printer are the
components of your system. The computer is manufactured by Nabu, and comes
housed in aspecially designed moveable cabinet, with two drawers. The lower
drawer can be used for storage of diskettes etc., while the upper drawer contains
the hardware associated with the computer. The system features 64K user memory
capacity, and uses the Z-BOA microprocessing unit developed by Zilog. Total storage
capacity of the system is 2 Megabytes, with the use of floppy diskettes. As well, the
system provides interfaces for printer and controls.
The keyboard/terminal is manufactured by Volker-Craig, and is microprocessor
based; providing afull set of standard functions as well as avariety of options. The
non-glare screen can display up to 24 lines x80 characters (a total of 1920 character
positions). The keyboard is detachable and features afull set of punctuation and
special symbols, avariety of control keys, and a numeric keypad.
Printer options for the Nabu 1100 System include a NEC Spinwriter 5510/20, a NEC
3510120, or a Centronics printer. Although these three options are available, the
most common option is the NEe Spinwriter 5510/20, which is aJetter-quality printer
with a printing speed of up to 660 words a minute. The Spinwriter features an
interchangeable, rotating thimble which contains up to 128 fully formatted
characters, and has a color printing option.
Now that the system has been introduced and briefly described; the manufacturer's
documentation on the system components will follow. This information should help
you to understand, operate and maintain your system, in order to obtain the best
possible performance from itl

SYSTEM MAINTENANCE
Maintenance of your new computer system should be one of your most important
consideration, since proper maintenance can help avoid computer downtime and
costly repai
rs.
General maintenance of the system involves periodic checks of the hardware. This
preventive maintenance inspection should be done every six months by a qualified
service Technician.
Regular cleaning
should be done by the operator at least once a month as follows:
- vacuum under the system cabinet
-
vacuum paper dust out of printer
-clean cabinet, printer, and screen with any spray cleaner and asoft cloth. •
•NOTE: Spray
the cleaner only on the cloth, NOT ON THE EQUIPMENT.
The system cabinet
has been installed with rollers, for maneuverability when
cleaning etc. However, if the system is to be moved a long distance (to another
office building for example), we recommend you repack it in its original cartons, to
avoid damage.

The Computer
Manufactured by Nabu Corporation

DIRECTORY
INTRODUCTION
TABLE 1: IEEE 5-100 Bus Utilization
TABLE 2: Board Positions In Card Cage
Power Supply
FIGURE 1: System Power Supply Schematic
1.0: CPU
BOARD
General Information
Specific Features
CPU Board Parts List
FIGURE 2: Schematic Diagram
of CPU Board
FIGURE 3: CPU Board Layout
2.0: 64K
DYNAMIC MEMORY BOARD
General Information
Specific Features
Memory Board Parts List
FIGURE
4: Schematic Diagram of Dynamic Memory Board
FIGURE
5: Dynamic Memory Board Layout
3.0
INPUT/OUTPUT BOARD
General Information
Specific Features
Input/Output Board Parts List
FIGURE 6: Schematic
Diagram of Input/Output Board
FIGURE 7:
Input/Output Board Optional Circuit #1
FIGURE 8: Input/Output Board Optional Circuit #2
FIGURE 9: Input/Output Board Power Supply
FIGURE 10:
Input/Output Board Layout
4.0 FLOPPY DISK DRIVE CONTROLLER
BOARD
General Information
Specific Features
Floppy Disk Drive Controller Parts List
FIGURE 11: Schematic Diagram
of Floppy Controller Board
FIGURE 12:
Floppy Disk Controller Board Layout

e·
INTRODUCTION
Congratulations on the purchase of your new Nabu 1100 Computer; you have
invested
in asophisticated and reliable microprocessing unit. This system uses the
powerful Zilog Z-80A microprocessor chip, and is equipped with 2 double-sided,
double-density floppy Disk Drives. It features 64K user memory capacity; 62K of
which is designated as R/W memory, and 2K as RIO memory. Total storage capacity
for the system, using floppy diskettes, is 2Megabytes (1 Megabyte per Drive).
The system
is equipped with two RS-232C Serial 1/0 ports with programmable Baud
Rate. These I/O ports facilitate
the use of both aconsole and a printer; or any two
peripherals you may require. As well, aparallel output port is provided for the use
of the optional Centronics dot matrix printer. Another feature of the system is the
programmable timer, which can be used to implement areal time clock for the
system.
The
computer hardware is located in the upper drawer of the specially designed
cabinet.
Directly against the right side of the drawer as you open it are the Disk
Drives,
manufactured by Shugart. They feature low heat dissipation, improved access
time, capacity for single or double density recording on standard diskettes, and write
protection and programmable door lock for improved data security. The Shugart
Disk
Drive manual has been included for further information.
To the left of the Disk Drives is the card cage containing the printed circuit boards,
which plug into astandard 5-100 Bus. There have been some modifications to certain
pin functions, and these are indicated in the 5-100 Bus table included in the manual.
Attached
to the boards are the interconnecting cables used to interface between the
various components of the system. The four printed circuit boards (CPU. Memory,
Input/Output, and Floppy Controller) are described in detail in the manual, and
complete circuit diagrams for each board have been included.

TABLE ~ l!BE 6-100 allS UTILIZATION
PIN t
SIGNAL NAME
IMPLEMENTATION
-----------------------------------------------------------------
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
tt ~~
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
+8
Volts
+16 Volts
XRDY (S)
V10*(S)
V11*{S)
VI2*(S)
VI3*(S)
VI4*(S)
VI5*(S)
V16*(S)
VI7*(S)
NM1*(S)
PWRFAIL* (B)
DMA3* (M)
A18 (M)
A16 (M)
Al7 (M)
SDSB* (M)
CDSB* (M)
GDN (B)
NDEF
ADSB* (M)
DODSB*(M)
(J (B)
pSTVAL* (M)
pH LOA (M)
PWAIT
RFU
A5 (M)
A4 (M)
A3 (M)
Al5 (M)
Al2 (M)
A9 (M)
DOl (M)
000 (M)
A10 (M)
004 (M)
005 (M)
D06 (M)
DI2 (8)
013 (5)
017 (5)
sMI
(M)
sOUT (M)
sINP (M)
sMEMR (M)
sHLTA (M)
CLOCK (B)
GND (B)
Power supply
Power supply
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Implemented but not used
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Disables the 8 status signals
Disables the 5 control output signals
Ground (not implemented)
Not to be defined
Disables the 16 address signals
Disables the 8 data output signals
Master tim1ng signal
status valid strobe
Hold control signal
Indicates processor is in wait state
Reserved for future use
Address bit 5
Address bit 4
Address bit 3
Address bit 15
Address bit 12
Address bit 9
Data out bit 1
Data out bit 0
Address bit 10
Data out bit 4
Data out bit 5
Data out bit 6
Data in bit 2
Data in bit 3
Data in bit 7
Op-code fetch status signal
Transfer status signal
Transfer status signal
Memory read status signal
HLT aCKnowledge
2 MHz (O.5%) 40-60% duty cycle
Ground

51
52
53
54
55
56
57
58
59
60
61
62
63
t
64
65
+66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
tt
97
98
99
100
+8 Volts (B)
-16 Volts (B)
GND (B)
SLAVE CLR*(B)
DMAO* (M)
DMAl*(M)
DMA2* (M)
sXTRQ* (M)
A19 (M)
SIXTN*(S)
A20 (M)
A21 (M)
A22 (M)
A23 (M)
MREQ
MRFSH
PHANTOM * (M/ S)
MWRT (B)
RFU
GND (B)
RFU
ROY (S)
INT*(5)
HOLO*(M)
RE5ET*(B)
pSYNC (M)
pWR* (M)
pOBIN (M)
AO (M)
Al (M)
A2 (M)
A6 (M)
A7 (M)
A8 (M)
A13 (M)
A14 (M)
All (M)
002 (M)
003 (M)
007 (M)
014 (5)
DIS (S)
016 (5)
011 (5)
010 (5)
sINTA (M)
sWO*(M)
FREQ
POC*(B)
GNO (B)
Power
supply
Power supply
Ground (not implemented)
Reset bus slaves
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Not implemented
Memory request
Memory refresh
Enables phantom slaves
Memory write
Reserved for future use
Ground (not implemented)
Reserved for future use
Ready input
Primary interrupt request
HOLD control signal
Resets bus master devices
Control signal identitying BSl
Data bus control signal
Data in control signal
Address bit 0
Address bit 1
Address bit 2
Address bit 6
Address bit 7
Address bit 8
Address bit 13
Address bit 14
Address bit 11
Data out bit 2
Data out bit 3
Data out bit 7
Data in bit 4
Data in bit 5
Data in bit 6
Data in bit 1
Data in bit 0
Interrupt status signal
Data out status signal
Status signal for 4 MHz clock
Power-on clear signal
Ground
tThese signals are not defined in the standard but are used in
the system for the Z-80A microprocessor memory control signal.
ttThese signals are non-standard

TABLE 2...i.. BQARDPQSITIONS .IN ~ ~
1. Empty
2. FLOPPY DISK CONTROLLER BOARD
3. INPUT/OUTPUT BOARD
4. Empty
5. CPU BOARD
6. Empty
7. MEMORY BOARD
8. Empty
NOTE: Positions indicated are numbered from left to r1ght as
viewed from the front of the cabinet.

POWER SUPPLY
The 53 power supply (from Sunny International) is an open-
frame module located behind the two drives in the top drawer of
the Nabu system. It provides unregulated +8, +16, and -16 volts
for the 5-100 bus and regulated +5, -5 and +24 volts for the disk
drives. It consists of four major components: transformer,
rectifiers, filter capacitors, and regulators.
The transformer primary has two llOV windings. They are
connected in parallel for use with a llOV supply, and in series
for use with a 220V supply.
SPECIFICATIONS;
INPUT:
OUTPUT:
110 Volts AC, 60 Hz, single phase
Unregulated: +8 Volts @ 14A, +16 Volts @ 3A, -16 Volts @ 3A
RegUlated: +5 Volts @ 4A, -5 Volts @ lA, +24 Volts @ 4A

k.Q. CPU--BOARO
GENERAL INFORMATION
The Nabu ACP-llOl CPU Board is designed to bring the full
power of the Zilog Z-80A microprocessor to the 5-100 bus. The
CPU board has provision for up to three 2716 type EPROM's (for a
total of 6K bytes), and two 2114 type static RAM's (for a total
of lK bytes). The base address of this memory block can be set
using on-board jumpers. The board also performs an automatic
jump to a user selected memory address on system start-up or
reset. The clock frequency of the main processor is also
selectable between 2 and 4MHz. When the 4 MHz clock frequency
is used, the board automatically inserts one wait state when the
on-board EPROM or RAM is accessed.
When used in the Nabu 1100 computer system, the board
operates at a 4 MHz clock rate, with one 2716 EPROM and two 2114
RAMls addressed from F800H to FFFFH.

SPECIFIC FEATURES
Clock Frequency Selection
The Nabu ACP-llOl may be clocked either at 4 MHz or 2 MHZ.
The operating frequency is selectable with Jumper 8 (JP-8).
(Please refer to the board layout for the location of all
jumpers). Connecting this jumper sets the operating clock
frequency to 2MHz. The standard CPU card is shipped with the
jumper disconnected and runs reliably at 4 MHz.
Pin 98, labelled as FREQ, on the 5-100 bus, is used by the
Nabu system as an indicator line for the operating frequency.
For 4 MHz operation the line will be high; for 2 MHz it is low.
Automatic Power-On JYmB
When system power is turned on, or a reset signal is
received, the CPU jumps to one of two hundred and fifty-six
possible memory locations. The jump address is selected by the
eight address jumpers JP-9 to JP-16. Only the eight most
significant address bits (A15 -A8) are used to decode the jump
address. The eight least significant address bits (A7 - AO) are
taken as logic 0 as shown on the next page.
Power-On Jump Address:
t
LA? -AO, always at logic 0
---------A15 - AS, selected by user
The standard Nabu CPU board has the power-on jump address
set at FCOOR (jumpers JP-15 and JP-16 installed).
On~Board Memory Selection
The Nabu CPU board offers a maximum of six kilo-bytes of on-
board memory, which consists of three 2K x 8 (2716 type) EPROM's
and two lK x 4 (2114 type) static RAM'S. IC sockets are prov~ded
on the board for the memory chips.

The memory address for the on-board EPROMls and RAM's are
grouped as a block. Within the block, the individual memory
chips are allocated as follows:
Base + 2000H
ROM 1*
Base +leOOH
RAM I / RAM 2
Base + 1800H
ROM 3
Base + 1000H
ROM 2
Base +800H
NOT ASSIGNED
Base of Block
*On1y the upper lK of ROM 1 is used.
The RAM is configured as 1024 x 4 bits (2114 type). RAM 1
stores data bits DO, 07, 06, and 05; and RAM 2 stores data bits
04, 03, 02, and D1.
The base address of the block is set by jumpers JP-l through
Jp-3. The three most-significant address bits are used to set
the address of the block. Table 1 (on the following page), lists
the possible base addressses of the block corresponding to each
jumper connection.
JUMPERS (JP)
STARTING ADDRESS (IN HEX) OF:
ROM 2 ROM 3
RAM l/RAM 2
ROM 1
------------------------------------------------
0800 1000 1800
ICOO
2800
3000 3800
3eOO
4800
5000
5800 seoo
6800
7000 7800
7eOO
8800
9000 9800 geOa
A80D BOOO
B800
BCaO
e800 0000 0800
DCaa
E80D
FOOD
F800
FeOD
--- J
'I' represents 'Jumper is connected'
.0
1
represents 'Jumper is disconnected'
I23
--------------
a00
00I
aIa
0I1
1a a
1a1
I1Ia
l1 1 1
-------------
TABLE 1.1. Jumper Connection AM starting Address .Q! Memory

The enabling of these memory chips is done by connecting
jumpers JP-5, JP-6, and JP-7 in the selection area S-l. JP-5
enables ROM 2, JP-6 enables ROM 3, and JP-7 enables ROM 1 and
RAM 1/ RAM 2, as seen in the figure below. (Note that ROM 1 and
RAM 1/ RAM 2 are enabled together, and so both must be used
together) •
Selection o0o0o0o0
Area S-1
o0o000o0
Jumpers (JP)
56 7
IlL
~--connected
to
enable ROM
1/
RAMls
connected
to enable ROM
3
.connected
to enable ROM 2
In addition, enabling on-board RAM's and EPROMls renders any
external devices or memory at the selected address-blocK
inaccessible to a read instruction. HoweverIawri te operation
will write into all devices located there.
The standard Nabu ACP-lIOI is shipped with the following
memory setting:
Jumpers (JP) 1 2 3
Selection
Area 5-1
Irr o
o
o
o
5
o
o
6r
7
o
o
The memory map corresponding to the standard setting would
be:
FFFF
FCOO
F800
FOOO
E800
-----------------------i
ROM 1
-- --------------------
---~~_:_~-~~~-~----j
NOT SELECTED
- --------------------
NOT SELECTED
-----------------------

When both the 4 MHz operating frequency, and the on-board
EPROM's and RAM's are chosen, (as in the standard Nabu ACP-IIOl
setting), one wait-cycle is automatically inserted by the CPU
logic circuitry.
Refxesh Enable
Dynamic RAM's periodically require a refresh to maintain the
data stored within the memory cell. The Nabu CPU board brings
the memory-refresh signal from the Zilog Z-80A microprocessor to
the S-100 bus. Pin 66 on the 8-100 bus is designated by Nabu as
the memory-refresh signal, RF8H. The memory request signal from
the Z-80A processor is also brought out to the 8-100 bus. Pin 65
(named as MREQ), is used to indicate a valid memory address on
the address bus.

~ ACP-IIOI ~ BOARD
PARTS .L..I.S.:r
Integrated Circuits
U1-U4
2114
V5
74LS136
U6
74LS42
V7
74LS20
U8,
V9, V28,
V30-U34 74LS241
UI0 74LS175
VII
74LS123
U12, U17, U20,
U23,
V24
V13
U14, V21
U15
U16
V18
U19
U22, U25, U35
U26
U27
U29, U36
U37, U38
ROM1-ROM3
Transistors:
Q1
Q2
Diodes:
01, 02
Capacitors;
74LS74
74LS132
74LS04
74LSOB
74LS32
Z-80A-CPU
74LS157
74LS02
74LS367
74LS14
74LS368
7805
2716
2N4124
2N4126
IN914A
1024 x 4-bit NMOS static RAM
Quadruple 2-input NOR with open-
collector outputs
4-line-to-lO-line decoder
Dual 4-input NAND
Octal buffer/line-driver witn 3-state
outputs
Quadruple D-type flip-flop
Dual retriggerable monostable
multivibrator with clear
Dual D-type rising-edge-triggered flip-
flop with preset and clear
Quadruple 2-input NAND with Schmitt-
triggered inputs
Hex inverter
Quadruple 2-input AND
Quadruple 2-input OR
Central processing unit (4 MHz)
Quadruple 2-line-to-l-line multiplexer
Quadruple 2-input NOR
Hex non-inverting bus-driver
Hex inverter with Schmitt-triggered
inputs
Hex inverting bus-driver
5 V positive voltage regulator
2716 EPROM with bootstrap program
NPN silicon transistor
PNP silicon transistor
Silicon switching diode
CI-CIO, CI3-CI5,
C19-C24, C25,
C26, C30,
C31
CIl, C18
C12
C16, C27-C29
C17
0.1 pF
33 pF disc
22 pF, 16 V tantalum electrolytic
10 ~F, 16 V tantalum electrolytic
10 nF

Resistors:
Rl, R2
R3, RS-R7, R11
R4
R8
R9
RIO
RNI-RN3
Crystal:
XTAL
Quantity
16
7
4
8
3
1
1
6
6
1
10 kf\.
1 k J"'L
100J\..
220 J\.
22 1l.
100 kA
9-resistor pack of 1 k~resistors with
common pin #1
8.000 MHz parallel-resonant
Descriptioo
14 pin socket
16 pin socket
18 pin socket
20 pin socket
24 pin socket
40 pin socket
Delta 680-0.5-220 Heatsink
#6-32 x 3/8" machine screw
#6-32 nuts
p.c. board

~:
The following 11 pages have been reproduced by perm1ssion
of Zilog, Inc. © 1979, 80, 81. This material shall not
be reproduced without the written consent of Zilog, Inc.
Z-80A is a trademark of Zilog, Inc., with whom the
publisher is not associated.