National Instruments ISO5851 User manual

User's Guide
SLLU218–June 2015
ISO5851 Evaluation Module
The manual describes the ISO5851 Evaluation Module (EVM). The ISO5851 EVM allows designers to
evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in
either of the standard TO-247 or TO-220 packages.
Warning: Note that although these devices provide galvanic isolation of up
to 5700-V, the EVM cannot be used for isolation voltage testing. Voltage
exceeding the EVM’s ratings (VCC1 > 5.5-V, VCC2 – VEE2 > 30-V, or IGBT
Collector-Emitter Voltage VCE > 50-V) can damage the EVM resulting in
personal injury.
Contents
1 Overview...................................................................................................................... 2
2 EVM Setup and Precautions ............................................................................................... 3
2.1 Power Supply Connections........................................................................................ 3
2.2 Signal Connections................................................................................................. 4
3 Example Measurements .................................................................................................... 5
4 Printed-Circuit Board ........................................................................................................ 8
4.1 ISO5851 Operation................................................................................................. 8
4.2 ISO5851 EVM Bill of Materials .................................................................................. 11
List of Figures
1 ISO5851 EVM Power Supply Schematic................................................................................. 3
2 Output Power Supply for Unipolar (Left) or Bipolar (Right) Operation................................................ 3
3 ISO5851 EVM Signal Path Schematic.................................................................................... 4
4 ISO5851 EVM Input and Output With Unipolar Output Supply........................................................ 5
5 ISO5851 EVM Input and Output With Bipolar Output Supply (VCC2 = 15-V, VEE2 = –8-V) .......................... 6
6 ISO5851 EVM DESAT and Reset with Unipolar Output Supply....................................................... 6
7 ISO5851 EVM DESAT and Reset with Bipolar Output Supply ........................................................ 7
8 ISO5851 EVM ............................................................................................................... 8
9 To have different Turn-on and Turn-off................................................................................... 9
List of Tables
1 Test Points .................................................................................................................. 10
2 Bill of Materials ............................................................................................................. 11
All trademarks are the property of their respective owners.
1
SLLU218–June 2015 ISO5851 Evaluation Module
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Overview www.ti.com
1 Overview
The ISO5851 is a 5.7-kVRMS, reinforced isolated, IGBT gate driver with 2.5-A source and 5-A sink currents.
The primary side operates from a single 3-V to 5.5-V supply. The output side allows for a supply range
from minimum 15-V to maximum 30-V. Two complementary CMOS inputs control the output state of the
gate driver. The short propagation time assures accurate control of the output stage.
An internal desaturation detection recognizes when the IGBT is in an overload condition. Upon a
desaturation detect, the gate driver output is driven low to VEE2 potential, turning the IGBT immediately off.
When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the
primary side low and blocking the isolator input. The FLT output condition is latched and can be reset
through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp
to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink
across a low impedance path preventing IGBT to dynamically turned on during high voltage transient
conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits
monitoring the primary and secondary supplies. If either side have insufficient supply, the RDY output
goes low, otherwise the output is high.
2ISO5851 Evaluation Module SLLU218–June 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

TB2
PSU
VCC2
VEE2
GND2
VCC2
TB2
PSU
VCC2
VEE2
GND2
VCC2
VEE2
www.ti.com EVM Setup and Precautions
2 EVM Setup and Precautions
2.1 Power Supply Connections
Figure 1 illustrates the EVM power supply schematic.
Figure 1. ISO5851 EVM Power Supply Schematic
The primary side of the EVM (VCC1) operates from a single 3-V to 5.5-V power supply and connected via
TB3. Test point (TP8) is available for monitoring the primary power supply.
The EVM provides connections for evaluating the output side (VCC2, VEE2) with either a bipolar or unipolar
power supply, from a minimum 15-V to maximum 30-V. For unipolar operation, connect VEE2 to GND2
through a wire-bridge between pin 2 and pin 3 of TB2, as shown in Figure 2. VCC2 and VEE2 can be
monitored via TP17 and TP19, respectively.
Figure 2. Output Power Supply for Unipolar (Left) or Bipolar (Right) Operation
3
SLLU218–June 2015 ISO5851 Evaluation Module
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

VCC1
VCC1
VEE2
VCC1
EVM Setup and Precautions www.ti.com
2.2 Signal Connections
Figure 3 illustrates the ISO5851 EVM signal path schematic.
Figure 3. ISO5851 EVM Signal Path Schematic
2.2.1 I/O Connections
Figure 3 shows the signal path schematic of the EVM. JMP1 allows for stimulus or monitoring of the
device I/O pins IN+, IN-, RDY, FLT, and RST. Test points 1, 2, 3, 4, and 5 provide additional access to the
I/O pins. The EVM comes populated with 10-kΩpullup resistors (R1, R2) on the RDY and FLT pins, as
well as 220-pF capacitors (C4, C5) to GND1 for noise filtering.
2.2.2 Output and Loading
The EVM comes populated with a 1-nF load (C12) on the output side. The output can be monitored
directly via TP12. A 10:1 resistor-divider network is provided for monitoring the output with a low-voltage
probe via TP20. The divider circuit can be disconnected from the output by removing the shunt on JMP5.
10-Ωgate resistors (R3, R12) control the rise and fall times of the output. These resistors can be modified
by the user to alter the turn-on and turn-off characteristics of the output.
The EVM also allows for evaluation of the device with an IGBT load in either of the standard TO-247 or
TO-220 footprints. During evaluation with an IGBT load, the pre-installed capacitive load (C12) can be
disconnected from the output by removing the shunt on JMP2.
The EVM provides an additional connection (P2) for applying an external power supply to the IGBT
Collector. The EVM is not intended for high voltage testing and the voltage applied to P2 should be limited
to 50-V DC.
When evaluating the device with an IGBT load using P2, the components D1, D2, R7, and C13 should be
populated with their default values, specified in Figure 3. Additionally, ensure that the DESAT pin is not
connected to GND2 when driving an IGBT load using P2, either by removing R8, or verifying that all
jumpers are removed from JMP3.
4ISO5851 Evaluation Module SLLU218–June 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Example Measurements
2.2.3 DESAT
The EVM comes populated with a 220-pF DESAT capacitance. Pin1 on JMP3 can be used to apply a
signal directly to the DESAT pin.
For evaluation with the default 1-nF load, when actual IGBT is not connected as load, the desaturation
function should be disabled by connecting the DESAT pin to GND2 by shunting pin 1 to pin 2 on JMP3.
2.2.4 CLAMP
By default, the CLAMP pin is connected to the output via a 0-Ωresistor (R6). The CLAMP feature can be
disabled by removing R6. CLAMP can be monitored via TP14, and a signal can be applied directly to the
CLAMP pin via JMP4.
3 Example Measurements
Figure 4 illustrates measurements performed under the default EVM configuration. For these
measurements, VIN- is connected to GND1.
Figure 4. ISO5851 EVM Input and Output With Unipolar Output Supply
Figure 4 shows the input and output of the ISO5851 EVM for a 100-kHz clock with RG= 10 Ω(R3) and
R12 = 10 Ωand a unipolar output supply (VCC2 = 15-V, VEE2 = GND2). The output is measured at TP12.
5
SLLU218–June 2015 ISO5851 Evaluation Module
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Example Measurements www.ti.com
Figure 5 shows the input and output of the ISO5851 EVM for a 100-kHz clock with RG= 10 Ω(R3) and
R12 = 10 Ωand a bipolar output supply (VCC2 = 15-V, VEE2 = –8-V).
Figure 5. ISO5851 EVM Input and Output With Bipolar Output Supply (VCC2 = 15-V, VEE2 = –8-V)
Figure 6 with Unipolar Output Supply and Figure 7 with Bipolar Output Supply, shows the functionality of
the DESAT, FLT, and RST pins. IN+ is set to 5-VDC, and an 10-µs pulse is applied to RST. On the rising
edge of RST, the fault is cleared and the DESAT capacitor begins to charge. As the DESAT pin reaches
the DESAT threshold voltage, a fault is triggered on FLT, and the output goes into active turn-off. RST
must be toggled low, then high to reset the device, and the cycle begins again.
Figure 6. ISO5851 EVM DESAT and Reset with Unipolar Output Supply
6ISO5851 Evaluation Module SLLU218–June 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

www.ti.com Example Measurements
Figure 7. ISO5851 EVM DESAT and Reset with Bipolar Output Supply
7
SLLU218–June 2015 ISO5851 Evaluation Module
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Printed-Circuit Board www.ti.com
4 Printed-Circuit Board
The ISO5851 is an isolated gate driver with several important features. The printed-circuit board
(PCB)/EVM, as shown in Figure 8 ISO5851 EVM, has been designed to support the ISO5851 device and
to allow the user to evaluate its basic operation and features. The left side of the PCB contains the
interface to the input, control, and status functions of the integrated circuit (IC). The right side of the PCB
has been designed to interface to an IGBT. No electrical connections exist between the right and left sides
of the PCB.
Figure 8. ISO5851 EVM
Refer to the ISO5851EVM schematic shown in Figure 3 and the bill of materials given in Table 2, to
become familiar with the PCB components and layout.
The following table pertains to the labels on the EVM board (Figure 8):
Given Read As
VCC1 VCC1
VCC2 VCC2
VEE2 VEE2
VCE VCE
VIN+ IN+
VIN– IN–
/FAULT FLT
4.1 ISO5851 Operation
4.1.1 Left-Side Operation: DC Power, Control, and Status
4.1.1.1 DC Input Power
The left side of the ISO5851 (and therefore the PCB) can be operated using either a +3-V (±10%) to +5.5-
V (±10%) dc power supply. As the current requirement is extremely low, the user can choose to operate
the ISO5851 EVM by battery. The dc power supply must be connected to the TB3 terminal having VCC1
(+5.5-V DC) and GND1 (+5.5-V DC return).
8ISO5851 Evaluation Module SLLU218–June 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated

(As Shipped)
10 :
R3
R12
D4
OUT
Turnon/Turnoff
is Same
10 :
10 :
R3
R12
D4
OUT
To Change
Turnon and Turnoff
by R3 and R12
www.ti.com Printed-Circuit Board
4.1.1.2 Control and Status
The interface to the device is via the JMP1 header. It contains the IN+ and IN– inputs, the device RST,
RDY, and FLT indicator output. The JMP1 header allows easy connections to test equipment using
standard clip leads. Each of the five signals also has a test point for additional connections. These are test
points TP1–TP5.
4.1.2 Right-Side Operation
4.1.2.1 DC Output Power
Power is provided to VCC2 on the right side of the device at TB2 terminal as shown in Figure 2. The dc
supply must be able to provide a bias voltage over the range of +15-V DC to +30-V DC. As the current
requirement is extremely low, the user can choose to operate the ISO5851 EVM by battery. If a negative
gate drive is required, a dc supply (or battery) must be connected across VEE2 at the TB3 terminal as
shown in Figure 2. The voltage range must be between 0-V and 15-V DC.
4.1.2.2 DESAT – JMP3
One of the features of the ISO5851 is the IGBT desaturation protection. JMP3 provides access to the
DESAT pin. It is a 3-pin male header, and installing a shorting jumper between pin 1 and pin 2 on JMP3
disables the DESAT function.
4.1.2.3 Load
As shipped, the ISO5851EVM does not have an IGBT installed. The user can evaluate device operation
using a capacitive load of 1nF provided on EVM or capacitive load can be removed and IGBT can be
connected onto the board. Most IGBTs are available in the standard TO-247 or TO-220 package. The
PCB has provisions to solder an IGBT directly onto the board.
4.1.2.3.1 No IGBT Installed – JMP2
When using the capacitive load, the user must install a jumper short onto JMP2. It connects a 1-nF
capacitor (C12) to the OUT pin. The capacitive consists of the 10-Ωgate resistor (R3) and the 1-nF
capacitor (C12).
4.1.2.3.2 IGBT Installed – REMOVE JMP2
If the user chooses to install an IGBT, JMP2 must be left open with no shorting jumper installed. The PCB
has been designed with plated-through holes (or vias) as Q1 and Q2 shown on the schematic for IGBT
connections.
4.1.2.4 Turn-on and Turn-off Adjust
The PCB contains10-Ωgate resistor (R3), D4 diode, and 10-ΩR12 resistor. It allows the user to evaluate
device operation with different turn-on and turn-off characteristics. It is shown in Figure 9.
Figure 9. To have different Turn-on and Turn-off
9
SLLU218–June 2015 ISO5851 Evaluation Module
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Printed-Circuit Board www.ti.com
4.1.3 Test Points
Test points have been provided for ready access to signal monitoring and are listed in Table 1.
Table 1. Test Points
Test Points I/O Function
TP1 Input IN+ (Side 1)
TP2 Input IN– (Side 1)
TP3 Output RDY (Side 1)
TP4 Output FLT (Side 1)
TP5 Input RST (Side 1)
TP6 Ground GND1 (Side 1)
TP7 Ground GND1 (Side 1)
TP8 Supply VCC1 (Side 1)
TP9 Ground GND1 (Side 1)
TP10 Input COLLECTOR VOLTAGE (Side 2)
TP11 Input EMITTER VOLTAGE (Side 2)
TP12 Output GATE VOLTAGE (Side 2)
TP13 Input DESAT (Side 2)
TP14 Input CLAMP (Side 2)
TP15 Ground GND2 (Side 2)
TP16 Ground GND2 (Side 2)
TP17 Supply VCC2 (Side 2)
TP18 Ground GND2 (Side 2)
TP19 Supply VEE2 (Side 2)
TP20 Output OUT (Side 2)
P1 Ground GND2 (Side 2)
P2 Input COLLECTOR VOLTAGE (Side 2)
10 ISO5851 Evaluation Module SLLU218–June 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated