National LMH6517 User manual

www.national.com
Rev 2.2
September 2009
SP16160CH1RB
High-IF Receiver Reference Design Board
LMH6517 ADC16DV160 LMK04031B
User’s Guide
1.0 Reference Board Overview 2
2.0 Evaluation Kit Contents
3.0 System Description
.0 Data Capture 5
5.0 Quick Start 5
6.0 Functional Description 7
7.0 System Performance 11
8.0 Device Configuration 13
9.0 Optional Hardware Configurations 17
10.0 Schematic 19
11.0 Layout 23
12.0 Bill of Materials 29

SP16160CH1RB Reference Design Board User’s Guide
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1.0 Reference Board Overview
Figure 1: SP16160CH1RB board (front side)
SMA_AMP_I:
In-Phase
Analog Input
ADC
16DV160
VCXO
(76.8 MHz)
Reference
Crystal
Oscillator
(61.44 MHz)
LMK
04031B
Low Noise
Regulators
H3: uWire
Header
LMH
6517
JP1
FutureBus
Connector
5.0V
Power
Connector
SMA_AMP_Q:
Quadrature
Analog Input
SAW &
Clock
Buffer
Manual DVGA
Gain Control (Optional)

SP16160CH1RB Reference Design Board User’s Guide
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Figure 2: SP16160CH1RB board (back side)
Switching
Regulators
Varactor
Controlled
Crystal XO
(Optional)

SP16160CH1RB Reference Design Board User’s Guide
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2.0 Evaluation Kit Contents
The SP16160CH1RB evaluation kit includes the
following items:
• SP16160CH1RB reference design board
• PIC microcontroller board (ADC1 PIC REV. A)
The SP16160CH1RB reference board is fully
assembled for immediate evaluation. A PIC
microcontroller board is included with the evaluation kit
to properly configure the on-board clock solution.
The following items are required to evaluate the
SP16160CH1RB but NOT included in the evaluation
kit. See section 5.0 Quickstart for more information.
• Signal generator and connecting cables
• +5V, 1A power supply and cable
• Data capture hardware and analysis software
3.0 System Description
The SP16160CH1RB is a high IF receiver reference
design board that utilizes the following components
from National Semiconductor:
• ADC16DV160 A dual channel, 16-bit, 160 MSPS
(Megasamples-per-second) analog-to-digital
converter (ADC) with parallel LVDS outputs.
• LMH6517 A high performance, dual channel
digitally controlled variable gain amplifier (DVGA)
with a 31.5 dB gain range in 0.5 dB steps.
• LMK04031B A clock conditioning solution
composed of a low-noise jitter cleaner, clock
multiplier, and clock distribution stage.
• Several energy-efficient power management ICs
including the LM2734 switching regulator and the
LP3878-ADJ and LP5900 low drop-out (LDO)
regulators.
Figure 3: SP16160CH1RB block diagram
VRM
CLK
153.6 MHz
CMOS
Sampling
Clock
SP16160CH1RB Reference Board
PLL1 External
Loop Filter
Components
76.8 MHz
Voltage Controlled
Crystal Oscillator
CLK-
ADC16DV160
DVGA – I
LMH6517
1:4
LMK04031B
PLL2 External
Loop Filter
Components
61.44 MHz
Crystal Oscillator
Reference
153.6 MHz
SAW Filter
LM2734 LP3878-ADJ
LM2734 LP3878-ADJ
LP5900
LP5900
LP3878-ADJ
VA 3.0V
VA 1.8V
VPLL 3.3V
VD 1.8V
VXO 3.3V
5V
Low Noise
CMOS
Buffer
6-bit Gain
Control
DVGA – Q ADC – Q
ADC – I
FutureBus Connector
16-bit, 8-lane
DDR Interleaved
LVDS Digital Data
16-bit, 8-lane
DDR Interleaved
LVDS Digital Data

SP16160CH1RB Reference Design Board User’s Guide
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As shown in block diagram of Figure 3, this subsystem
reference design provides single-to-differential
conversion, digitally controlled gain, bandpass filtering
of dual channel input signals and high dynamic range
digitization. The low-noise optimized clock path
provides a 153.6 MHz low-jitter, single-ended CMOS
sampling clock for the ADC.
The measured system performance demonstrates an
Nyquist band SNR of 72 dBFS for a -3 dBFS, 192 MHz
input signal and SFDR greater than 85 dBFS for single
tone input frequencies between 182 and 202 MHz and
a sampling frequency of 153.6 MSPS.
This reference design enables immediate evaluation of
a high dynamic range, high-IF sampling application
such as a wireless communications sampling receiver
subsystem.
4.0 Data Capture
The digital data from the SP16160CH1RB reference
design board can be captured with a suitable
instrument, such as a logic analyzer, or with National
Semiconductor’s WaveVision signal path data
acquisition hardware and software platform. The
SP16160CH1RB board is connected to the data
acquisition hardware through the FutureBus connector
(schematic reference designator H ).
The SP16160CH1RB is compatible with National
Semiconductor’s WaveVision 5.1 Signal Path Digital
Interface Board and associated WaveVision 5
software. Please note that the SP16160CH1RB board
is not compatible with previous versions of the
WaveVision hardware (WaveVision .x Digital Interface
Boards).
The WaveVision hardware and software package
allows fast and easy data acquisition and analysis. The
WaveVision hardware connects to a host PC via a USB
cable and is fully configured and controlled by the latest
WaveVision software. The latest version of the
WaveVision 5 software and information about the
WaveVision 5.1 Signal Path Digital Interface hardware
(part number: WAVEVSN BRD 5.1) are available
through the National Semiconductor website at
http://www.national.com/analog/adc.
5.0 Quick Start
5.1 WaveVision Software and Hardware Installation
• Begin by installing the latest version of WaveVision
5 and be sure to enable the update manager to
keep up to date with the most current version. Do
not start the WaveVision software application at
this point.
The WaveVision software must be installed
before connecting the WaveVision hardware.
Figure : Connection diagram for the SP16160CH1RB board and WaveVision 5.1 data capture hardware