NEC NEC MultiSync LCD1550X LCD1550X LCD1550X User manual

SERVICE MANUAL
LCD DISPLAY
LCD1550X / LCD1550X-BK
NEC-MITSUBISHI ELECTRIC VISUAL SYSTEMS CORPORATION
DECEMBER 2001
CBB-S5765 Rev A

ii
Changes
Following changes are added to Adjustment Procedure
1) 1 PC available for DVI-PC is added to 2 2 Measurement
instrument used
2) Configuration of DVI-I input connector (VIDEO) men-
tioned in 2 4 3 Configuration of signal input/power input
section is revised
3) The check item <Swivel> is added to 2 5 2 Mechanism
and appearance inspection
4) Note 1) is added to 2 6 1 Preparation
5) BRIGHTNESS MAX value of the setting state is changed
to 220 from 255 in 2 6 1 Preparation
6) Some confirmation items are added to 2 6 1 1 Confirming
operation of operation SW and functions
7) ADC MAX value is specified in 2 6 2 1 Confirming OSM
picture during heat running
8) 2 6 2 1 Confirming OSM picture during heat running is
revised
9) EDID DATA DUMP TEXT is newly entitled as 2 7 Con-
figuration of DDC (EDID) data
10)2 7 1 10 Power voltage fluctuation and 2 7 1 11 Power
asynchronous swing are deleted
11)The table in 2 8 2 1 Picture performance inspection is
revised
12)The picture and the table in 2 8 2 3 Panel inspection is
modified
13)2 9 3 Standards for display conditions is revised
14)BRIGHTNESS MAX value in 2 10 1 OSM default setting
is changed to 220 from 255
15)The table <Factory mode> in 2 12 OSM display matrix is
modified
Rev.A: 2/6/2002

iii
Contents
1 Circuit description 1-1
1 1 Power circuit 1-1
1 2 Detailed description of each circuit 1-2
1 2 1 Pseudo-resonance circuit method 1-2
1 2 2 Switching circuit operation 1-3
1 2 3 Description of operation 1-4
1 2 4 Protection circuit 1-6
1 2 4 1 Latch circuit 1-6
1 2 4 2 Overheat protection circuit 1-6
1 2 4 3 Overvoltage protection circuit 1-7
1 3 PWB-MAIN basic specifications 1-8
1 3 1 Basic specifications 1-8
1 3 2 PWB-MAIN circuit block diagram 1-9
1 3 3 Input/output connector pin assignment 1-10
1 4 Video input signal specifications 1-11
1 4 1 Video interface peripheral circuit 1-12
1 4 2 Horizontal/vertical synchronizing signal input circuit 1-13
1 4 3 Composite sync V separation circuit 1-14
1 4 4 Sync On Green synchronization separating circuit 1-15
1 4 5 TMDS receiver 1-17
1 4 6 Input signal presence judgment function 1-18
1 4 7 Input signal switching control function 1-21
1 5 DDC interface peripheral circuit 1-24
1 5 1 DDC switching control function 1-25
1 5 2 DDC2BI/DDC CI function (only DVI-I connector side) 1-28
1 5 3 EDID data write protect control function 1-29
1 6 Power peripheral circuit 1-30
1 6 1 DC/DC converter and panel power specifications 1-31
1 6 2 DC/DC output voltage design sheet 1-32
1 6 3 Power rising/falling edge sequence control function 1-37
1 6 4 Reset circuit 1-39
1 7 Panel interface 1-40
1 7 1 Switch substrate interface 1-41
1 8 Inverter circuit 1-42
1 8 1 Basic configuration 1-42
1 8 2 Circuit block diagram 1-42
1 8 3 Input/output terminal functions 1-43
1 8 4 Detailed description of each circuit 1-44

iv
1 8 4 1 Power input section 1-44
1 8 4 2 Lamp drive circuit section 1-44
1 8 4 3 Protection circuit section 1-45
1 8 4 3 1 Lamp current detection protection circuit
(lamp current limiter) 1-45
1 8 4 3 2 Overvoltage protection circuit 1-45
1 8 4 3 3 Protection circuit operation timer circuit
(malfunction prevention) 1-46
1 8 4 3 4 Fuse 1-46

v
2 Adjustment procedure 2-1
2 1 Application 2-1
2 2 Measurement instruments used 2-1
2 3 Standard setting state 2-1
2 4 Names of each LCD monitor part, and adjustment methods 2-2
2 4 1 Configuration of front control panel 2-2
2 4 2 OSM operation method 2-2
2 4 3 Configuration of signal input / power input section 2-3
2 5 PWB, mechanism and appearance inspection 2-4
2 5 1 Visual and conductivity check 2-4
2 5 2 Mechanism and appearance inspection 2-4
2 5 3 PWB adjustment 2-6
2 5 3 1 Initial writing in EEPROM data 2-6
2 6 General adjustment and inspection 2-6
2 6 1 Preparation 2-6
2 6 1 1 Confirming operation of operation SW and functions 2-6
2 6 1 2 Inspection of picture 2-6
2 6 1 3 Aging 2-7
2 6 2 Main adjustment 2-7
2 6 2 1 Confirming OSM picture during heat running 2-7
2 6 2 2 BIAS adjustment 2-7
2 6 2 3 GAIN adjustment 2-7
2 6 2 4 BRIGHT-LIMIT adjustment 2-7
2 6 2 5 Confirming color coordination of Liquid Crystal Panel 2-7
2 7 Configuration of DDC (EDID) data 2-8
2 8 Inspection 2-12
2 8 1 Electric performance 2-12
2 8 1 1 Confirming the operation of operation SW 2-12
2 8 1 2 Frequency change speed 2-12
2 8 1 3 Confirming frequency range (Confirming preset timing) 2-12
2 8 1 4 Confirming automatic adjustment function 2-12
2 8 1 5 Confirming composite sync signal 2-12
2 8 1 6 Confirming Sync On Green signal 2-12
2 8 1 7 Confirming digital input 2-12
2 8 1 8 Confirming D-SUB input connector 2-12
2 8 1 9 Confirming power management function 2-13
2 8 1 10 Isolation voltage 2-13
2 8 1 11 Ground resistance 2-13

vi
2 8 1 12 Shock test 2-13
2 8 1 13 Confirming color selecting (AccuColor) function 2-13
2 8 2 Picture performance 2-14
2 8 2 1 Picture performance inspection 2-14
2 8 2 2 Confirming color coordination 2-15
2 8 2 3 Panel inspection (luminance / color coordination / defect) 2-15
2 9 Liquid crystal display defect standards 2-16
2 9 1 Condition of appearance inspection 2-16
2 9 1 1 Scope of inspection 2-16
2 9 1 2 Environment for inspection 2-16
2 9 1 3 Picture pattern 2-16
2 9 2 Definition of applicable area 2-16
2 9 3 Standards for display conditions (standard for errors/defects) 2-17
2 10 Outgoing inspection 2-20
2 10 1 OSM default setting 2-20
2 10 2 Checking the labels, etc 2-20
2 10 3 Packaging specifications 2-20
2 11 Timing chart 2-21
2 12 OSM display matrix 2-22
3 Trouble shooting
4 Waveform
5 Schematic diagram
<Attachment>
Serial number information
Specification
User's guide
All parts list

1 - 1
1. Circuit description
1.1 Power circuit
(1) The power block is compatible with 100 to 120VAC/220 to 240VAC. (Automatically tracke )
(2) The power supply section is a PRC (ON wi th control with constant OFF time) uring P-SAVE, an
operates as a pseu o-resonance circuit in the stea y state.
By fee ing back via the photocoupler IC903 from the output voltage with the HIC (STR-G6452)
flyback converter type switching IC (IC901) with built-in POWER-MOS FET an separate-exciting
control IC, the voltage is constantly controlle to prevent output voltage fluctuations cause by AC
input voltage fluctuations an secon ary si e loa fluctuations.
(3) Switching of the PRC an pseu o-resonance is controlle by inputting to IC901 via IC905 with a
microcomputer signal.
(4) The secon ary si e output voltage of this power circuit is a single-phase 12V.
Microcomputer signal (J901 1 PIN)
IC901 oscillation frequency
Stan by mo e
(PRC mo e)
L
Approx. 20kHz
Normal mo e
(pseu o-resonance mo e)
H
Approx. 50k~150kHz
<Block iagram>
AC100~120
220~240
Transformer
Vcc
IC901
F/B
IC903
12V
IC905
Starting resistance
To inverter
To main
IC904
+B
EMI filter Rectification Rush
prevention
HIC control IC
Shunt
regulator
P-SAVE
microcomputer
signal

1 - 2
1.2 Detailed description of each circuit
1.2.1 Pseudo-resonance circuit method
With pseu o-resonance, when the ischarge of energy (secon ary coil current = 0) en s on
the secon ary si e of the transformer, the transformer en s the transformer connection.
Pseu o-resonance takes place between the primary si e in uctance an voltage resonance
capacitor (or parasitic capacity) between the rain an source. The rain voltage is re uce to
the sine wave. When the rain voltage reaches the bottom (valley) of this vibration waveform
an the next cycle turns ON, soft switching takes place. With the effect of the voltage reso-
nance capacitor, the v/ t of the VDS uring turn OFF becomes gra ual. This series of opera-
tions is calle pseu o-resonance. The turn ON timing is applie using the signal that has
passe through the elay circuit using the flyback voltage waveform of the auxiliary coil.
<Circuit an waveform>
C1
D2
2
D3
1
C3
C2
V OCP
P
VD
T= LpC4( elay time)
D
D4
R3
C4
C5
R4
R5
VDS
4
5
V DS
V D
I D
V P
V P
V IN(DC)
fR=1/(2 LpC4)(resonance frequency)
VDS lower limit
V OCP 3.4
OCP/FB terminal threshol voltage (2) 1.5
OCP/FB terminal threshol voltage (1) 0.76
V P
VIN(DC)

1 - 3
1.2.2 Switching circuit operation
When actually changing over, if the voltage Vth (1) of the pseu o-signal applie on the HIC pin
OCP/FB terminal is nearly equal to 0.76VMIN or more or less than the threshol voltage Vth
(2) 1.3V, the internal Comp 1 operates, an PRC operation with a fixe OFF interval takes
place at TOFF 50µS.
When this voltage is more than the threshol voltage Vth (2) 1.5V or more (Max. 6V), the
internal Comp 2 operates. The OFF time generate by the internal transmitter changes at
approx. 1µS (Max). MOSFET remains OFF while the voltage is higher than the threshol
voltage Vth (1).
Pseu o-resonance operation refers to matching the timing for turning this MOSFET ON with
the bottom point of the voltage resonance after the transformer has ischarge the energy, an
with a cycle one-half of the resonance frequency. When the voltage resonance capacitor C906
is connecte between the rain an groun , an the elay circuit R907, R909, C914 or D902 is
connecte between the auxiliary coil T - an pin OCP/FB terminal, the flyback voltage
generate from the auxiliary coil when MOSFET is OFF causes the pseu o-resonance signal to
operate the IC internal Comp 1 an Comp 2, an starts pseu o-resonance operation.
Even when ischarge of the transformer energy has finishe with the elay circuit, the pseu o-
resonance signal will not lower to the pin terminal imme iately. This is because the charge
at C909 an C914 rises above the threshol Vth (1) or less for a set time after the charge is
ischarge by the composite impe ance of the IC internal active lowpass filter an R905.
<Waveform at switching>
IC901 pin waveform
At stan by When normal

1 - 4
1.2.3 Description of operation
(1) When the power is turne ON, C924 is charge by the starting resistors R903 an R934.
When this IC901 pin voltage reaches 17.6V, the control circuit starts operation.
After the control circuit starts operation, power is attaine by rectifying an smoothing the
coil voltage at the T901 auxiliary coil - .
(2) IC901 pin OCP/FB terminal, oscillator an constant-voltage control circuit
The oscillator uses the HIC's internal CI charging/ ischarging. Pulse signals are generate
to etermine the MOSFET OFF time. The constant-voltage control when the switching
power is configure fixes the MOSFET OFF time (50µsec), an functions with the PRC
operation that changes the ON time an the pseu o-resonance operation.
The operation for no-constant voltage is shown in the figure below. When MOSFET is ON,
capacitor C1 in OSC is charge to the constant-voltage (5.6V). By passing the rain current IP
to R906, a voltage rop (VR5) occurs at the pin OCP/FB terminal. This voltage has the
same waveform as IP, an approximately the same voltage as VR5 is applie on the pin .
When the pin voltage reaches the threshol voltage 0.76V, Comp 1 operates, an MOSFET
turns OFF when the internal converter reverses. The C1 charge is release when MOSFET
turns OFF, an charging of C1 starts with the constant-current ischarge circuit. The voltage
at both en s rops at the inclination etermine by the capacitor in the OSC an the constant-
current ischarge circuit. When the voltage at both en s of the capacitor in OSC rops to
approx. 1.2V, the oscillator output reverses again an MOSFET turns ON. At this time, the
capacitor in OSC is rapi ly charge to 5.6V. MOSFET continues oscillation with a repetition of
these steps.
As explaine above, the time etermine by the VR5 (IP) inclination is the MOSFET ON time.
This fixe time is a juste to 50µsec by the constant-current ischarge circuit.
To control the output, the F/B current passe to photocoupler IC903 is passe to R905 an
R935, an the voltage rop VR4 cause by this is applie on VR5. With this, the VR5 voltage
value (IP peak value) require to reverse Comp 1 is use as the control for the current mo e
controlle by VR4 (FB current).
When MOSFET is OFF, the bias amount to just before MOSFET turns ON is lowere to approx.
half by the active lowpass filter's 0.8mA (typ.) constant-current bias circuit. As a result, the
surge noise that occurs when MOSFET turns ON is absorbe by C909.
Oscillation operation urin
g
constant-volta
g
e control
5V
Oscillator voltage
0V
0.76V
Voltage at both en s of C5
0V
Oscillator output
0
MOSFET
Direct-current bias cause by photo-transistor
ON ON
OFF
OSC
PWM Latch
S Q
R
Q S
R
INH Latch
Comp.1
+
-
+
-
Comp.2
Vth(1)
Vth(2)
Drive
Reg1
1
2
5
3
DPC
R2
VR5
VR4
R4
R5
C5
OCP/FB/Tri
GND
S

1 - 5
VR5VR4
0V
0.76
ON wi th control
Conventionally, the charging current of the oscillator's capacitor was change by the
photocoupler current, an the charging time until the threshol voltage Vth (1) $ 0.73[V] was
change . However, with the STR-G6452, the DC bias is controlle .
(3) Pin OCP/FB terminal an OCP circuit
This is a pulse bypass metho overcurrent protection circuit that etects the MOSFET
rain current's peak value every pulse, an reverses the oscillator output.
The MOSFET rain current is etecte by connecting R906 across the pin MOSFET
source terminal an pin GND terminal, an inputting the rop voltage into the OCP/FB
terminal.
The OCP terminal's threshol voltage r+h(1) is approx. 0.76V (typ.) in respect to the
GND. R905, R935 an C909 are the filter circuits use to prevent malfunctions by the
surge current generate when MOSFET turns ON.
When the secon ary output rops in the overloa state, the primary auxiliary coil voltage
rops in proportion. Thus, the pin voltage rops to below the operation stop voltage,
an the operation stops.
In this case, the circuit current rops simultaneously, so the pin voltage rises again
with the charging current from R903 an R934, an intermittent operation that restarts
with the operation start voltage takes place.

1 - 6
1.2.4 Protection circuit
A fuse is inserte in the 12V line (F910, F911) as an overcurrent protection an as a circuit
that maintains the oscillator output at the LOW level an stops the power circuit operation
when the overvoltage protection (OVP) circuit or overheat protection (TSD) circuit operate.
1.2.4.1. Latch circuit
This circuit maintains the oscillator output at the LOW level an stops the power circuit opera-
tion when the overvoltage protection (OVP) circuit or overheat protection (TSD) circuit operate.
The latch circuit hol ing current is 70µA max. (Ta = 25˚C) when the voltage of pin is 10.5V.
By consi ering that this increases lightly at high temperatures an by passing a current of
140µA or more to the pin from the starting resistor, the power circuit will maintain the
stoppe state. A elay time is provi e with C2 in the hybri IC to prevent malfunctioning by
noise, etc. If the OVP or TSD circuit operation continues for approx. 10µsec or more, the
latch circuit will operate.
Note that even if the latch circuit operates, the constant-voltage power (Reg) circuit is function-
ing in the control circuit, an the circuit current is high. Thus, the voltage of pin will rop
su enly. When the voltage of pin rops to below the operation stop voltage (10.1V (typ.)),
the circuit current will rop to 70µA (Ta = 25˚C) or less, so the voltage of pin will start
rising.
When the operation start voltage (17.6V (typ.)) is reache , the circuit current will start to in-
crease again, so the voltage of pin will rop su enly. Thus, when the latch circuit is oper-
ating, the voltage of pin will rise an lower between 10.1V (typ.) an 17.6V (typ.) an pre-
vent the voltage of pin from rising higher. An example of the voltage of pin waveform
uring latch circuit operation is shown in the figure below. The latch circuit is cancele by
lowering the voltage of pin to less than 7.9V, an generally, it is restarte by turning the AC
power OFF an ON.
1.2.4.2 O erheat protection circuit
This circuit operates the latch circuit when the hybri IC's frame temperature excee s 135˚C
(MIN). The temperature is actually etecte by the control circuit element. Since MOSFET
an the control circuit element are on the same frame, this will also function when MOSFET
overheats.
4
(TYP)
(TYP)
Example of waveform of pin at latch circuit operation

1 - 7
1.2.4.3 O er oltage protection circuit
This circuit operates the latch circuit when the voltage of pin excee s 25.5V (typ.). Basi-
cally, this functions as the overvoltage protection for pin in the control circuit. Normally, the
pin is supplie from the transformer's secon ary coil. This voltage is proportional to the
output voltage, an also functions for the secon ary output overvoltage when the control circuit
is open, etc.
+
-REC
Latch Delay
Drive
Internal Bias
UVLO
Vin
4
Vin (on) = 17.5V
Vin (off) = 10V
+
-
+
-
OVP
Vth = 25.5V
Ta = 155°C
REG
TSD
S
PWM Latch
INH Latch
Tcoff = 50µSR
_
Q
QR
S
OSC
+
-
+
-
INH Comp.
OCP Comp.
Vth=1.45V
Vth=0.73V
Icont
GND
OCP/FB
3
S
D
2
1
5
Functions of each terminal
Terminal No.
1
2
3
4
5
Symbol
D
S
GND
VIN
O.C.P. / F.B
Name
Drain terminal
Source terminal
Groun terminal
Power terminal
Overcurrent/fee back terminal
Function
MOSFET rain
MOSFET source
Groun
Control circuit power input
Overcurrent etection signal an
constant-voltage control signal input

1 - 8
1.3 PWB-MAIN basic specifications
1.3.1 Basic specifications
· Two analog image system an one igital image system input compatible (AMBI X)
· Compatible synchronizing signal Analog 2Ch : SEPARATE, COMPOSITE, SYNC ON GREEN
Digital 1Ch : TMDS
· Compatible with signals not isplaye or selecte / Input signal presence ju gment an
automatic switching function (VIDEO DETECT)
· DDC switching control function (DVI SELECTION)
· DDC2Bi/DDC CI compatible
· EDID ata write protect control function (EEP WRITE PROTECT)
· Narrow bezel, wi e angle S-IPS LCD panel (Hitachi TX38D26VC0VAA) interface
· Maurice2 incorporate for ASIC
(Auto A just function, brightness, contrast, sharpness, curve, color temperature, color
control a justment function)

1 - 9
1.3.2 PWB-MAIN circuit block diagram
X'tal
A/D
A/D
A/D
R-IN1
G-IN1
B-IN1
DVI A_ RED
DVI A_GREEN
DVI A_BLUE
D-Sub RED
D-Sub GREEN
D-Sub BLUE
DVI A_ HSYNC
DVI A_VSYNC
D-Sub HSYNC
D-Sub VSYNC
AH1 AH2 AV1 AV2
LPF
LPF
LPF
LPF
TMDS
receiver
SiI 143
DVI RX2-
DVI RX2+
DVI RX1-
DVI RX1+
DVI RX0-
DVI RX0+
DVI RXC-
DVI RXC+
SEL_HS2_GS2
SEL_HS1_GS
C/S_H1
C/S_H2
C/S_V1
C/S_V2
S/G_H1
S/G_V1
S/G_H2
S/G_V2
SCDT
/PD
/PDO
P_TMDS
DDC_SCL,
DDC_SDA
DVI DDC_SCL,
DVI DDC_SDA
D-Sub DDC_SCL,
D-Sub DDC_SDA
2kBit
EEPROM
2kBit
EEPROM
2kBit
EEPROM
64kBit
EEPROM
EEP_SCL,
EEP_SDA
U/D
/INC
A2_Dig
A2_Ana
/WP
8
8
8DB[7..0]
DG[7..0]
DR[7..0]
HSYNC
VSYNC
DE
VCLK
5
3
SEL_2
FS_[2..0]
10MHz
SCLK
XIN
16
16
16
16
16
16
8bit x 2
8bit x 2
8bit x 2
QCK
QDE
QVD
QHD
QVD_M
2
2
Microcomputer
M30625
ASIC
M64539FP(MAURICE2)
8
2
LED_P_G,
LED_P_U
SW[7..0] SW[7..0]
LED_P_G,
LED_P_U
DUTYCINV
DUTYCINV
P_INVT
PRO_DLY
P_SAVE
+12V
PWB-MAIN block iagram
To DVI/D-Sub connector
To panel mo ule
+5.5V
+5V
+3.3V
+2.5V
/CS
SEL_1
R-IN2
G-IN2
B-IN2
2
Vi eo clock Panel clock
Input process
Line memory
Scaler/color conversion
PLL
Vi eo
buffer
Vi eo
buffer
S/G
synchronization
separation
S/G
synchronization
separation
To SW boar
To POWER
boar
Switching
circuit
Power
supply

1 - 10
1.3.3 Input/output connector pin assignment
Main boar - power boar
Main boar - switch boar Main boar - serial writer
Main boar - panel Main boar - panel Main boar - signal connector (DVI) Main boar - signal connector (DSUB)
J601
1 2 3 4 5 6 7 8
+12V +12V
GND GND
P_INVT
DUTYCINV
PRO_DLY
P_SAVE
J901
1 2 3 4 5 6 7 8
Pin name J600
1 2
AUX_TH
+5V_OUT
Pin name
B8B-PH-SM3-TBT SCN-8P B 2B-PH-SM3-TBT
J100
1 2 3 4 5 6 7 8 9
10 11 12
Pin name
GND
LED_P_U
LEFT
EXIT
-
RIGHT
NEXT
+
POWER_SW
RESET
LED_P_G
GND
J800
1 2 3 4 5 6 7 8 9
10 11 12
J101
1 2 3 4 5 6 7 8 9
10
Pin name
DG
CVSS
RESET
TXD
RXD
SCLK
BUSY
EPM*
CE*
M3.3V
J200
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
25 (C1) 26 (C2) 27 (C3) 28 (C4) 29 (C5)
Pin name
RX2- (RED)
RX2+ (RED)
GND
NC NC
SCL_DDC
SDA_DDC
A_VSYNC
RX1- (GREEN)
RX1+ (GREEN)
GND
NC NC
+5VDC
GND
HTPLUG
RX0- (BLUE)
RX0+ (BLUE)
GND
NC NC
GND
RXC+ (CLOCK)
RXC- (CLOCK)
A_RED
A_GREEN
A_BLUE
A_HSYNC
A_GND
J400
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
Pin name
GND
Q5_7 Q5_6 Q5_5 Q5_4
GND
Q5_3 Q5_2 Q5_1 Q5_0
GND
Q3_7 Q3_6 Q3_5 Q3_4
GND
Q3_3 Q3_2 Q3_1 Q3_0
GND
Q1_7 Q1_6 Q1_5 Q1_4
GND
Q1_3 Q1_2 Q1_1 Q1_0
CN2
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Pin name
GND
PEV B7 PEV B6 PEV B5 PEV B4
GND
PEV B3 PEV B2 PEV B1 PEV B0
GND
PEV G7 PEV G6 PEV G5 PEV G4
GND
PEV G3 PEV G2 PEV G1 PEV G0
GND
PEV R7 PEV R6 PEV R5 PEV R4
GND
PEV R3 PEV R2 PEV R1 PEV R0
FH12A-30S-0.5SH (CP452P281A11)
J401
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
Pin name
GND
QCK
GND
QDE
GND
QVD
GND QHD GND
NC
GND
Q4_7 Q4_6 Q4_5 Q4_4
GND
Q4_3 Q4_2 Q4_1 Q4_0
GND
Q2_7 Q2_6 Q2_5 Q2_4
GND
Q2_3 Q2_2 Q2_1 Q2_0
GND
Q0_7 Q0_6 Q0_5 Q0_4
GND
Q0_3 Q0_2 Q0_1 Q0_0
PANEL5V PANEL5V PANEL5V PANEL5V
TEST
CN1
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Pin name
GND
PDCLK
GND
PDENA
GND
VSYNC
GND
HSYNC
GND
NC
GND
POD B7 POD B6 POD B5 POD B4
GND
POD B3 POD B2 POD B1 POD B0
GND
POD G7 POD G6 POD G5 POD G4
GND
POD G3 POD G2 POD G1 POD G0
GND
POD R7 POD R6 POD R5 POD R4
GND
POD R3 POD R2 POD R1 POD R0
VDDD VDDD VDDD VDDD
TEST
FH12A-45S-0.5SH (CP452P282A11) QH11121-CB0 (CP452P343A10)
J201
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15
Pin name
RED
GREEN
BLUE
GND GND GND GND GND
+5VDC
GND GND
SDA_DDC
HSYNC
VSYNC
SCL_DDC
NFNB715A10 (CP452C070A10)
52852-1290 (CP452P318A21)
SM10B-SRSS-TB (CP452P311A51)
2 1
Cable connection
8 1
Cable connection
1 12
Flexible cable connection
1 10
Cable connection
1 30
Flexible cable connection
1 45
Flexible cable connection
52807-1210
Main boar - external thermistor (not use )

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1.4 Video input signal specifications
Analog RGB vi eo signal 0.7Vp-p, igital signal TMDS
Composite synchronizing signal (TTL level positive/negative polarity)
Separate synchronizing signal (TTL level positive/negative polarity)
Composite image synchronizing signal (0.3Vp-p Sync On Green negative polarity)
Vi eo signal
Synchronizing
signal
•Types of signals
• Analog input signal rating
• Digital input signal rating
Signal name
Specifications
Typical Unit Remarks Min.
30.0
50
25.1
DVI 1.0 compatible
Max.
60
75.1
78.8
kHz
Hz
MHz
Horizontal synchronizing signal frequency range
Vertical synchronizing signal frequency range
Vi eo clock frequency
TMDS signal GND for 50Ω impe ance
Signal name
Specifications
Typical
0.7
Unit Remarks
Min.
30.0
50
25.1
2.5
0
0.6
Max.
60
75.1
78.8
5.0
0.8
1.0
kHz
Hz
MHz
Volt
Volt
Vp-p
Horizontal synchronizing signal frequency range
Vertical synchronizing signal frequency range
Vi eo clock frequency
Separate/composite synchronizing signal Hi level
Separate/composite synchronizing signal Lo level
Analog vi eo signal level
Impe ance 2.2kΩ
Impe ance 75kΩ

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1.4.1 Video interface peripheral circuit
D-SUB connector
DVI-I connector
TMDS
receiver
R2
V2
G2
B2
H2
R2
G2
B2
S/G2
AH2
AV2
C/S V1
R-VIN2
G-VIN2
B-VIN2
ASIC I/O
A5V
D3_3V
74LCX14
TM3_3V
M3_3V
A5V
D3_3V
S/G H2
Vi eo interface periphery
AH1
AV1
Sync Sepa
A5V
74F14
R1
V1
G1
B1
S/G1
A5V
S/G H1
SEL 1
/PDO
SCDT
/PD
LPF
LPF
H1
Sync Sepa
LPF
74F14 A5V 74LCX14 D3_3V
LPF
SEL HS2_SG2
C/S V2
C/S H2
C/S H1
SEL HS1_SG1
A5V
R1
G1
B1
R-VIN1
B-VIN1
G-VIN1
SEL 2
74ACT157
74ACT157
P_TMDS
J200
IC500
J201
IC201
IC201
IC300
IC303
IC304
IC301
IC400
Vi eo
buffer
Vi eo
buffer
Micro-
computer
IC102
* 74LCX14 is use for the waveform rectification an level conversion (5V system to 3.3V system).

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1.4.2 Horizontal/ ertical synchronizing signal input circuit
The horizontal/vertical synchronizing signal input from an external source is terminate to
2.2kΩ an then passes through IC201 (74F14) which has hysteresis characteristics. The
separate sync an composite sync are input into the synchronizing signal.
IC201
74F14
HSYNC 2.2kΩ
VSYNC 2.2kΩ 100Ω
100Ω
47pF
47pF
431
431
HS
VS
33Ω
100Ω

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1.4.3 Composite sync V separation circuit
• LPF input step (HS* or GS*)
When 74F14 VOL = 0.5V (Max.): 1OL = 20mA
The LPF, 74ACT157 an 74LCX14 input impe ance is high, so if it ignore , the current le in
at 74F14 VOL will be 4.8mA [5V/(1K+33)Ω], an the maximum value at HS* an GS* Lo level
will be 0.66V = 0.5V [75F14 VOL (Max.)] + 33Ω x 4.8mA.
74LCX14 VIL = 0.72V (Min.) (at VCC = 3.3V conversion) > 0.66V OK
74ACT157 VIL = 0.8V (Min.) > 0.66V OK
• LPF output step
74LCX4MTCX threshol level (at VCC = 3.3V conversion)
Min. Max.
VIH 1.38V 2.50V
VIL 0.72V 1.74V
The V signal sampling circuit's constant was set in consi eration of the 74LCX14MTCX thresh-
ol level fluctuation. (Confirmation with the over-range of input signal SPEC timing, confirma-
tion with ifferent polarity, etc.)
A5V
A5V A5V
1K
100
1K
1.2K -F
2SC2412
V signal sampling circuit
74F14 74LCX14MTCX
2.7K -F
5600P
D3 3V
D3 3V
D3 3V
A5V
33
74LCX14MTCX
74ACT157
4.7K
74LCX14MTCX
100
AH*
C/S_V* or S/G_V*
HS* or GS*
LPF
IC201 IC300, IC303
IC300, IC303
IC300, IC303
IC301, IC304
C/S_H* or S/G_H*
To microcomputer
To ASIC
To microcomputer
Composite sync
* in icates the input Ch 1 or 2.