Northern NS-622 User manual

Ot'
1024 A Li C
CONVERSION GAIN
512
256
1024
•
ZERO LEVEL
COINC
ANTI COINC
1
5V,
256
GROUP SIZE
)12
1024
1111
64
r
DIGITAL OFFSET
256
512
NORTHERN
AOC INPUT
AC
ANALYZE
0-5V
SUBSIDIARY Of
AlUDLEION
24/125
1 2
/ 1
8
24/03

CONTENTS
I. INTRODUCTION
1
II. GENERAL SYSTEM DESCRIPTION
2
III. OPERATING CONTROLS AND SPECIFICATIONS
6
A.
Inputs
6
B. Discriminators
6
C.
Zero Level Controls
7
D.
Conversion Gain
7
E. Group Size Switch
8
F.
Analyze Off Switch
8
G. Power Requirements
8
H. Rear Panel Connectors/Signals
8
IV. OPERATION
9
A. General 9
B.
Initial Set Up and Operation With The NS-630 Memory Unit 10
C.
Lower and Upper Level Discriminators
10
D.
Zero Level Adjustment
11
E.
Conversion Gain
12
F. Group Size Switch
13
G.
Coincidence, Anti-Coincidence Operation . ..
• •
.14
H.
Analyzing dc or Slow ac Signals
15
V. SYSTEM AND CIRCUIT DESIGN
17
A.
General
17
B.
The Basic ADC Circuitry
17
C.
Store, Clear, Reject and DigitalOffset Logic Circuits . . . 32
VI. SERVICING
39
MAJOR SIGNALS AND THEIR FUNCTIONS
40
REAR PANEL 26M ADC CONNECTOR
42

I. INTRODUCTION
This manual covers the NS-622 Analog-to-Digital Converter (ADC)
and the ADC section of the NS-633 Pulse Height Analyzer. Both units use
the same printed-circuit board and nearly identical circuitry in the ADC's.
In general this manual will not differentiate between units unless circuit
differences exist. The design of the NS-633 is such that the ADC and
memory are almost completely independent units. A second manual covers
the memory/control section of the NS-633, and also contains operating in-
structions for pulse height analysis.
Except for address scaler size this ADC uses the same system design
as larger, more sophisticated units manufactured by Northern Scientific.
Rear panel connectors, logic levels, and pin assignments are the same as
other NSI ADC's so that units are completely interchangeable.
The converter is of the familiar Wilkinson type with peak detection
used to start the conversion process. Digitizing is performed at 50 MHz
into a 10-bit scaler for resolution up to 1024 channels. Integrated cir-
cuits are used extensively to improve stability and reliability. Operation
from the standard NIM supply voltages is accomplished by using internal
regulators to drop the NIM voltages to proper levels for the DTL and TTL
integrated circuits used.
1

II. GENERAL SYSTEM DESCRIPTION
Figure 1 is a block diagram of a typical acquisition system employing
this ADC. Figure 2 is a timing diagram showing the relative time scale
for the major signals involved in the analysis of an analog input.
Incident radiation at the detector is converted to an electrical signal
which is amplified and shaped by the amplifier. The output of the ampli-
fier connects to the ADC input where it triggers the ADC and starts con-
version of the analog input into a digital address. Once the ADC has
accepted a signal for conversion it is insensitive to other inputs until it
has been cleared (reset).
Briefly, conversion of the analog input is accomplished in the following
manner. The positive input pulse from the amplifier is applied to a stretcher
circuit which charges a capacitor to the peak amplitude of the input signal.
When the capacitor is fully charged a linear gate at the ADC input is closed,
blocking ADC response to any other input. At the same time a gate is opened
which allows 50 MHz clock pulses to start advancing a 10-bit scaler. Also
at this time logic circuits turn on a current source which linearly discharges
the stretcher capacitor back to zero. When the capacitor reaches zero the
50 MHz gate is closed and the 10-bit scaler contains a binary number whose
magnitude is directly proportional to the amplitude of the analog input pulse.
The binary number (address) is then presented to the memory unit for data
storage. When storage is complete the memory unit sends a clear signal to
the ADC. The clear signal resets the ADC, opens its linear gate; and the
ADC is available to convert another input.
The complete connection between ADC and memory unit consists of three
signals in addition to the 10-bit address. Signal STORE is generated approxi-
mately 1 usec after the ADC conversion is complete. The address is pre-
sented to the memory until 1 usec before STORE but presentation of an
address does not always mean it will be followed by a STORE. During the
1 usec, acceptance tests are performed on the address and only if these
tests are passed will a STORE follow 1 usec later. The tests performed
are: address underflow (address less than zero when using digital zero
offset), channel zero test (channel zero is reserved for live time and data
2

MEMORY
UNIT
0
ALL 10 BITS PROVIDED.
MEMORY UNIT USES ONLY
LOWER SIGNIFICANT BITS
FOR MEMORY SIZE COMPATIBILITY.
AO ------ A9
116 ...11.1.111.1=11••••11•111.,.....IMMIMM O
10 BIT BINARY
ADDRESS
STORE CLEAR
DEAD
TIME
FIG. I
BLOCK DIAGRAM OF SIMPLIFIED SYSTEM

0-5v POS. OR POS —FIRST BIPOLAR.
LINEAR RUNDOWN
INPUT
STRETCHER
END OF RUNDOWN
PSB
PEAK DETECT TIME
4-5
SET BY PSB
RESET BY CLEAR
50 MHZ
PULSE TRAIN
REMOVED AT CLEAR TIME
LOGIC I=-4-5
TYPICAL
I iitt NOTE I
LOGIC 0.0v
ADDRESS STAGE
OUTPUT
+5
NO STORE SIGNAL
FOR INTERNAL ADC
REJECT.
0
STORE
I psec
CLEAR
(FROM MEMORY)
T
I
NOTE 2
+5
311
.5 TO I psec PULSE.
NOTE I
ADDRESS OUTPUT RETURNS TO
OV IN I psec UNDER INTERNAL
REJECT CONDITIONS.
FIG. 2
ADC TIMING
NOTE
2
TIME T IS DETERMINED BY MEMORY UNIT.
ADDRESS AND STORE REMAIN UNTIL CLEAR
IS SENT.

must not be stored there), and address overflow (address greater than
memory size available). In the event the address as generated fails any
one of the three tests it will not be stored and the ADC will automatically
be reset by internal circuitry.
When the address passes the acceptance tests it is followed by a STORE
command. The memory unit is designed to respond to this signal and trans-
fer the address to its input register. At the end of data-transfer the memory
unit sends a CLEAR to the ADC. This resets the ADC and allows it to accept
another pulse for conversion. Both the address and STORE are dc signals
and will remain indefinitely until a CLEAR is received. This arrangement
greatly simplifies connection to any memory unit with no restrictions on
transfer time. The acceptance tests performed on the address with auto-
matic ADC reset under reject conditions also reduce the number of signals
required to complete connection.
The third signal sent to the memory unit is signal DT. The one state of
this signal starts with triggering of the ADC by an analog input and ends 3
usec after the ADC is reset, either internally by address reject, or by a
CLEAR from the memory unit. DT represents the complete dead time for
the ADC, the time it is not available to accept an input for conversion. This
signal can be used by the memory unit for live timer operation. In the
NS-633 signal DT is used on the ADC board to gate a clock which comes
from the memory section. For live time operation the ADC and memory
unit are both used to store live time counts. This is covered in detail in
the section on Circuit and System Design.
5

III. OPERATING CONTROLS AND SPECIFICATIONS
A. INPUTS
1. ADC Analog Input
a.
Range: 0-5V. Full scale with respect to the conversion
gain is 4V. The additional 25% over range can be utilized
by offsetting the zero intercept by 25%.
b. Polarity: Positive unipolar or positive-first bipolar.
c. Rise Time: .1 to 5 usec.
d. Fall Time: .1 to 10 usec; up to 30 usec is permissible but
the linearity of the lower 5% of the range will be degraded.
e.
Input Impedance: 10K ohm.
f.
Coupling: Switch selected, ac (capacitive) or dc (direct).
2. COINC Input
a.
Positive 5V signal performs either coincidence or anti coinci-
dence function depending on position of COINC-ANTI COINC
switch.
b.
Input Impedance: 3.3K ohm, dc connected.
c. Refer to section on Operation for timing requirements.
B. DISCRIMINATORS
1. LOWER LEVEL
a.
Function: Sets lower limit on signals to be converted by
ADC. Signals below the lower level add no dead time to
system operation.
b.
Range: 0-100% of the full-scale conversion as set by the
CONVERSION GAIN switch.
c.
Coupling: dc to ADC input (ADC in turn may be either ac
or dc coupled depending on position of COUPLING switch).
d. Stability: Maximum 200 ppm/
° C or 24 hrs at constant
temperature, typically 50 ppm.
2. UPPER LEVEL
a. Function: Sets upper limit on signals to be converted by
ADC. Dead time for signals above the upper limit is equal
6

to signal time above the lower level threshold.
b.
Range: 5 to 125% of full-scale conversion.
c.
Coupling: Same as lower level discriminator.
d.
Stability: Max 200 ppm/ °
C or 24 hrs, typically 50 ppm.
C. ZERO LEVEL CONTROLS
1. Analog ZERO LEVEL
a.
Function: Adjusts the level of the analog input which cor-
responds to channel 0 (extrapolated).
b.
Range: -0.5 to 10%. Range refers to extrapolated zero
intercept of a plot of channel number versus analog input
amplitude.
c.
Stability: 100 ppm/°C max, 50 ppm/
°
C typical; 200 ppm/24
hrs at constant temperature; referred to full scale analog
input.
2. DIGITAL ZERO OFFSET
a.
Function: Digitally subtracts selected offset from converted
address.
b.
Positions: 0, 256, 512, 768 channels.
c.
ADC Dead Time: Independent of digital offset for a given
analog input.
d. Remarks: Underflow conversions (addresses less than 0
after offset subtraction) are rejected within the ADC; no
STORE is generated and ADC is internally reset.
D. CONVERSION GAIN
1. SWITCH
a.
Function: Sets the number of channels corresponding to full
scale analog input of 4V. Switch selects magnitude of current
effecting linear rundown of stretcher capacitor.
b.
Positions: 256, 512, 1024 channels per 4V input.
c.
Stability: 200 ppm/°C max, 50 ppm/°C typical; 200 ppm/
24 hrs at constant temperature, referred to full scale analog
input.
7

E. GROUP SIZE Switch (NS-622 only)
1.
Function: Digitally sets upper limit on channel number to be
stored in memory unit. Addresses greater than selected number
are automatically rejected within the ADC.
2.
Range: 32 to 1024 channels in binary increments.
3.
Remarks: Reject occurs when group size overflow is sensed
after conversion. When digital offset is used, overflow is sensed
on group size above channel zero. Group size in NS-633 is wired
to be a fixed 256 channels.
F. ANALYZE OFF Switch (NS-622 only)
1.
ANALYZE Position: Normal operating position.
2.
OFF Position: ADC is in dc reset condition.
G. POWER REQUIREMENTS (NS-622 only)
1. +24 : 25 mA.
2.
-24 : 30 mA.
3. +12 : 280 mA.
4. -12 : none.
H. REAR PANEL CONNECTORS/SIGNALS (NS-622 only)
NS-630 Memory Unit
a.
Size: 26 pin Amp.
b.
Signals: Address, STORE, CLEAR, DT, plus several
control input/ outputs.
c.
Levels: Logic one = +5V, Logic zero = OV, DTL/TTL
compatible.
8

IV. OPERATION
A.
General
This section covers operation of the NS-622 ADC and the NS-630
Memory Unit in pulse height analysis. Operation of the combined units
is not unlike the conventional pulse height analyzer found in a single
package. The discussion here will pertain to the ADC connected to the
Northern Scientific NS-630 Memory Unit but the front-panel adjustments
of the ADC are essentially the same when operating it in the NS-633 Pulse
Height Analyzer.
B.
Initial Set Up and Operation With The NS-630 Memory Unit
Listed below are the switch positions and signal requirements which
will ensure proper operation of the ADC and the NS-630 Memory Unit. It
is assumed that the NS-630 Memory Unit has been adjusted for pulse height
analysis mode of operation. If there is any question about proper switch
positions for this mode, refer to the NS-630 manual. This set up is for
simple, straightforward nuclear pulse height analysis and does not utilize
the full capabilities of the system. Sections which follow cover the controls
individually so that maximum acquisition efficiency can be achieved under
more complex modes of operation.
1.
Turn off the power on all units.
2.
Connect the ADC to the memory unit using the cable supplied.
3. Connect the signal source to the ADC BNC input labeled ADC
INPUT. Signal must be positive unipolar or positive first bi-
polar. Set the coupling switch on the ADC front panel to ac.
4.
Set COINC/ANTI COINC switch to ANTI COINC.
5. Set ULD full clockwise.
6. Set LLD one quarter turn from full CCW position.
7. Set ZERO LEVEL at 100 small dial divisions.
8. Set CONVERSION GAIN to the switch position which corresponds
to the memory unit size available.
9. Set the GROUP SIZE switch to the same position as the CONVER-
SION GAIN switch.

10.
Place all DIGITAL OFFSET switches in the OFF position.
11.
Now energize the NS-630 Memory Unit and the power supply
in the NIM bin.
12.
Place the ANALYZE OFF switch on the ADC to the ANALYZE
position.
13.
Control system with the START MEASURE and STOP pushbuttons
on the NS-630. The above procedure sets up the ADC for analysis
of the entire range from threshold to full scale. The ZERO LEVEL
is set near 0-0 intercept and the lower level discriminator is set
for approximately maximum sensitivity. Either the ADC ANALYZE
OFF switch or the memory START MEASURE and STOP pushbuttons
can be used to control analysis. The controls on the memory unit
are preferred, however, because they also control operation of the
clock/live timer in the memory unit. Accurate live time can be
realized only when the memory unit pushbuttons are used to control
analysis.
C. Lower and Upper Level Discriminators
The lower and upper level discriminators are connected directly to the
ADC input and are used to bracket the range of analog signals to be converted
by the ADC. Internally both discriminators are directly coupled to the ADC
input. Also, the range of the lower level discriminator extends below zero
so that the full CCW position of the front panel control will cause the dis-
criminator to be triggered 100% of the time. This is indicated by 100%
deflection on the dead time meter with no input signal. This is an improper
operating point for the ADC, but this point was designed to accommodate
small dc offsets of the input signal baseline when external restorers and
dc input connection are used. The lower level discriminator is set for
maximum sensitivity at the point where the dead time meter just drops
from 100% back to zero with no input signal. Operation at maximum sensi-
tivity should be avoided, however, because any small drift in the system
may cause the lower level discriminator to trigger 100% of the time. The
maximum sensitivity point should be found experimentally and then the
10

control should be adjusted to be positioned one-eighth turn above this point.
The upper level discriminator inhibits conversion of any signals above
the upper level threshold. ADC dead time can be reduced considerably by
adjusting the upper level threshold to be just above the maximum signal of
interest. At low count rates this adjustment is not important but at high
count rates considerable system dead time can be eliminated by proper
setting of this control.
The upper and lower level discriminators should be adjusted to bracket
a region of interest when using digital zero offset. With the discriminator
set to convert the entire full scale spectrum considerable dead time is used
in converting signals which are later rejected by underflow and overflow
tests performed after conversion. After the region of interest is once se-
lected with the DIGITAL OFFSET and GROUP SIZE controls, the upper and
lower level thresholds should be adjusted to fall just outside the region of
interest which has been bracketed digitally. Operation in this manner pro-
vides double selection of the region of interest. The discriminators provide
analog selection and reduce ADC dead time while the GROUP SIZE/DIGITAL
OFFSET controls provide for logic functions which precisely select the re-
gion to be stored in the memory unit.
D. Zero Level Adjustment
Zero level is defined as that analog input level which corresponds to
channel zero (extrapolated) in the stored analysis. Using the front panel
ZERO LEVEL Helipot any analog input from zero through . 4 volts can be
adjusted to correspond to channel zero in the memory unit. The ZERO
LEVEL control is analogous to the bias level on a biased amplifier; signals
below the zero level are not converted by the ADC just as signals below bias
level are not amplified. As the ZERO LEVEL control is turned clockwise
the channel number for a given energy is reduced. This has the effect of
shifting the entire spectrum to lower channels when viewed from channel
zero through full scale. From the standpoint of the spectrum stored in the
memory unit there is no difference in the results obtained using the analog
ZERO LEVEL control or the DIGITAL OFFSET switches. The main difference

in the two, however, is that the analog zero level control does reduce the
amount of dead time required for a given conversion. The digital offset
switches operate on the address after conversion. That is, for a given
energy, the conversion time is independent of the digital offset switch
positions. Using analog offset, however, the dead time is inversely pro-
portional to the magnitude of offset. From a dead time standpoint only,
analog adjustment is preferred over digital offset of zero level. However,
digital offset does provide a convenient means of shifting the spectrum some
fraction of the full scale conversion gain since offset, conversion gain, and
memory group sizes are all in binary increments. The speed of the NS-622
is such that conversion times are low even with digital offset. For medium
count rates the increased dead time is not significant, especially if the lower
and upper level discriminators are adjusted properly to bracket the region-
of-interest selected.
One final word on the analog zero level control at this time is in order.
While the analog zero level control performs the same function as the bias
level on a biased amplifier, the disadvantages associated with biased ampli-
fiers are not found in the ADC. It is normal for a biased amplifier to bias
off the lower portion of the input signal with a resultant change in pulse
shape for signals above the bias level. The NS-622 ADC, however, employs
a different design technique whereby the signal as seen by the pulse stretcher
is independent of the ZERO LEVEL control setting. The significant advan-
tages of this technique are that the ADC linearity is independent of zero level
adjustment, and also the ADC stability is not dependent on zero level setting.
See the next section on System and Circuit Design for details on how this is
accomplished.
E. Conversion Gain
Front panel switch positions on the CONVERSION GAIN switch indicate
the address generated for a 4 volt analog input signal. This switch then
effectively adjusts the resolution of the ADC since the number of discrete
channels for a given analog input is a function of this switch position. In-
ternally this switch adjusts the magnitude of the rundown current which
effects linear discharge of the stretcher capacitor. If the entire energy
12

range from zero to full scale is to be analyzed, the CONVERSION GAIN
switch is set to the number which corresponds to the size of the available
memory. The ADC may be operated at higher resolution settings than this
but only by viewing a smaller portion of the entire spectrum. For example,
if a 256 channel memory is the size in use then in order to view the entire
voltage range from zero to 4 volts the CONVERSION GAIN must be operated
at the 256 position. The CONVERSION GAIN may be operated at a setting
of 1024 however if only one-fourth of the spectrum is to be stored. The
CONVERSION GAIN switch is adjusted first for the resolution desired; then
either the ZERO LEVEL control or DIGITAL OFFSET is used to shift the
region of interest into channels 0 through 255. CONVERSION GAIN should
be adjusted to provide the resolution desired over the dynamic range re-
quired by the region of interest.
F. GROUP SIZE Switch (NS-622 only)
The GROUP SIZE switch is essentially a digital upper level discrim-
inator adjustment and sets the maximum address which will be stored in
the memory unit. This is accomplished by testing each conversion for an
address greater than the number selected on the front panel GROUP SIZE
switch. Addresses above the number selected cause STORE to be inhibited
and the ADC to be reset internally. The overflow tests are performed after
conversion so that digital offset is subtracted before the tests are performed.
This means that the group size as selected refers to the number of channels
above zero. Conversions below channel zero are also rejected when under-
flow is sensed in the ADC.
In normal single parameter analysis the GROUP SIZE switch position
corresponds to the memory size available. If the NS-630 is being used at
something less than full memory (quarters, halves), the switch position
should still correspond to the size of the memory being used. Switch po-
sitions corresponding to very small group sizes, 64 channels for example,
is provided for two parameter analysis in a 64 x 64 configuration of two
ADC's. Where only 64 channels along one axis are being used, digital offset
will most probably be employed. The DIGITAL OFFSET and GROUP SIZE
13

switches provide for selecting a 64 channel region of interest with the
ADC operating at much higher resolution.
G. Coincidence, Anti-Coincidence Operation
A front panel BNC is provided on the ADC for acceptance of a 0-5V
signal for coincidence or anti-coincidence operation of the ADC. A toggle
switch next to the BNC controls the operating mode. Connection is direct
so that this input may be used as an auxiliary start-stop control of the ADC
using a logic signal. Circuitry is such that this input can also be used for
time coincidence or anti-coincidence operation of the ADC.
Requirements for pulse coincidence operation are as follows. With the
toggle switch in the COINC position the ADC is inhibited from accepting any
analog input for conversion. This is accomplished by holding a linear gate
at the stretcher input closed. Analog input signals accompanied by a posi-
tive 5 volt pulse will be accepted by the ADC for conversion. All other logic
functions, both analog and digital in nature, will still apply to the subsequent
conversion. The lower and upper level discriminators, zero level control,
digital offset and group size functions operate in normal fashion so that
acceptance of a signal by the ADC does not necessarily mean it will be
stored. Timing requirements for the application of the 5 volt coincidence
signal are fairly straightforward and non critical. Pulse rise time for the
coincidence input should be somewhere in the range between 50 and 250 nano-
seconds. The coincidence pulse must arrive at the input no later than one-
half microsecond before the analog input signal reaches its peak amplitude.
There is no delay line in the ADC so that an external delay line may be
necessary to allow time for the external coincidence circuitry to make its
decision. Application of the coincidence input opens the ADC linear gate
and the signal passes through the open gate and connects to the stretcher
circuitry. When the signal reaches peak amplitude the peak detector is
triggered. At peak detect time the linear gate is closed even if the coinci-
dence input remains.
The duration of the coincidence input must be long enough to hold the
linear gate open until it is closed by the ADC at peak detect time. The
14

suggested pulse duration is one-half microsecond greater than baseline-
to-peak time of the analog input signal.
During the conversion process the ADC busy signal keeps the linear
gate closed and additional coincidence inputs have no affect on the conver-
sion. Once the ADC is reset, either by internal reject of a conversion or
at the time a CLEAR signal is received from the memory unit, the coinci-
dence input is again operative.
Pulse requirements for anti-coincidence operation of the ADC are less
stringent than for the coincidence mode. To inhibit an analog input, the
anti-Ooincidence input must be +5V at peak detect time and for approximately
400 nanoseconds thereafter. Pulse durations longer than the 400 nanosecond
minimum, or pulses applied before peak detect time have no detrimental
affect on operation. Pulses approximately two microsecond duration applied
at the same time the analog signal is applied are suggested when analyzing
one to two microsecond input pulses. The dead time for an analog input
which is inhibited is equal to the input's time above the lower level discrim-
inator threshold. The COINC input can be used as an auxiliary analyze-stop
control for the ADC. The anti-coincidence input signal is not included in
ADC dead time however, so that accurate live time operation cannot be rea-
lized if this mode of operation is used to control analysis.
H. Analyzing dc or Slow ac Signals
Either dc or slow ac signals can be analyzed with the NS-622 ADC by
sampling at the ADC input. The following front panel switch positions
should be used for operating in this mode. Place the COUPLING switch to
the dc position, and the COINC/ANTI COINC switch to the COINC position.
A positive 5 volt pulse source is required to strobe the ADC input. The
pulse duration should be a minimum of one microsecond and a maximum
of 4 microseconds. Operation is as follows. With the COINC/ANTI COINC
switch in the COINC position the linear gate of the ADC is held closed. The
dc applied at the front panel is connected to the linear gate but is blocked.
Application of the 5 volt, one microsecond pulse at the coincidence input
opens the linear gate for one microsecond. This effectively generates a
15

one microsecond pulse at the linear gate with a peak amplitude equal to
the dc input. The ADC converts the one microsecond pulse in identical
fashion to normal pulse inputs. All front panel controls, both analog and
digital, are operative in this mode.
For analysis of slow ac signals the ADC front panel controls are set
up the same as for dc signals. The ADC operated in this mode will convert
only the positive portion of the ac input. Internal circuitry clips the nega-
tive portion of bipolar inputs and coincidence pulses applied will not produce
conversions. If analysis of the entire signal is required, the ac signal must
be superimposed on a dc pedestal such that the input to the NS-622 is always
positive with respect to ground. As with dc inputs, all front panel controls
remain operative so that the discriminators, zero level and region of interest
selection controls can be used to bracket a region of interest. Once the ADC
has accepted an input for analysis, the busy signal holds the linear gate closed
until the ADC is ready to accept another pulse. Application of additional co-
incident inputs will not affect the conversion of the accepted input.
16

SS.
33,37
-I-4
i
Ti -
LLD -f- B
LLD
ZERO LEVEL/
PASSIVE
RESTORER
CLIPPER-DRIVER
LINEAR
GATE
25
ULD
CSC
PEAK DETECT M.V.
LLD +B
F.F.
II
-
LLD
RESET
PSB
/LOWER LEVEL/
UPPER LEVEL/
LLD BIASED AMP.
ADC BUSY F.F.
- STRETCHER
I CAPACITOR
- 1000 pf
CURRENT
SW
36,43,51
LLD -I-B
7
PSB PSB
F. F.
7
< ZL
PULSE STRETCHER BUSY F.F.
COUPLING/
+5
-I-4
• IC
PULSE STRETCHER
-F
19.22
1 1* •
--
U.
EC
ACN
(EP.)
LLDA-B
8
ZERO LEVEL BIASED AMP.
+
35,
40,39,23,
ZL
28
LINEAR
GATE
15
FIG. 3
BLOCK DIAGRAM OF ANALOG CIRCUITS
AND STRETCHER LOGIC CIRCUITS.

STRETCHER
CAPACITOR
- 1\1 "
ADC INPUT
ADC
LINEAR GATE
i
150 mV
i
t
LLD --1
IIIIMMII
PEAK DETECT
STROBE
4-
50
nsec
PULSE STRETCHER
BUSY F.F.
ADC BUSY F.F.
CSC FE
R EC
STORE
CLEAR
RESET AT CLEAR TIME
\t---. SET BY PSB
RESET AT CLEAR TIME
1
4 -- APPROX. 100 nsec
./ 1
PSB F.F. CANNOT BE
TRIGGERED DURING
3 psec PERIOD.
3
psec
H
1/2 — I psec
FIG. 4
TIMING FOR A BOARD SIGNALS
WITH RESPECT TO STORE—CLEAR