Nuvoton NAU88L21 User manual

Feb 28, 2022 Page 1 of 78 Rev 2.8
NAU88L21
Ultra-Low Power Audio CODEC Ground-Referenced Headphone Amplifier
GENERAL DESCRIPTION
The NAU88L21 is an ultra-low power high performance audio codec that supports both analog and digital audio functions. It includes
one I2S/PCM interface, one digital microphone interface, one digital mixer, two high quality DACs and ADC’s, and one stereo class
G headphone amplifier. The advanced on-chip signal processing engine that includes dynamic range compressor (DRC),
programmable biquad filter, as well as an integrated frequency locked loop (FLL) to support various input clocks.
FEATURES
DAC: 105dB SNR, (A-weighted) @ 0dB gain, 1.8V and -
88dB THD @ 20mW and RL= 32Ω, DAC playback to
headphone output mode
ADC: 103dB SNR (A-weighted) @ 0dB MIC gain, 1.8V, Fs
= 48kHz and -93dB THD, 1.8V, MIC gain 0dB, OSR 256x
1 Digital I2S/PCM I/O port
Two mono differential or one stereo differential analog
microphone inputs, two single-ended microphone inputs or
one stereo digital microphone input
Cap-free Low noise Microphone bias with 7uVrms noise
between 20Hz-20kHz, internal pull high resistor for
microphone.
Class G Headphone Amplifier (28mW @ 32Ω, 1%
THD+N)
Sampling rate from 8k to 192 kHz
Dynamic Range Compressor (DRC)Programmable Biquad
filter Integrated DSP with specific functions:Input
automatic level control (ALC/AGC)/limiter
Output dynamic-range-compressor/limiter
Package: 32 Pin QFN package
APPLICATIONS
Gaming controller
Wireless Headset
Smart Remote Controller

Feb 28, 2022 Page 2 of 78 Rev 2.8
Block Diagram - QFN32
Charge
Pump
ADC
MICBIAS
FLL
MUX
ADC Effect
Volume
DRC
Programmable
BiQuad
Interface
& MUX
DAC Effect
Volume
DRC
Programmable
BiQuad
BCLK
FS
DAC HPL
CPOUTP
VSSCP
CPCB
CPOUTN
CPCA
Digital Audio
Effects
Mixers
Sidetone
I2S/PCM
DAC HPR
MICBIAS
I2 C Slave
& Registers
MICL+
BIAS
VREF
SCLK
SDIO
DACIN
ADCOUT
GPIO1
VDDA
VDDB VSSD VDDA(2)
VSSA
VDDMIC
MCLK
ADC
MICR+
MUX MUX
DMIC I/F
MICR-
MICL -
MICDET
MICDET
GPIO2

Feb 28, 2022 Page 3 of 78 Rev 2.8
Table of Contents
BLOCK DIAGRAM - QFN32...................................................................... 2
PIN DIAGRAM........................................................................................... 6
PIN DESCRIPTION.................................................................................... 7
ELECTRICAL CHARACTERISTICS.......................................................... 8
1. GENERAL DESCRIPTION................................................................ 11
1.1 Inputs............................................................................................................... 11
1.2 Outputs............................................................................................................ 11
1.3 ADC, DAC and Digital Signal Processing........................................................ 11
1.4 Digital Interfaces.............................................................................................. 11
2. POWER SUPPLY ............................................................................. 12
2.1 Power on and off reset..................................................................................... 12
2.2 Power up and Start Sequence......................................................................... 12
3. INPUT PATH DETAILED DESCRIPTIONS....................................... 13
3.1 Analog Microphone Inputs............................................................................... 13
3.2 Digital Microphone Input.................................................................................. 14
3.3 VREF............................................................................................................... 14
3.4 MIC Bias.......................................................................................................... 15
3.5 MIC detect....................................................................................................... 15
3.5.1 Key Release .......................................................................................................................................17
4. ADC DIGITAL BLOCK...................................................................... 18
4.1 ADC Dynamic Range Compressors (DRC) ..................................................... 18
4.1.1 Level Estimation .................................................................................................................................18
4.1.2 Static Curve........................................................................................................................................18
4.1.3 Limitation ............................................................................................................................................20
4.2 ADC Digital Volume Control ............................................................................ 21
4.3 ADC Programmable Biquad Filter ................................................................... 21
4.4 Companding.................................................................................................... 22
4.5 Additional ADC Application Notes ................................................................... 22
5. DAC DIGITAL BLOCK...................................................................... 23
5.1 DAC Dynamic Range Control (DRC)............................................................... 23
5.1.1 Level Estimation .................................................................................................................................23
5.1.2 Static Curve........................................................................................................................................24
5.2 DAC Digital Volume Control, Mute and Channel selection.............................. 25
5.3 DAC Soft Mute................................................................................................. 25
5.4 DAC Auto Attenuate ........................................................................................ 25
5.5 DAC Path Digital Mixer with Side tone............................................................. 25

Feb 28, 2022 Page 4 of 78 Rev 2.8
5.6 Companding.................................................................................................... 27
5.6.1 µ-law...................................................................................................................................................27
5.6.2 A-law...................................................................................................................................................27
6. CLOCKING AND SAMPLE RATES.................................................. 28
6.1 I2S/PCM Clock Generation.............................................................................. 29
6.2 Frequency Locked Loop(FLL).......................................................................... 31
7. CONTROL INTERFACES................................................................. 33
7.1 2-Wire-Serial Control Mode (I2C Style Interface)............................................. 33
7.2 2-Wire Protocol Convention............................................................................. 33
7.3 2-Wire Write Operation.................................................................................... 34
7.4 2-Wire Read Operation.................................................................................... 35
7.5 Digital Serial Interface Timing.......................................................................... 36
Table 13 Digital Serial Interface Timing Parameters................................................. 36
7.6 Software Reset................................................................................................ 36
8. DIGITAL AUDIO INTERFACES........................................................ 37
8.1 Digital Audio Interface...................................................................................... 37
8.1.1 Right-Justified Audio Data............................................................................... 37
8.1.2 Left-Justified Audio Data.................................................................................. 37
8.1.3 I2S Audio Data ................................................................................................ 37
8.1.4 PCMA Audio Data ........................................................................................... 38
8.1.5 PCMB Audio Data ........................................................................................... 38
8.1.6 PCM Time Slot Audio Data.............................................................................. 38
8.1.7 TDM I2S Audio Data........................................................................................ 39
8.1.8 TDM PCMA Audio Data................................................................................... 39
8.1.9 TDM PCMB Audio Data................................................................................... 40
8.1.10 TDM PCM Offset Audio Data...................................................................... 40
8.2 Digital Audio Interface Timing Diagrams.......................................................... 42
8.2.1 Digital Audio Interface Slave Mode.................................................................. 42
8.2.2 Digital Audio Interface Master Mode................................................................ 43
8.2.3 PCM Audio Interface Slave Mode.................................................................... 44
8.2.4 PCM Audio Interface Master Mode.................................................................. 44
8.2.5 PCM Time Slot Audio Interface Slave Mode.................................................... 45
8.2.6 PCM Time Slot Audio Interface Master Mode.................................................. 45
9. OUTPUTS......................................................................................... 46
9.1 Class G Headphone Driver and Charge Pump................................................ 46
10. CONTROL AND STATUS REGISTERS ........................................... 47
11. TYPICAL APPLICATION DIAGRAM................................................ 72

Feb 28, 2022 Page 5 of 78 Rev 2.8
12. PACKAGE INFORMATION .............................................................. 73
13. REVISION HISTORY ........................................................................ 77
IMPORTANT NOTICE............................................................................ 78

Feb 28, 2022 Page 6 of 78 Rev 2.8
Pin Diagram
QFN 32-pin
26 25
28
27 30
29 31
32
20
24
18
17
22
23
19
21
16 14 15
12 13 10 11
9
1
2
3
4
6
7
8
5
MCLK
DACIN
CPOUTN
VDDA
HPOUTR HPOUTL
CPCA CPCB
VSSA
VREF
VDDMIC
VDDA
HPFB
VDDB
SCLK
SDIO
IRQ
GPIO2/JKDET
BITCLK
CPOUTP
MICL+
MICBIAS
VSSD
VDDA
ADCOUT
MICL-/DMICDATA
FS
GPIO1/CSB
VSSCP
MICDET
MIC R -/DMICCLK
MIC R +

Feb 28, 2022 Page 7 of 78 Rev 2.8
Pin Description
Pin # Name Type Functionality
1 MICDET Analog IO Microphone/button detect, 2kOhm between Mic and Mic Bias
2 MICBIAS Analog Output Microphone Bias Output
3 VDDMIC Supply Microphone supply
4 VREF Analog I/O Internal DAC & ADC voltage reference decoupling I/O
5 VSSA Ground Analog Ground
6 VDDA Supply Analog Supply
7 CPOUTP Analog I/O Charge Pump positive voltage
8 VSSCP Ground Charge Pump Supply ground
9 CPOUTN Analog I/O Charge Pump negative voltage
10 CPCB Analog I/O Charge Pump switching capacitor node B
11 CPCA Analog I/O Charge Pump switching capacitor node A
12 JKTIP(HPL) Analog Output Jack Tip; Headphone left channel output
13 JKR1(HPR) Analog Output Jack Ring1; Headphone right channel output
14 HPFB Ground Headphone Ground
15 IRQ Digital I/O IRQ
16 GPIO1/CSB Digital I/O General Purpose IO/CSB
17 SDIO Digital I/O Serial Data for I2C
18 SCLK Digital Input Serial Data Clock for I2C
19 VDDB Supply Digital IO Supply
20 VSSD Ground Digital IO ground
21 VDDA Supply Analog supply
22 MCLK Digital Input CODEC Master clock input
23 BCLK Digital I/O Serial data bit clock input or output for I2S or PCM data
24 FS Digital I/O Frame Sync input or output for I2S or PCM data
25 DACIN Digital Input Serial Audio data input for I2S or PCM data
26 ADCOUT Digital Output Serial Audio data Output for I2S or PCM data
27 JKDET Analog Input Jack detect input
28 MICR+ Analog Input PGA MICR+ Analog Input
29 MICR-/DMCLK Analog/Digital Output PGA MICR- Analog Input / Digital Microphone Clk output
30 MICL-/DMDATA Analog Input/Digital Input PGA MICL- Analog Input / Digital Microphone Data input
31 MICL+ Analog Input PGA MICL+ Analog Input
32 VDDA Supply Analog Supply

Feb 28, 2022 Page 8 of 78 Rev 2.8
Electrical Characteristics
Conditions: VDDA = VDDB = 1.8V; VDDMIC= 3.6V.
RL(Headphone) = 32 Ω, f = 1kHz, MCLK=12.88MHz, unless otherwise specified. Limits apply for TA= 25°C
Symbol Parameter Conditions Typical Limit Units
ISD Shutdown Current
V
DD
A
4
16
µA
V
DD
B
0.2
1
VDDMIC
0.2
1
IDD
Headset Detection Standby
Mode
MCLK off, Jack Insertion, IRQ enabled 10 µA
Active Current Normal Playback
Mode
f
S
= 48kHz, Stereo HP DAC On, HP
On, POUT = 0mW. RL(HP) = 32Ω
5 mA
Headphone Amplifier
POOutput Power
Stereo RL = 32Ω, DAC Input, CPVVDD =
1.8V, f=1020Hz, 22kHz BW,
THD+N = 1% (QFN package), 28 mW
Stereo RL = 16Ω, DAC Input, CPVVDD =
1.8V, f=1020Hz, 22kHz BW,
THD+N = 1% (QFN Package)
33 mW
THD+N
Total Harmonic Distortion +
Noise
RL = 32Ω, f=1020Hz, PO= 20mW -88 dB
SNR Signal to Noise Ratio
VOUT = 1VRMS, DAC Input,
DAC_Gain = 0dB, HP_Gain = 0dB,
Digital Zero Input, f=1020Hz, A-
Weighted)
105 dB
VOUT = 1 V
RMS
, DAC Input,
DAC_Gain = 0dB, HP_Gain = 0dB,
Digital Zero Input, f=1020Hz, A-
Weighted, auto attenuate enabled,
108 dB
PSRR Power Supply Rejection Ratio
f
RIPPLE
= 217Hz, V
RIPPLE
= 200mV
P_P
Input Referred, HP_GAIN = 0dB
DAC Input, DAC_Gain = 0dB Ripple
Applied to VDDA
90 dB
Mono_Gain = 0dB Ripple Applied to
VDDA
90 dB
Stereo Single Ended Input Terminated,
Stereo_Gain = 0dB Ripple Applied
to VDDA
90 dB
XTALK Channel Crosstalk Left Channel to Right Channel, -
1dBFS, Gain = 0dB, f
= 1020Hz
70 dB
Interchannel Level Mismatch +/- 0.1 dB
Frequency Response F = 20Hz ~ 20kHz +0.1/-0.2 dB
Pop up Noise 1 mVrms
eOS Output Noise
DAC_Gain = 0dB, HP_Gain = 0dB,
fS=48kHz, OSRDAC = 128, A-
Weighted
4.4 uVRMS
Out of Band Noise Level -60dB
VOS Output Offset Voltage
HP_Gain = 0dB, DAC_Gain= 0dB,
DAC Input
±1 mV
Power Consunption MP3 Mode No Load, No Signal, Amp on 6 mW

Feb 28, 2022 Page 9 of 78 Rev 2.8
Symbol Parameter Conditions Typical Limit Units
f
S
= 48kHz, Stereo DAC On, Amp On,
POUT = 0mW. RL = 32Ω
Fs Accuracy (44.1 / 48 kHz)
+/-
0.02%
Pop and Click Noise plug Into or out of DAC to Headphone 1 mVrms
ADC
THD+N ADC Total Harmonic Distortion +
Noise
MIC Input, MIC_GAIN = 0dB, VIN =
0.8Vrms, f=1020Hz, fs = 48KHz,
Mono Differential Input
-91 dB
MIC Input, MIC_GAIN = 30dB, Volume
= 0dB, Vin=28.5mVrms, f=1020Hz,
Digital Gain = 0dB, Mono
Differential Input
-80 dB
SNR Signal to Noise Ratio
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
0dB,fs = 48kHz, Mono Differential
Input
102 dB
Reference = VOUT(0dBFS), A-
Weighted, MIC Input, MIC Gain =
6dB,fs = 48kHz, Mono Differential
Input
101 dB
PSRR Power Supply Rejection Ratio
V
RIPPLE
= 200mV
PP
applied to V
DD
A,
fRIPPLE = 217Hz, Input Referred,
MIC_GAIN = 0dB Differential Input
90 dB
CMRR Common Mode Rejection Ratio Differential Input 100mVrms, PGA gain = 20dB, frequency sweep from
20Hz to 20KHz 65 dB
FSADC
ADC Full Scale Input Level
VDDA= 1.8V
1
VRMS
Minimum Input Impedance 10 kOhm
Frequency Response f = 20Hz ~ 20kHz +0.1/-0.2 dB
Pop up Noise TBD 1 mVrms
Power Consumption
No Signal, ADC on
fs= 44.1kHz
5 mW
MICBIAS
VBIAS Output Voltage Programmable 1.8V to 3.0V in 6 steps 2.5 V
I
OUT
Output Current
4
mA
eos Output Noise Low noise mode, at 1kHz 47 nV/√Hz
Digital I/O
Parameter
Symbol
Comments/Conditions
Min
Max
Units
Input LOW level VIL
VDDB = 1.8V
0.33*VDDB
V
VDDB = 3.3V
0.37*VDDB
Input HIGH level VIH
VDDB = 1.8V
0.67*VDDB
V
VDDB = 3.3V
0.63*VDDB
Output HIGH level VOH ILoad= 1mA
VDDB=1.8V
0.9*VDDB
V
VDDB = 3.3V
0.95*VDDB
Output LOW level VOL ILoad= 1mA
VDDB = 1.8V
0.1*VDDB
V
VDDB=3.3V
0.05*VDDB

Feb 28, 2022 Page 10 of 78 Rev 2.8
Recommended Operating Conditions
Condition Symbol Min Typical Max Units
Digital I/O Supply Range
VDDB
1.62
3.3
3.6
V
Analog Supply Range
VDDA
1.62
1.8
1.98
V
Headphone Supply Range
VDDA
1.62
1.8
1.98
V
Microphone Bias Supply Voltage
VDDMIC
3.0
3.3
3.6
V
Temperature Range
TA
-40
+85
°C
Absolute Maximum Ratings
Parameter Min Max Units
Digital Supply Range
-0.3
2.2
V
Digital I/O Supply Range
-0.3
4.0
V
Analog Supply Range
-0.3
2.2
V
Headphone Supply Range
-0.3
2.2
V
Microphone Bias Supply Voltage
-0.3
4.0
V
Voltage Input Digital Range
DGND - 0.3
VDD + 0.3
V
Voltage Input Analog Range
AGND - 0.3
VDD + 0.3
V
Junction Temperature, TJ
-40
+150
°C
Storage Temperature
-65
+150
°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods. Exposure to such conditions may adversely
influence product reliability and result in failures not covered by warranty.