NXP Semiconductors AN10365 Installation and operating instructions

AN10365
Surface mount reflow soldering description
Rev. 03 — 22 April 2008 Application note
Document information
Info Content
Keywords surface mount reflow soldering
Abstract This application note provides guidelines for the board mounting of IC
packages.

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 2 of 24
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors AN10365
Surface mount reflow soldering description
Revision history
Rev Date Description
03 20080422 various text amendments to Section 1,2.1,2.2,2.3,3,4.1,4.2,4.3 and 6.
02 20060726 updates in Table 1, Table 8 and on page 20: the minimum peak reflow temperature when
using SnPb solder is changed from 210 °C to 215 °C
01 20050524 initial version

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 3 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
1. Introduction
This application note provides guidelines for board mounting of surface mount IC
packages. Nowadays, reflow soldering is a widely spread technology for soldering of
surface mount IC packages. For some of the newer IC packages, such as Ball Grid Arrays
(BGAs), reflow soldering is the only suitable method.
This application note describes the materials for reflow soldering: the Printed-Circuit
Board (PCB), IC packages and solder paste. One of the key features of the PCB is the
footprint design. The footprint design describes the recommended solder land on the PCB
to make a reliable solder joint between the IC package and the PCB. A proven solder
material is SnPb, but due to legislation, the industry has changed, to a large extent, to
Pb-free solutions such as SAC. Process requirements for solder paste printing and reflow
soldering, for SnPb and Pb-free, are also discussed in this application note. This
document concludes with a section about inspection and repair.
2. Materials
2.1 Printed-circuit boards and footprints
Printed-Circuit Boards (PCBs) are not only used as mechanical carriers for electronic
components; they also provide the electronic interconnection between these components
and also between these components and the outside world. These electronic components
may be ICs, or other types such as capacitors and resistors. Through component
selection and the use of Cu interconnections between the components, an electronic
system, such as a mobile phone, can be assembled on a PCB. The substrates used for
mounting the packages can be made of a variety of materials, including FR4 and flexible
polymers.
Due to the increased transistor density in the latest IC technologies, generation of heat
has become a major limitation of IC performance. By applying an exposed pad or heat
sink in the IC package, in combination with thermal vias in the PCB, the heat can be
transferred from the active die to the outside world. Four examples of vias capped in
different ways, are shown in Figure 1. Note that the only difference lies in the solder resist
pattern.
Common board finishes include NiAu, Organic Solderability Preservative (OSP), and
immersion Sn. Although finishes may look different after reflow, and some appear to have
better wetting characteristics than others, all common finishes can be used, provided that
they are in accordance with the specifications.
Fig 1. Capped vias; from left to right: via tenting from top, via tenting from bottom, via
capping from bottom, via encroached from bottom
001aac754

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 4 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
Examples of other issues in board quality are tolerances on the pad and solder resist
dimensions and component placement, maximum board dimensions, and flatness.
A footprint design describes the recommended dimensions of the solder lands on the
PCB, to make reliable solder joints between the IC package and the PCB. The PCB
footprints of NXP Semiconductors packages can be found by clicking ‘Package
Information’ on the ‘Product Information’ page of the NXP Semiconductors web site at the
URL given in “Contact information” at the bottom of page 2. The unique identifier for the
PCB footprint is the NXP package outline code (the package SOT number). The next
paragraph explains how to read the PCB footprint. Figure 2 shows an example of a PCB
footprint, as found on the NXP Semiconductors web site.

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 5 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
Fig 2. PCB footprint for the SOT266-1 package (SSOP20)
DIMENSIONS in mm
Ay By D1 D2 Gy HyP1
7.200 4.500 1.350 0.400
C
0.600 6.900 5.300
Gx
7.450
Hx
7.3000.650
SOT266-1
solder land
occupied area
Footprint information for reflow soldering of SSOP20 package
AyByGy
C
Hy
Hx
Gx
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
(0.125) (0.125)
D1
D2 (4x)
P2
0.750
001aaf255

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 6 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
All footprints within a package family (in this example all SSOP packages) use the same
generic footprint drawing, regardless of the actual number of package terminals. In this
example, it is not accidental that the generic footprint drawing shows 18 terminals,
whereas the SSOP20 package has 20 terminals. The table on the PCB footprint, below
the drawing, shows the actual dimensions for the specific package outline (with 20
terminals), while the generic drawing is used to illustrate the dimensions. The real
package outline (with the correct number of terminals) can be found under ‘Package
information’ on the ‘Product information’ page of the NXP Semiconductors web site at the
URL given in “Contact information” at the bottom of page 2.
The soldering process is carried out under a set of process parameters that includes
accuracies in the process, and IC package, board, and stencil tolerances. The footprint
design is directly related to these aspects of the soldering process; the calculation of
these dimensions is based on process parameters that are compliant with modern
machines and a state-of-the-art process.
A solder resist layer (also known as a solder mask layer) is usually applied to the board, to
isolate the solder lands and tracks. If this solder resist extends onto the Cu, the remaining
solderable area is solder resist defined. This is sometimes referred to as Solder Mask
Defined (SMD). Figure 3 shows solder resist defined pads; yellow is Cu and dark green is
solder resist. The Cu underneath the solder resist is shown in a lighter shade of green.
The alternative situation is that the solder resist layer starts outside of the Cu. In that case,
the solder lands are Cu defined. This is sometimes referred to as Non Solder Mask
Defined (NSMD). A Cu defined layout is shown in Figure 4 (white is the bare board).
A layout may also be partially solder resist defined and partially Cu defined.
Fig 3. Solder resist defined solder lands
Fig 4. Cu defined solder lands
001aac831
001aac832

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 7 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
Note that a solder resist defined layout requires the application of a solder resist bridge
between two terminals. There is a minimum width of solder resist that can be applied by
board suppliers. This fact, in combination with a maximum solder resist placement
accuracy, implies that solder resist defined layouts are not always possible. For IC
packages with a small pitch, it is no longer possible to apply a solder resist bridge
between two terminals, and a Cu defined or combination layout must be used.
If a solder land is solder resist defined, the Cu must extend far enough underneath the
solder resist to allow for tolerances in Cu etching and solder resist placement during board
production. Similarly, if a solder land is Cu defined, the solder resist must lie sufficiently far
away from the solder land to prevent bleeding of the solder resist onto the Cu pad. Typical
values for these distances are 50 µm to 75 µm.
The footprints referred to in this document indicate the areas that can be soldered.
The footprint shown in Figure 2 is redefined for both a solder resist and a Cu layout, in
Figure 5. Note that the overlap/gap between the solder resist and the Cu is 0.05 mm in
this particular example.
2.2 IC packages
IC packages may be divided into groups in various ways. In this document, they are
categorized according to the shape of the terminals, as this has the largest influence on
board assembly. Accordingly, the three main IC family types are the leaded packages
(such as QFPs), the leadless packages with solder balls (such as BGAs) or leadless
packages with solder lands (such as HVQFNs). Apart from the terminals, packages may
have heat sinks and/or ground connections.
Fig 5. Solder land dimensions for SOT266-1 package, either solder resist or Cu defined
001aac833
0.65 mm
0.05 mm
1.35 mm
0.05 mm
1.35 mm
0.4 mm
1.35 mm
0.4 mm 0.05 mm 0.05 mm
footprint
dimensions
solder resist defined copper defined
0.65 mm 0.4 mm
0.65 mm

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 8 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
Leaded packages (e.g. SO and QFP)
•With leaded packages, coplanarity is an important issue; coplanarity must be within
the specifications (refer to the package outline drawing) in order to prevent the
occurrence of open circuits or bad joints; poor coplanarity may also increase
problems caused by board warpage
•The tips of leads, where they are cut out of the lead frame, do not have to be wetted
after reflow
•Within NXP, two possible lead finishes are applied: pure Sn and NiPdAu; the finish
used depends on the package family. SnPb finish is still used, but only for selected
applications
•Leaded packages are reflow solderable; standard gull wing packages are wave
solderable only if the lead pitch is equal to, or larger than 0.65 mm and no exposed
heatsink is present; wave soldering smaller pitches will lead to a higher defect level
Leadless packages with solder balls (e.g. BGA and TFBGA)
•These IC packages are particularly good at self-alignment, as the package body is
essentially suspended over molten solder during reflow; therefore, this package type
results in a robust reflow soldering process
•The balls are made of SnPb, or SAC for Pb-free applications
•Packages with solder balls are only reflow solderable, they cannot be wave soldered
Fig 6. Package types
Fig 7. Example of a QFP
001aac834
leads
solder ballsterminal types
lands (leadless)
001aac835

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 9 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
Leadless packages with solder lands (e.g. HVQFN and HVSON)
•The exposed lead frame edges at the sides of the IC packages are often not finished
- these do not have to be wetted for a proper joint
•Possible solder land finishes are SnPb, and pure Sn or NiPdAu for Pb-free
applications
•Leadless packages with solder lands are reflow solderable only, they cannot be wave
soldered
IC packages may have heat sinks at the top or the bottom of the package. A few extra
remarks are made on IC packages with heat sinks at the bottom (such as HVQFNs):
•Even if the exposed pad does not have to be soldered to the board for electrical or
thermal purposes, the package reliability may improve if it is soldered to the board
•Voids in the solder joint connecting the heat sink pad to the board are allowed,
provided that this does not conflict with demands made by the application
Fig 8. Example of a BGA
Fig 9. Example of an HVQFN
001aac836
001aac837

AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 10 of 24
NXP Semiconductors AN10365
Surface mount reflow soldering description
2.3 Solder paste
In line with european legislation, it is recommended to use lead-free solder paste,
although exemptions are granted for selected applications, such as automotive.
A wide variety of Pb-free solder pastes is available, containing combinations of tin, copper,
antimony, silver, bismuth, indium, and other elements. The different types of Pb-free
solder pastes have a wide range of melting temperatures. Solders with a high melting
point may be more suitable for the automotive industry, whereas solders with a low melting
point can be used for soldering consumer IC packages.
As a substitute for SnPb solder, the most common Pb-free paste is SAC, which is a
combination of tin (Sn), silver (Ag), and copper (Cu). These three elements are usually in
the range of 3 % to 4 % of Ag and 0 % to 1 % of Cu, which is near eutectic. SAC typically
has a melting temperature of around 217 °C, and it requires a reflow temperature of more
than 235 °C.
[1] Temperature is measured at solder joint.
A no-clean solder paste does not require cleaning after reflow soldering and is therefore
preferred, provided that this is possible within the process window. If a no-clean paste is
used, flux residues may be visible on the board after reflow.
For more information on the solder paste, please contact your solder paste supplier.
3. Moisture sensitivity level and storage
If there is moisture trapped inside a package, and the package is exposed to a reflow
temperature profile, the moisture may turn into steam, which expands rapidly. This may
cause damage to the inside of the package (delamination), and it may even result in a
cracked IC package body (the popcorn effect). A package’s sensitivity to moisture, or
Moisture Sensitivity Level (MSL), depends on the package characteristics and on the
temperature it is exposed to during reflow soldering.
The MSL of IC packages can be determined through standardized tests in which the
packages are moisturized to a predetermined level and then exposed to a temperature
profile. Studies have shown that small and thin packages reach higher temperatures
during reflow than do larger packages. Therefore, small and thin packages must be
classified at higher reflow temperatures.
The temperatures that packages are exposed to are always measured at the top of the
package body.
Depending on the damage after this test, an MSL of 1 (not sensitive to moisture) to 6 (very
sensitive to moisture) is attached to the IC package. For every product, this MSL is given
on a packing label on the shipping box. Each package is rated at two temperatures, for
SnPb and Pb-free soldering conditions. An example of a packing label is given in
Figure 10.
Table 1. Typical solder paste characteristics
Solder Melting temperature Minimum peak reflow
temperature[1]
SAC 217 °C 235 °C
SnPb 183 °C 215 °C