NXP Semiconductors MWCT1014SF Series User manual

MWCT101xS Series Reference
Manual
Supports MWCT1014SFxxx, MWCT1015SFxxx, MWCT1016SFxxx
Document Number: MWCT101XSFRM
Rev. 3, 07/2019

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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 43
1.2 Organization..................................................................................................................................................................43
1.3 Module descriptions......................................................................................................................................................43
1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 44
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 45
1.4 Register descriptions.....................................................................................................................................................46
1.5 Conventions.................................................................................................................................................................. 47
1.5.1 Notes, Cautions, and Warnings......................................................................................................................47
1.5.2 Numbering systems........................................................................................................................................47
1.5.3 Typographic notation..................................................................................................................................... 48
1.5.4 Special terms..................................................................................................................................................48
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................51
2.2 MWCT101xS Series introduction.................................................................................................................................51
2.3 Feature summary...........................................................................................................................................................52
2.4 Block diagram...............................................................................................................................................................55
2.5 Feature comparison.......................................................................................................................................................56
2.6 Applications..................................................................................................................................................................58
2.7 Module functional categories........................................................................................................................................58
2.7.1 Arm Cortex-M4F Core Modules....................................................................................................................59
2.7.2 System modules............................................................................................................................................. 60
2.7.3 Memories and memory interfaces..................................................................................................................61
2.7.4 Power Management........................................................................................................................................62
2.7.5 Clocking.........................................................................................................................................................62
2.7.6 Analog modules............................................................................................................................................. 62
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2.7.7 Timer modules............................................................................................................................................... 63
2.7.8 Communication interfaces............................................................................................................................. 64
2.7.9 Debug modules.............................................................................................................................................. 64
Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................65
3.2 SRAM memory map.....................................................................................................................................................65
3.3 Flash memory map........................................................................................................................................................65
3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................66
3.4.1 Read-after-write sequence and required serialization of memory operations................................................67
3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................68
3.6 Aliased bit-band regions............................................................................................................................................... 68
Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction...................................................................................................................................................................71
4.2 Functional description...................................................................................................................................................71
4.3 Pad description..............................................................................................................................................................72
4.4 Default pad state........................................................................................................................................................... 73
4.5 Signal Multiplexing sheet............................................................................................................................................. 74
4.5.1 IO Signal Table ............................................................................................................................................. 74
4.5.2 Input muxing table......................................................................................................................................... 76
4.6 Pinout diagrams............................................................................................................................................................ 77
Chapter 5
Security Overview
5.1 Introduction...................................................................................................................................................................79
5.2 Device security..............................................................................................................................................................79
5.2.1 Flash memory security...................................................................................................................................79
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................80
5.2.3 Device Boot modes........................................................................................................................................ 81
5.3 Security use case examples...........................................................................................................................................81
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5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 81
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 82
5.3.3 Secure communication...................................................................................................................................83
5.3.4 Component protection....................................................................................................................................84
5.3.5 Message-authentication example................................................................................................................... 85
5.4 Steps required before failure analysis...........................................................................................................................86
5.5 Security programming flow example (Secure Boot).................................................................................................... 87
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................89
6.2 WCT101xS safety concept........................................................................................................................................... 90
6.2.1 Cortex-M4 Structural Core Self Test (SCST)................................................................................................91
6.2.2 ECC on RAM and flash memory...................................................................................................................92
6.2.3 Power supply monitoring...............................................................................................................................92
6.2.4 Clock monitoring........................................................................................................................................... 93
6.2.5 Temporal protection.......................................................................................................................................93
6.2.6 Operational interference protection............................................................................................................... 93
6.2.7 CRC................................................................................................................................................................95
6.2.8 Diversity of system resources........................................................................................................................ 95
Chapter 7
Core Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................97
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 98
7.1.2 System Tick Timer.........................................................................................................................................98
7.1.3 Debug facilities.............................................................................................................................................. 98
7.1.4 Caches............................................................................................................................................................ 99
7.1.5 Core privilege levels...................................................................................................................................... 99
7.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 100
7.2.1 Interrupt priority levels.................................................................................................................................. 100
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7.2.2 Non-maskable interrupt..................................................................................................................................101
7.2.3 Determining the bitfield and register location for configuring a particular interrupt.................................... 101
7.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................102
7.3.1 Wake-up sources............................................................................................................................................102
7.4 FPU configuration.........................................................................................................................................................103
7.5 JTAG controller configuration......................................................................................................................................104
Chapter 8
Miscellaneous Control Module (MCM)
8.1 Chip-specific MCM information.................................................................................................................................. 105
8.2 Introduction...................................................................................................................................................................105
8.2.1 Features.......................................................................................................................................................... 105
8.3 Memory map/register descriptions............................................................................................................................... 106
8.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................107
8.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 107
8.3.3 Core Platform Control Register (MCM_CPCR)............................................................................................109
8.3.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 112
8.3.5 Process ID Register (MCM_PID)..................................................................................................................115
8.3.6 Compute Operation Control Register (MCM_CPO)..................................................................................... 116
8.3.7 Local Memory Descriptor Register (MCM_LMDRn)...................................................................................117
8.3.8 Local Memory Descriptor Register2 (MCM_LMDR2).................................................................................120
8.3.9 LMEM Parity and ECC Control Register (MCM_LMPECR).......................................................................124
8.3.10 LMEM Parity and ECC Interrupt Register (MCM_LMPEIR)...................................................................... 124
8.3.11 LMEM Fault Address Register (MCM_LMFAR).........................................................................................126
8.3.12 LMEM Fault Attribute Register (MCM_LMFATR).....................................................................................127
8.3.13 LMEM Fault Data High Register (MCM_LMFDHR).................................................................................. 128
8.3.14 LMEM Fault Data Low Register (MCM_LMFDLR)....................................................................................128
8.4 Functional description...................................................................................................................................................129
8.4.1 Interrupts........................................................................................................................................................ 129
Chapter 9
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System Integration Module (SIM)
9.1 Chip-specific SIM information.....................................................................................................................................131
9.1.1 SIM register bitfield implementation.............................................................................................................131
9.2 Introduction...................................................................................................................................................................131
9.2.1 Features.......................................................................................................................................................... 131
9.3 Memory map and register definition.............................................................................................................................132
9.3.1 SIM register descriptions............................................................................................................................... 132
Chapter 10
Port Control and Interrupts (PORT)
10.1 Chip-specific PORT information..................................................................................................................................159
10.1.1 Number of PCRs............................................................................................................................................ 159
10.1.2 Finding address for PORTx_PCRn ...............................................................................................................160
10.1.3 I/O configuration sequence ........................................................................................................................... 160
10.1.4 Digital input filter configuration sequence ................................................................................................... 161
10.1.5 Reset pin configuration.................................................................................................................................. 162
10.2 Introduction...................................................................................................................................................................162
10.3 Overview.......................................................................................................................................................................162
10.3.1 Features.......................................................................................................................................................... 162
10.3.2 Modes of operation........................................................................................................................................ 163
10.4 External signal description............................................................................................................................................164
10.5 Detailed signal description............................................................................................................................................164
10.6 Memory map and register definition.............................................................................................................................164
10.6.1 Pin Control Register n (PORTx_PCRn).........................................................................................................172
10.6.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................175
10.6.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................175
10.6.4 Global Interrupt Control Low Register (PORTx_GICLR)............................................................................ 176
10.6.5 Global Interrupt Control High Register (PORTx_GICHR)........................................................................... 176
10.6.6 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 177
10.6.7 Digital Filter Enable Register (PORTx_DFER).............................................................................................177
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10.6.8 Digital Filter Clock Register (PORTx_DFCR)..............................................................................................178
10.6.9 Digital Filter Width Register (PORTx_DFWR)............................................................................................ 178
10.7 Functional description...................................................................................................................................................179
10.7.1 Pin control......................................................................................................................................................179
10.7.2 Global pin control.......................................................................................................................................... 180
10.7.3 Global interrupt control..................................................................................................................................180
10.7.4 External interrupts..........................................................................................................................................180
10.7.5 Digital filter....................................................................................................................................................181
Chapter 11
General-Purpose Input/Output (GPIO)
11.1 Chip-specific GPIO information...................................................................................................................................183
11.1.1 Instantiation information................................................................................................................................183
11.1.2 GPIO ports memory map............................................................................................................................... 183
11.1.3 GPIO register reset values .............................................................................................................................184
11.2 Introduction...................................................................................................................................................................184
11.2.1 Features.......................................................................................................................................................... 184
11.2.2 Modes of operation........................................................................................................................................ 184
11.2.3 GPIO signal descriptions............................................................................................................................... 185
11.3 Memory map and register definition.............................................................................................................................186
11.3.1 GPIO register descriptions.............................................................................................................................186
11.4 Functional description...................................................................................................................................................193
11.4.1 General-purpose input....................................................................................................................................193
11.4.2 General-purpose output..................................................................................................................................193
Chapter 12
Crossbar Switch Lite (AXBS-Lite)
12.1 Chip-specific AXBS-Lite information..........................................................................................................................195
12.1.1 Crossbar Switch master assignments............................................................................................................. 195
12.1.2 Crossbar Switch slave assignments................................................................................................................195
12.2 Introduction...................................................................................................................................................................196
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12.2.1 Features.......................................................................................................................................................... 196
12.3 Functional Description..................................................................................................................................................196
12.3.1 General operation...........................................................................................................................................196
12.3.2 Arbitration......................................................................................................................................................197
12.4 Initialization/application information........................................................................................................................... 199
Chapter 13
Memory Protection Unit (MPU)
13.1 Chip-specific MPU information................................................................................................................................... 201
13.1.1 MPU Slave Port Assignments........................................................................................................................201
13.1.2 MPU Logical Bus Master Assignments.........................................................................................................201
13.1.3 Current PID....................................................................................................................................................202
13.1.4 Region descriptors and slave port configuration............................................................................................202
13.2 Introduction...................................................................................................................................................................202
13.3 Overview.......................................................................................................................................................................203
13.3.1 Block diagram................................................................................................................................................203
13.3.2 Features.......................................................................................................................................................... 204
13.4 MPU register descriptions.............................................................................................................................................204
13.4.1 MPU Memory map........................................................................................................................................ 205
13.4.2 Control/Error Status Register (CESR)........................................................................................................... 207
13.4.3 Error Address Register, slave port n (EAR0 - EAR4)................................................................................... 210
13.4.4 Error Detail Register, slave port n (EDR0 - EDR4)...................................................................................... 211
13.4.5 Region Descriptor n, Word 0 (RGD0_WORD0 - RGD15_WORD0)...........................................................212
13.4.6 Region Descriptor 0, Word 1 (RGD0_WORD1)...........................................................................................214
13.4.7 Region Descriptor 0, Word 2 (RGD0_WORD2)...........................................................................................215
13.4.8 Region Descriptor 0, Word 3 (RGD0_WORD3)...........................................................................................218
13.4.9 Region Descriptor n, Word 1 (RGD1_WORD1 - RGD15_WORD1)...........................................................219
13.4.10 Region Descriptor n, Word 2 (RGD1_WORD2 - RGD15_WORD2)...........................................................220
13.4.11 Region Descriptor n, Word 3 (RGD1_WORD3 - RGD15_WORD3)...........................................................223
13.4.12 Region Descriptor Alternate Access Control 0 (RGDAAC0)....................................................................... 225
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13.4.13 Region Descriptor Alternate Access Control n (RGDAAC1 - RGDAAC15)...............................................228
13.5 Functional description...................................................................................................................................................231
13.5.1 Access evaluation macro................................................................................................................................231
13.5.2 Putting it all together and error terminations................................................................................................. 233
13.5.3 Power management........................................................................................................................................233
13.6 Initialization information.............................................................................................................................................. 234
13.7 Application information................................................................................................................................................234
Chapter 14
Peripheral Bridge (AIPS-Lite)
14.1 Chip-specific AIPS information................................................................................................................................... 237
14.1.1 Instantiation information................................................................................................................................237
14.1.2 Memory maps................................................................................................................................................ 237
14.2 Introduction...................................................................................................................................................................238
14.2.1 Features.......................................................................................................................................................... 238
14.2.2 General operation...........................................................................................................................................238
14.3 Memory map/register definition................................................................................................................................... 239
14.3.1 AIPS register descriptions..............................................................................................................................239
14.4 Functional description...................................................................................................................................................283
14.4.1 Access support............................................................................................................................................... 283
Chapter 15
Direct Memory Access Multiplexer (DMAMUX)
15.1 Chip-specific DMAMUX information......................................................................................................................... 285
15.1.1 Number of channels ...................................................................................................................................... 285
15.1.2 DMA transfers via TRGMUX trigger............................................................................................................285
15.2 Introduction...................................................................................................................................................................285
15.2.1 Overview........................................................................................................................................................286
15.2.2 Features.......................................................................................................................................................... 286
15.2.3 Modes of operation........................................................................................................................................ 287
15.3 Memory map/register definition................................................................................................................................... 287
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15.3.1 DMAMUX register descriptions....................................................................................................................287
15.4 Functional description...................................................................................................................................................289
15.4.1 DMA channels with periodic triggering capability........................................................................................289
15.4.2 DMA channels with no triggering capability.................................................................................................292
15.4.3 Always-enabled DMA sources...................................................................................................................... 292
15.5 Initialization/application information........................................................................................................................... 293
15.5.1 Reset...............................................................................................................................................................293
15.5.2 Enabling and configuring sources..................................................................................................................293
Chapter 16
Enhanced Direct Memory Access (eDMA)
16.1 Chip-specific eDMA information ................................................................................................................................297
16.1.1 Number of channels ...................................................................................................................................... 297
16.2 Introduction...................................................................................................................................................................297
16.2.1 eDMA system block diagram........................................................................................................................ 298
16.2.2 Block parts..................................................................................................................................................... 298
16.2.3 Features.......................................................................................................................................................... 299
16.3 Modes of operation....................................................................................................................................................... 301
16.4 Memory map/register definition................................................................................................................................... 301
16.4.1 TCD memory................................................................................................................................................. 301
16.4.2 TCD initialization.......................................................................................................................................... 301
16.4.3 TCD structure.................................................................................................................................................302
16.4.4 Reserved memory and bit fields.....................................................................................................................302
16.4.5 DMA register descriptions.............................................................................................................................302
16.5 Functional description...................................................................................................................................................351
16.5.1 eDMA basic data flow................................................................................................................................... 351
16.5.2 Fault reporting and handling..........................................................................................................................354
16.5.3 Channel preemption....................................................................................................................................... 357
16.6 Initialization/application information........................................................................................................................... 357
16.6.1 eDMA initialization....................................................................................................................................... 357
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16.6.2 Programming errors....................................................................................................................................... 359
16.6.3 Arbitration mode considerations....................................................................................................................360
16.6.4 Performing DMA transfers............................................................................................................................ 360
16.6.5 Monitoring transfer descriptor status............................................................................................................. 364
16.6.6 Channel Linking.............................................................................................................................................366
16.6.7 Dynamic programming.................................................................................................................................. 367
16.6.8 Suspend/resume a DMA channel with active hardware service requests......................................................371
Chapter 17
Trigger MUX Control (TRGMUX)
17.1 Chip-specific TRGMUX information...........................................................................................................................373
17.1.1 Module interconnectivity............................................................................................................................... 373
17.1.2 Chip-specific TRGMUX registers................................................................................................................. 377
17.2 Introduction...................................................................................................................................................................377
17.3 Features.........................................................................................................................................................................377
17.4 Memory map and register definition.............................................................................................................................378
17.4.1 TRGMUX register descriptions.....................................................................................................................378
Chapter 18
External Watchdog Monitor (EWM)
18.1 Chip-specific EWM information.................................................................................................................................. 417
18.1.1 EWM_OUT signal configuration...................................................................................................................417
18.1.2 EWM Memory Map access............................................................................................................................417
18.1.3 EWM low-power modes................................................................................................................................ 417
18.2 Introduction...................................................................................................................................................................418
18.2.1 Features.......................................................................................................................................................... 418
18.2.2 Modes of Operation....................................................................................................................................... 419
18.2.3 Block Diagram............................................................................................................................................... 419
18.3 EWM Signal Descriptions............................................................................................................................................ 420
18.4 Memory Map/Register Definition.................................................................................................................................421
18.4.1 EWM register descriptions.............................................................................................................................421
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18.5 Functional Description..................................................................................................................................................426
18.5.1 The EWM_OUT_b Signal............................................................................................................................. 426
18.5.2 EWM_OUT_b pin state in low power modes................................................................................................427
18.5.3 The EWM_in Signal...................................................................................................................................... 427
18.5.4 EWM Counter................................................................................................................................................428
18.5.5 EWM Compare Registers.............................................................................................................................. 428
18.5.6 EWM Refresh Mechanism.............................................................................................................................428
18.5.7 EWM Interrupt...............................................................................................................................................429
18.5.8 Counter clock prescaler..................................................................................................................................429
Chapter 19
Error Injection Module (EIM)
19.1 Chip-specific EIM information.....................................................................................................................................431
19.1.1 EIM channel assignments.............................................................................................................................. 431
19.2 Introduction...................................................................................................................................................................431
19.2.1 Overview........................................................................................................................................................431
19.2.2 Features.......................................................................................................................................................... 433
19.3 EIM register descriptions..............................................................................................................................................433
19.3.1 EIM Memory map..........................................................................................................................................434
19.3.2 Error Injection Module Configuration Register (EIMCR)............................................................................ 434
19.3.3 Error Injection Channel Enable register (EICHEN)...................................................................................... 435
19.3.4 Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 - EICHD1_WORD0)............................438
19.3.5 Error Injection Channel Descriptor n, Word1 (EICHD0_WORD1 - EICHD1_WORD1)............................440
19.4 Functional description...................................................................................................................................................441
19.4.1 Error injection scenarios................................................................................................................................ 441
Chapter 20
Error Reporting Module (ERM)
20.1 Chip-specific ERM information................................................................................................................................... 443
20.1.1 Sources of memory error events.................................................................................................................... 443
20.2 Introduction...................................................................................................................................................................443
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20.2.1 Overview........................................................................................................................................................443
20.2.2 Features.......................................................................................................................................................... 444
20.3 ERM register descriptions.............................................................................................................................................444
20.3.1 ERM Memory map........................................................................................................................................ 444
20.3.2 ERM Configuration Register 0 (CR0)........................................................................................................... 445
20.3.3 ERM Status Register 0 (SR0)........................................................................................................................ 447
20.3.4 ERM Memory n Error Address Register (EAR0 - EAR1)............................................................................ 449
20.4 Functional description...................................................................................................................................................450
20.4.1 Single-bit correction events........................................................................................................................... 450
20.4.2 Non-correctable error events..........................................................................................................................451
20.5 Initialization..................................................................................................................................................................452
Chapter 21
Watchdog timer (WDOG)
21.1 Chip-specific WDOG information................................................................................................................................453
21.1.1 WDOG clocks................................................................................................................................................453
21.1.2 WDOG low-power modes............................................................................................................................. 453
21.1.3 Default watchdog timeout .............................................................................................................................454
21.1.4 Watchdog Timeout Reaction......................................................................................................................... 454
21.2 Introduction...................................................................................................................................................................455
21.2.1 Features.......................................................................................................................................................... 455
21.2.2 Block diagram................................................................................................................................................456
21.3 Memory map and register definition.............................................................................................................................456
21.3.1 WDOG register descriptions..........................................................................................................................456
21.4 Functional description...................................................................................................................................................463
21.4.1 Clock source...................................................................................................................................................463
21.4.2 Watchdog refresh mechanism........................................................................................................................464
21.4.3 Configuring the Watchdog.............................................................................................................................466
21.4.4 Using interrupts to delay resets......................................................................................................................467
21.4.5 Backup reset...................................................................................................................................................467
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21.4.6 Functionality in debug and low-power modes...............................................................................................468
21.4.7 Fast testing of the watchdog...........................................................................................................................468
21.5 Application Information................................................................................................................................................470
21.5.1 Disable Watchdog..........................................................................................................................................470
21.5.2 Disable Watchdog after Reset........................................................................................................................470
21.5.3 Configure Watchdog......................................................................................................................................471
21.5.4 Refreshing the Watchdog...............................................................................................................................471
Chapter 22
Cyclic Redundancy Check (CRC)
22.1 Chip-specific CRC information....................................................................................................................................473
22.2 Introduction...................................................................................................................................................................473
22.2.1 Features.......................................................................................................................................................... 473
22.2.2 Block diagram................................................................................................................................................474
22.2.3 Modes of operation........................................................................................................................................ 474
22.3 Memory map and register descriptions.........................................................................................................................474
22.3.1 CRC register descriptions.............................................................................................................................. 474
22.4 Functional description...................................................................................................................................................479
22.4.1 CRC initialization/reinitialization..................................................................................................................479
22.4.2 CRC calculations............................................................................................................................................479
22.4.3 Transpose feature........................................................................................................................................... 480
22.4.4 CRC result complement.................................................................................................................................482
Chapter 23
Reset and Boot
23.1 Introduction...................................................................................................................................................................483
23.2 Reset..............................................................................................................................................................................483
23.2.1 Power-on reset (POR).................................................................................................................................... 484
23.2.2 System reset sources...................................................................................................................................... 484
23.2.3 MCU Resets................................................................................................................................................... 488
23.2.4 Reset pin ........................................................................................................................................................488
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23.2.5 Debug resets...................................................................................................................................................489
23.3 Boot...............................................................................................................................................................................490
23.3.1 Boot sources...................................................................................................................................................490
23.3.2 FOPT boot options.........................................................................................................................................490
23.3.3 Boot sequence................................................................................................................................................ 491
Chapter 24
Reset Control Module (RCM)
24.1 Chip-specific RCM information................................................................................................................................... 493
24.2 Reset pin filter operation in STOP1/2 modes .............................................................................................................. 493
24.3 Introduction...................................................................................................................................................................493
24.4 Reset memory map and register descriptions............................................................................................................... 494
24.4.1 Version ID Register (RCM_VERID).............................................................................................................494
24.4.2 Parameter Register (RCM_PARAM)............................................................................................................ 496
24.4.3 System Reset Status Register (RCM_SRS)................................................................................................... 498
24.4.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 501
24.4.5 Sticky System Reset Status Register (RCM_SSRS)......................................................................................503
24.4.6 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 505
Chapter 25
Clock Distribution
25.1 Introduction...................................................................................................................................................................509
25.2 High level clocking diagram.........................................................................................................................................509
25.3 Clock definitions...........................................................................................................................................................510
25.4 Internal clocking requirements..................................................................................................................................... 512
25.4.1 Clock divider values after reset......................................................................................................................516
25.4.2 HSRUN mode clocking................................................................................................................................. 516
25.4.3 VLPR mode clocking.....................................................................................................................................516
25.4.4 VLPR/VLPS mode entry............................................................................................................................... 516
25.5 Clock Gating.................................................................................................................................................................517
25.6 Module clocks...............................................................................................................................................................517
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Chapter 26
System Clock Generator (SCG)
26.1 Chip-specific SCG information.................................................................................................................................... 529
26.1.1 Supported frequency ranges...........................................................................................................................529
26.1.2 Oscillator and SPLL guidelines..................................................................................................................... 529
26.1.3 System clock switching .................................................................................................................................530
26.1.4 System clock and clock monitor requirement ...............................................................................................530
26.2 Introduction...................................................................................................................................................................531
26.2.1 Features.......................................................................................................................................................... 531
26.3 Memory Map/Register Definition.................................................................................................................................532
26.3.1 Version ID Register (SCG_VERID)..............................................................................................................533
26.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 534
26.3.3 Clock Status Register (SCG_CSR)................................................................................................................535
26.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................537
26.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................539
26.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................541
26.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................543
26.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................545
26.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 547
26.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 548
26.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................550
26.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 551
26.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................552
26.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 553
26.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................555
26.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 556
26.3.17 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 557
26.3.18 System PLL Divide Register (SCG_SPLLDIV)............................................................................................559
26.3.19 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 560
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26.4 Functional description...................................................................................................................................................562
26.4.1 SCG Clock Mode Transitions........................................................................................................................562
Chapter 27
Peripheral Clock Controller (PCC)
27.1 Chip-specific PCC information.....................................................................................................................................565
27.1.1 Chip-specific PCC register information.........................................................................................................565
27.2 Introduction...................................................................................................................................................................565
27.3 Features.........................................................................................................................................................................566
27.4 Functional description...................................................................................................................................................567
27.5 Memory map and register definition.............................................................................................................................567
27.6 PCC register descriptions..............................................................................................................................................567
27.6.1 PCC Memory map......................................................................................................................................... 567
27.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 568
27.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 570
27.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 572
27.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 573
27.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 575
27.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................576
27.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 578
27.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................579
27.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................581
27.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................582
27.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................584
27.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................586
27.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................587
27.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................589
27.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 590
27.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 592
27.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 593
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27.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................595
27.6.20 PCC RTC Register (PCC_RTC)....................................................................................................................597
27.6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................598
27.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 600
27.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................602
27.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................603
27.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 605
27.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 606
27.6.27 PCC FlexIO Register (PCC_FlexIO).............................................................................................................608
27.6.28 PCC EWM Register (PCC_EWM)................................................................................................................609
27.6.29 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 611
27.6.30 PCC LPI2C1 Register (PCC_LPI2C1).......................................................................................................... 612
27.6.31 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 614
27.6.32 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 615
27.6.33 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 617
27.6.34 PCC FTM4 Register (PCC_FTM4)............................................................................................................... 619
27.6.35 PCC FTM5 Register (PCC_FTM5)............................................................................................................... 620
27.6.36 PCC FTM6 Register (PCC_FTM6)............................................................................................................... 622
27.6.37 PCC FTM7 Register (PCC_FTM7)............................................................................................................... 624
27.6.38 PCC CMP0 Register (PCC_CMP0)...............................................................................................................625
27.6.39 PCC QSPI Register (PCC_QSPI).................................................................................................................. 627
Chapter 28
Memories and Memory Interfaces
28.1 Introduction...................................................................................................................................................................629
28.2 Flash Memory Controller and flash memory modules................................................................................................. 629
28.3 SRAM configuration.....................................................................................................................................................629
28.3.1 SRAM sizes....................................................................................................................................................630
28.3.2 SRAM accessibility........................................................................................................................................630
28.3.3 SRAM arbitration and priority control...........................................................................................................632
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28.3.4 SRAM retention: power modes and resets.....................................................................................................632
28.3.5 SRAM access: Behavior of device when in accessing a memory with multi-bit ECC error.........................632
Chapter 29
Local Memory Controller (LMEM)
29.1 Chip-specific LMEM information................................................................................................................................ 635
29.1.1 LMEM region description..............................................................................................................................635
29.1.2 LMEM SRAM sizes.......................................................................................................................................635
29.2 Introduction...................................................................................................................................................................635
29.2.1 Block Diagram............................................................................................................................................... 635
29.2.2 Cache features................................................................................................................................................637
29.3 Memory Map/Register Definition.................................................................................................................................639
29.3.1 LMEM register descriptions.......................................................................................................................... 639
29.4 Functional Description..................................................................................................................................................648
29.4.1 LMEM Function............................................................................................................................................ 648
29.4.2 SRAM Function............................................................................................................................................. 649
29.4.3 Cache Function.............................................................................................................................................. 651
29.4.4 Cache Control................................................................................................................................................ 652
Chapter 30
Miscellaneous System Control Module (MSCM)
30.1 Chip-specific MSCM information................................................................................................................................657
30.1.1 Chip-specific TMLSZ/TMUSZ information................................................................................................. 657
30.1.2 Chip-specific register information................................................................................................................. 657
30.2 Overview.......................................................................................................................................................................658
30.3 Chip Configuration and Boot........................................................................................................................................658
30.4 MSCM Memory Map/Register Definition....................................................................................................................659
30.4.1 CPU Configuration Memory Map and Registers...........................................................................................659
30.4.2 MSCM register descriptions.......................................................................................................................... 659
Chapter 31
Flash Memory Controller (FMC)
31.1 Chip-specific FMC information....................................................................................................................................691
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