GOWIN LittleBee GW2AN-18X User manual

GW2AN-18X & 9X
Programming and Configuration Guide
UG702-1.1E, 09/06/2022

Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin
Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark
Office, and other countries. All other words and logos identified as trademarks or service
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
09/10/2021
1.0E
Initial version published.
03/04/2022
1.0.1E
The default states of configuration pins updated.
07/28/2022
1.0.2E
Note about I2C configuration mode added.
09/06/2022
1.1E
Section 5.8 I2C Configuration Mode updated.
Section 6.5 Background Programming added.

Contents
UG702-1.1E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................ 1
1.3 Terminology and Abbreviations ..........................................................................................2
1.4 Support and Feedback....................................................................................................... 3
2 Glossary ...........................................................................................................4
3 Configuration Modes.......................................................................................6
4 Configuration Pin.............................................................................................8
4.1 Configuration Pin List and Reuse Options .........................................................................8
4.1.1 Configuration Pin List ...................................................................................................... 8
4.1.2 Configuration Pin Reuse ................................................................................................. 9
4.2 Configuration Pin Function and Application ......................................................................11
5 Configuration Mode Introduction .................................................................15
5.1 Configuration Notes..........................................................................................................15
5.2 AUTO BOOT Configuration..............................................................................................18
5.3 JTAG Configuration .......................................................................................................... 19
5.3.1 JTAG Configuration Mode Pins..................................................................................... 19
5.3.2 Connection Diagram for the JTAG Configuration Mode................................................20
5.3.3 JTAG Configuration Timing ...........................................................................................21
5.3.4 JTAG Configuration Process......................................................................................... 21
5.4 SSPI ................................................................................................................................. 38
5.4.1 SSPI Mode Pins ............................................................................................................ 38
5.4.2 SSPI Configuration Timing ............................................................................................ 40
5.4.3 SSPI Configuration Instruction ...................................................................................... 40
5.4.4 SSPI Configure SRAM Flow .........................................................................................44
5.4.5 Connection Diagram for SSPI Configuration Mode ......................................................45
5.4.6 Multiple FPGA Connection View in SSPI Mode ............................................................ 46
5.5 QSSPI Configuration Mode..............................................................................................47

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5.6 CPU Configuration Mode .................................................................................................50
5.6.1 Configuration Timing ..................................................................................................... 51
5.7 SERIAL............................................................................................................................. 51
5.8 I2C Configuration Mode ....................................................................................................53
5.8.1 Configuration Instruction ...............................................................................................56
5.8.2 The Process of Configuring SRAM through I2C............................................................57
5.8.3 The Process of Configuring (Programming) Flash through I2C....................................58
6 Bitstream File Configuration.........................................................................61
6.1 Configuration Options.......................................................................................................61
6.2 Configure Data Encryption ...............................................................................................62
6.2.1 Definition .......................................................................................................................62
6.2.2 Enter Encryption KEY....................................................................................................63
6.2.3 Enter the Decrypt Key ................................................................................................... 63
6.2.4 Programming Operation................................................................................................64
6.2.5 Programming Flow ........................................................................................................66
6.3 Configuration File Size ..................................................................................................... 69
6.4 Configuration File Loading Time ......................................................................................71
6.5 Background Programming ............................................................................................... 72
7 Safety Precautions ........................................................................................73
8 Boundary Scan ..............................................................................................75

List of Figures
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List of Figures
Figure 4-1 Configuring Pin Reuse ..................................................................................................... 11
Figure 5-1 Recommended Pin Connection........................................................................................ 17
Figure 5-2 Power Recycle Timing...................................................................................................... 17
Figure 5-3 Trigger Timing................................................................................................................... 18
Figure 5-4 Connection Diagram for JTAG Configuration Mode......................................................... 20
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode ..................................... 20
Figure 5-6 JTAG Configuration timing................................................................................................21
Figure 5-7 TAP State Machine........................................................................................................... 22
Figure 5-8 Instruction Register Access Timing .................................................................................. 23
Figure 5-9 Data Register Access Timing ...........................................................................................23
Figure 5-10 Flow Chart of Reading ID Code State Machine ............................................................. 25
Figure 5-11 Access Timing of Reading ID Code Instruction - 0x11....................................................25
Figure 5-12 Access Timing of Reading ID Code Data Register......................................................... 25
Figure 5-13 SRAM Configuration Flow ...........................................................................................27
Figure 5-14 Process of Reading SRAM............................................................................................. 29
Figure 5-15 Process of Use Boundary Scan Mode to Program SPI Flash........................................ 36
Figure 5-16 Connection Diagram of Daisy-Chain..............................................................................38
Figure 5-17 SSPI Configuration Timing .............................................................................................40
Figure 5-18 Read ID Code Timing ..................................................................................................... 41
Figure 5-19 Write Enable (0x15) Timing ............................................................................................ 42
Figure 5-20 Write Disable(0x3A00) Timing........................................................................................42
Figure 5-21 Write Data (0x3B) Timing ............................................................................................... 43
Figure 5-22 SSPI Configuration Mode Connection Diagram.................................................................. 45
Figure 5-23 Connection Diagram of Programming External Flash via SSPI..................................... 45
Figure 5-24 The Flow Chart of Flash Configuration via SSPI............................................................ 46
Figure 5-25 Multiple FPGA Connection Diagram 1............................................................................46
Figure 5-26 Multiple FPGA Connection Diagram 2............................................................................47
Figure 5-27 QSSPI Write Data (0x6B) Timing ...................................................................................48
Figure 5-28 The Flow Chart of SRAM Configuration via QSSPI .......................................................49
Figure 5-29 Connection Diagram for CPU Mode...............................................................................50
Figure 5-30 CPU Mode Configuration Timing.................................................................................... 51
Figure 5-31 Connection Diagram for SERIAL Mode..........................................................................52
Figure 5-32 SERIAL Configuration Timing......................................................................................... 52
Figure 5-33 Connection Diagram for I2C Configuration Mode........................................................... 54

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Figure 5-34 I2C Configuration timing..................................................................................................54
Figure 5-35 Reinit Timing Diagram .................................................................................................... 56
Figure 5-36 SRAM Configuration Timing Diagram ............................................................................ 56
Figure 5-37 Flash Configuration Timing Diagram..............................................................................57
Figure 5-38 Reboot Timing Diagram.................................................................................................. 57
Figure 5-39 Flow Chart of Configuring SRAM through I2C................................................................58
Figure 5-40 Flow Chart of Erasing Flash through I2C：....................................................................59
Figure 5-41 Flow Chart of Configuring Flash through I2C：..............................................................60
Figure 6-1 Configuration Options....................................................................................................... 62
Figure 6-2 Encryption Key Setting Method ........................................................................................ 63
Figure 6-3 Setting the Decryption Key............................................................................................... 64
Figure 6-4 AES Security Configure.................................................................................................... 65
Figure 6-5 Prepare............................................................................................................................. 66
Figure 6-6 Read AES Key Flow ......................................................................................................... 67
Figure 6-7 Program AES Key Flow....................................................................................................68
Figure 6-8 Lock AES Key Flow ..........................................................................................................69
Figure 6-9 Bitstream Format generation............................................................................................ 70
Figure 6-9 The Background Programming Option............................................................................. 72
Figure 8-1 Boundary Scan Operation Schematic Diagram ............................................................... 76

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 2
Table 2-1 Glossary ............................................................................................................................. 4
Table 3-1 Configuration Modes..........................................................................................................6
Table 4-1 Configuration Pin List.........................................................................................................8
Table 4-2 Pin Reuse Options ............................................................................................................. 9
Table 4-3 Pin Function ....................................................................................................................... 11
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 18
Table 5-2 Pin Description in JTAG Configuration Mode..................................................................... 19
Table 5-3 JTAG Configuration Timing Parameters ............................................................................ 21
Table 5-4 Gowin FPGA Device IDCODE ........................................................................................... 24
Table 5-5 Change of TDI and TMS Value in The Process of Sending Instructions ........................... 24
Table 5-6 Count of Address and Length of One Address .................................................................. 28
Table 5-7 Pin State............................................................................................................................. 36
Table 5-8 Status Register Definition ..................................................................................................37
Table 5-9 SSPI Mode Pins ................................................................................................................. 38
Table 5-10 SSPI Configuration Timing Parameters ........................................................................... 40
Table 5-11 Configuration Instruction .................................................................................................. 41
Table 5-12 QSSPI Mode Pins ............................................................................................................ 47
Table 5-13 CPU Mode Pins................................................................................................................ 50
Table 5-14 Pin Definition in SERIAL Configuration Mode..................................................................51
Table 5-15 SERIAL Configuration Timing Parameters....................................................................... 53
Table 5-16 Pin Definition in I2C Configuration Mode.......................................................................... 53
Table 5-17 I2C Configuration Timing Parameters .............................................................................. 54
Table 5-18 I2C Configuration Mode Frequency and Address............................................................. 55
Table 5-19 I2C Configuration Instruction ............................................................................................ 56
Table 6-1 Gowin FPGA GW2AN-18X/9 X Products Configuration File Size (Max.) ..........................70
Table 6-2 Loading Time in Autoboot Mode ........................................................................................ 71

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of the GW2AN-18X/9X device in Arora
family. It helps users to use Gowin FPGA products to their full potential.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS971, GW2AN-18X and GW2AN-9X Data Sheet
UG973, GW2AN-18X and GW2AN-9X Package & Pinout User Guide
UG972, GW2AN-18X Pinout
UG978, GW2AN-9X Pinout

1 About This Guide
1.3 Terminology and Abbreviations
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and
Abbreviations
Full Name
LUT
Look-up Table
FPGA
Field Programmable Gate Array
JTAG
Joint Test Action Group
GPIO
Gowin Programmable I/O
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
MSPI
Master Serial Peripheral Interface
SSPI
Slave Serial Peripheral Interface
CPU
Central Processing Unit
IEEE
Institute of Electrical and Electronics Engineers
ID
Identification
CRC
Cyclic Redundancy Check
FS file
Fuses file
Configuration
Configuration
Configuration Data
Configuration Data
Bitstream
Bitstream Data
Configuration Mode
Configuration Mode
EFlash/EmbFlash
Embedded Flash
Internal Flash
Internal Flash
Programming
Programming
Edit Mode
Edit Mode
User Mode
User Mode
Background Programming
Embedded Flash Background Programming
LSB
Least Significant Bit
MSB
Most Significant Bit
TAP
Test Access Port
Security Bit
Security Bit
Bscan
Boundary Scan
I2C（I2C, IIC）
Inter-Integrated Circuits
SCL
Serial Clock
SDA
Serial Data

1 About This Guide
1.4 Support and Feedback
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1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Glossary
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2Glossary
This chapter presents an overview of the terms that are commonly
used in the process of programming and configuring of Gowin FPGA
products to help users get familiar with the related concepts.
Table 2-1 Glossary
Glossary
Meaning
Program
Write the bitstream data generated by Gowin software to the
embedded Flash or external SPI Flash of FPGA.
Configure
Load the bitstream data generated by Gowin software to the
FPGA SRAM via external interfaces or embedded Flash.
GowinCONFIG
In addition to the generic JTAG configuration mode, Gowin
FPGA products support additional configurations, including
AUTO BOOT configuration, DUAL BOOT configuration,
MSPI configuration, SSPI configuration, SERIAL
configuration, and CPU configuration. How many
GowinCONFIG configuration modes each device supports
depend on the device model and package.
MODE[1:0]
A representation of the two MODE pin values associated
with GowinCONFIG.
AUTO BOOT Configuration
FPGA loads bitstream data into the SRAM from an
embedded Flash. Only non-volatile devices support this
mode.
MSPI Configuration
As a master, FPGA is configured by reading bitstream from
the external Flash via the SPI interface automatically.
SSPI Configuration
As a slave device, the bitstream data is written into the
FPGA via the SPI interface by the external master.
QSSPI Configuration
As a slave device, the bitstream data is written into the
FPGA via the QSPI interface by the external master.
SERIAL Configuration
As a slave device, the bitstream data is written into the
FPGA via the serial interface by the external master.
CPU Configuration
The bitstream data is written into the FPGA via the QSPI
interface by a parallel interface (8-bit).
I2C Configuration
As a slave device, the bitstream data is written into the
FPGA via the I2C interface by the external master.

2 Glossary
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Glossary
Meaning
MULTI BOOT Configuration
The derivative concept of MSPI, it refers to that FPGA reads
bitstream data from different addresses of external Flash.
The loading address of the latter bitstream data is written in
previous bitstream data and the configuration is completed
by triggering RECONFIG_N to switch the data stream file
under the condition that the device power is on. FPGA
products that support MSPI all support this mode.
Remote Upgrade
After FPGA starts to work, if an upgrade is required, first
write bitstream to an embedded or external Flash through
remote operation, and then FPGA reads the external Flash
by triggering RECONFIG_N or powering up again to
complete the configuration.
Daisy Chain
FPGA devices are connected sequentially in a serial way.
Devices can be configured from the head of the chain in
sequence according to the connection order, and data can
only be transmitted between adjacent devices.
User Mode
Hands over control to users when the FPGA configuration
has been completed. Only in user mode, configuration pins
can be reused as GPIOs (Gowin Programmable I/O).
Edit Mode
FPGA can be programmed and configured in this mode.
All configuration pins cannot be reused as GPIOs. The
output of all GPIOs is high-impedance state, except
transparent transmission.
ID CODE
Identification for the the Gowin FPGA device. Each series of
devices has a different number.
USER CODE
Used to identify the FPGA device that used. The user code
can be written to the FPGA device through Gowin
programmer. Up to 32-bit can be supported.
Security Bit
A special design for the configuration data security of Gowin
FPGA product. After you write the bitstream with security bit
to the device SRAM, no one will be able to read back the
data. Gowin software sets a security bit for the bitstream
data of all FPGA products by default.
Encryption
The Arora family of FPGA products support this feature.
After the encrypted bitstream is written to FPGA, the device
will match the pre-stored key automatically, and then decrypt
and wake up the device after successful matching. The
device cannot work if matching fails.

3 Configuration Modes
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3Configuration Modes
Besides the JTAG configuration mode that is commonly used in the
industry, the Arora Family of FPGA products also support GOWINSEMI's
own configuration mode: GowinCONFIG. The GowinCONFIG configuration
modes that are available and supported for each device depend on the
device model and package. The Arora Family of FPGA Products support
bitstream encryption and security bit setting, which is safety for user design.
The Arora Family FPGA products support bitstream decompression; users
can compress bitstream to save storage memory.
16M-bit Serial Flash (With Quad SPI) is embedded in GW2AN-18X/9X.
Up to 100Mhz Quad SPI configuration mode can be supported, and
Fixed-Address GOLDEN-IMAGE mode is supported.
Table 3-1 lists the configuration modes that are supported by
GW2AN-18X/ 9X.
Table 3-1 Configuration Modes
Configuration Modes
MODE[1:0][1]
Description
JTAG
XX[2]
FPGA products are configured via JTAG
interface by external Host. Supports up
to 62.5 Mhz.
GowinCONFIG
MSPI
00
As a Master, FPGA reads data from the
internal Flash via the SPI interface for
configuration.. Supports up to 100 Mhz.
Autoboot
01
As a Master, FPGA reads data from the
internal Flash via the QSPI interface for
configuration.. Supports GOLDEN
IMAGE. Supports up to 100 Mhz.
SSPI
0X[3]
Supported automatically upon
completion of Autoboot or MSPI. FPGA
products are configured via SPI interface
by external Host. Supports up to 100
Mhz.
QSSPI
Supported automatically upon
completion of Autoboot or MSPI. FPGA
products are configured via QSPI

3 Configuration Modes
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Configuration Modes
MODE[1:0][1]
Description
interface by external Host. Supports up
to 100 Mhz.
I2C
Supported automatically upon
completion of Autoboot or MSPI. FPGA
products are configured via I2C interface
by external Host. The supported
frequency is 100KHz~555KHz..
SERIAL[4]
10
FPGA products are configured via DIN
interface by external Host.
CPU[4]
11
FPGA products are configured via DBUS
interface by external Host.
Note!
[1] For the value of unbound mode pins, please refer to the related pinout manuals;
[2] The JTAG configuration mode is independent of the input values of MODE [1:0];
[3] The SSPI configuration mode is independent of the input values of MODE[0];
[4] The CPU configuration mode and SERIAL configuration mode share SCLK,
WE_N and CLKHOLD_N. The data bus pins for the CPU configuration mode share
pins with MSPI and SSPI configuration modes.
Note!
For details about configuration pins, pin reuse, and pin functions and application, please
refer to 4 Configuration Pin.

4 Configuration Pin
4.1 Configuration Pin List and Reuse Options
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4Configuration Pin
Gowin FPGA products have various configuration modes, including
generic JTAG configuration, active configuration, passive configuration,
serial configuration, and parallel configuration, etc., which can meet the
various peripheral requirements of different users. The programming and
configuration pins can be used as configuration pins and also can be
reused as GPIO. Users can configure the pins as required. Users also can
configure them according to their configuration functions to meet specific
requirements.
4.1 Configuration Pin List and Reuse Options
4.1.1 Configuration Pin List
Table 4-1 contains a list of all the configuration pins of Gowin FPGA
products together with the details of the pins used in each configuration
mode and the shared pins in chip packages.
Table 4-1 Configuration Pin List
Pin Name
I/O
JTAG
GowinCONFIG
AUTO
BOOT
I2C
SSPI
QSSPI
SERIAL
CPU
RECONFIG_N
I
Yes
Yes
Yes
Yes
Yes
Yes
Yes
JTAGSEL_N
I
Yes
TDO
O
Yes
TMS
I
Yes
TCK
I
Yes
TDI
I
Yes
READY
I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DONE
I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MODE[1:0]
I
Yes
Yes
Yes
Yes
Yes
Yes
SCLK
I
Yes
Yes
Yes
Yes

4 Configuration Pin
4.1 Configuration Pin List and Reuse Options
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Pin Name
I/O
JTAG
GowinCONFIG
AUTO
BOOT
I2C
SSPI
QSSPI
SERIAL
CPU
CLKHOLD_N/DIN
I
Yes
Yes
Yes
Yes
WE_N/DOUT
O
Yes
Yes
Yes
D7
I/O
Yes
D6
I/O
Yes
D5
I/O
Yes
D4
I/O
Yes
FASTRD_N /D3
I/O
Yes
SI /D2
I/O
Yes
Yes
Yes
SO /D1
I/O
Yes
Yes
Yes
SSPI_CS_N/D0
I/O
Yes
Yes
Yes
SCL
I
Yes
SDA
I/O
Yes
Note!
For the configuration modes supported by different devices, please refer to 3
Configuration Modes;
Please refer to 5 Configuration Mode Introduction for the definition of each pin in
different configuration modes.
4.1.2 Configuration Pin Reuse
To maximize the utilization of I/O, Gowin FPGA product support for
setting the configuration pins as GPIO pins. Before any configuration
operation is performed on all series of Gowin FPGA products after power
up, all related configuration pins are used as configuration pins by default.
After successful configuration, the device enters into user mode and
reassigns the pin functions according to the multiplex options selected by
the user.
Note!
When setting the pin reuse options, ensure the external initial connection state of the pins
does not affect the device configuration. Isolate the connections that affect the
configuration first, and then wait to modify them in user mode.
The reuse options for the configuration pins are detailed in Table 4-2.
Table 4-2 Pin Reuse Options
Name
Options
Description
JTAG PORT
Default Status
TMS, TCK, TDI, and TDO are used as
dedicated configuration pins. JTAGSEL_N is
used as GPIO.
Set as GPIO
JTAGSEL_N pins are used as dedicated
configuration pins:
JTAGSEL_N=0, TMS, TCK, TDI, and
TDO are used as configuration pins:
JTAGSEL_N = 1, TMS, TCK, TDI, and
TDO are used as GPIO after
configuration.

4 Configuration Pin
4.1 Configuration Pin List and Reuse Options
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Name
Options
Description
I2C PORT
Default Status
SCL and SDA pins are used as dedicated
configuration pins.
Set as GPIO
SCL and SDA pins are used as GPIO after
configuration.
SSPI PORT
Default Status
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO are used as dedicated configuration
pins.
Set as GPIO
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO are used as GPIO after configuration.
QSSPI PORT
Default Status
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO, and QSSPI_WPN are used as
dedicated configuration pins.
Set as GPIO
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO, and QSSPI_WPN are used as GPIO
after configuration.
RECONFIG_N
Default Status
Dedicated configuration pins.
Set as GPIO
Used as GPIO after configuration.
READY
Default Status
Dedicated configuration pins.
Set as GPIO
Used as GPIO after configuration.
DONE
Default Status
Dedicated configuration pins.
Set as GPIO
Used as GPIO after configuration.
Note!
[1] For the devices with JTAGSEL_N unbound, when debugging the cases with JTAG
pin reuse, it's suggested to set MODE value to non-auto configuration mode before
power up to avoid the other bit stream data affecting configuration. After the device is
power up and JTAG is manually configured, the device enters User Mode,and the
JTAG pin is used as GPIO. For the LittleBee® Family of FPGA products, when
MODE[2: 0]=001, the JTAGSEL_N pin and the four JTAG Configuration pins (TCK,
TMS, TDI, TDO) can be set as GPIOs simultaneously, but the JTAG pin cannot be
recovered as a configuration pin by JTAGSEL_N. It can be recovered when the
device reenters the edit mode.
[2] The SERIAL and CPU modes share pins with other configuration modes and
cannot be set as GPIO separately, however, the pins can be set as GPIO in
non-shared configuration modes.
Configuration Pin Reuse
The steps are as follows:
1. Open the project in Gowin software;
2. Select “Project > Configuration > Dual Purpose Pin” from the menu
options, as shown in Figure 4-1;
3. Check the corresponding options to set the configuration pins reuse.

4 Configuration Pin
4.2 Configuration Pin Function and Application
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Figure 4-1 Configuring Pin Reuse
4.2 Configuration Pin Function and Application
The RECONFIG_N, READY, and DONE pins are used in all
configuration modes. Other pins can be set as dedicated pins or GPIO
(Gowin Programmable IO) according to their specific application.
Table 4-3 Pin Function
Pin Name
Functional Description
RECONFIG_N
As a configuration pin, RECONFIG_N is an input pin that has an
internal weak pull-up. Active low is used as the reset function for the
FPGA programming configuration. FPGA can't be configured if
RECONFIG_N is set to low. Keep high-level during FPGA
powering up until the powering up is stable for 1ms.
As a configuration pin, a low level signal with pulse width no less
than 25ns is required for GowinCONFIG to reload bitstream data
according to the MODE setting value. You can also write logic to
control the pin to trigger the device to reconfigure as required. As a
GPIO pin, RECONFIG_N can only be used as the output type. To
ensure a smooth configuration, set the initial value of RECONFIG_N
to high.
READY
In-out pins. Active-high. FPGA can be configured only when the
READY signal is pulled up. When the READY signal is pulled down,
recover the status by powering up or triggering RECONFIG_N.
As an output configuration pin, it indicates that the FPGA can be
configured or not. If the FPGA meets the configuration condition, the
READY signal is high. If the configuration fails, READY signal is low.
As an input configuration pin, you can delay the configuration via its
own logic or by pulling down the READY signal.
As a GPIO, it can be used as an input or output type. If READY is

4 Configuration Pin
4.2 Configuration Pin Function and Application
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Pin Name
Functional Description
used as an input GPIO, the initial value needs to be 1 before
configuration. Otherwise, the FPGA cannot be configured.
DONE
In-out pins. A signal which indicates FPGA is configured
successfully, DONE is pulled up after successfully configuring.
As an output configuration pin, it indicates the current configuration
of FPGA: if configured successfully, the DONE signal is high and the
device enters into working state. if the configuration fails, the DONE
signal keeps low. As an input configuration pin, the user can delay
the entering of user mode via its own internal logic or by reducing the
DONE signal. When RECONFIG_N or READY signals are low,
DONE signal also keeps low. When configuring SRAM using JTAG
circuit, it does not need to take DONE signal into account.
As a GPIO, it can be used as an input or output type. If DONE is
used as an input GPIO, the initial value of DONE should be 1
before configuring. Otherwise, the FPGA will fail to enter the
user mode after being configured.
MODE
GowinCONFIG modes selection pin. As the selection pin of
GowinCONFIG modes, MODE is an input pin that has internal weak
pull-down. The maximum bit width is 2 bits. When FPGA powers up
or a low level pulse triggers RECONFIG_N, the device enters the
corresponding GowinCONFIG mode in accordance with the MODE
value. The same MODE value of the different Gowin series of FPGA
products may have different configuration MODE. As the number of
pins for each package is different, some MODE pins are not all
bonded out, and the unbound MODE pins are grounded by default.
Please refer to the corresponding PINOUT manual for further details.
When MODE pins are used as GPIOs, they can be used as an input
or output type.
Note that when the MODE value changes, power-on again or
providing one low pulse for triggering RECONFIG_N is required for it
to take effect.
JTAGSEL_N
As a configuration pin, it is an input pin with internal weak pull-down.
If JTAG pins are set as a GPIO in the Gowin software, the JTAG pins
can become GPIOs after the device being powered up and
successfully configured. The JTAG pin configuration functions can
be recovered by pulling down JTAGSEL_N. The JTAG configuration
functions are always available if no JTAG pin reuse is set. As a
GPIO, it can be used as an input or output type.
Note!
The JTAGSEL_N pin and four JTAG pins (TCK, TMS, TDI, and TDO) are
exclusive. JTAG pins can only be used as configuration pins if JTAGSEL_N is
set as a GPIO. JTAGSEL_N can only be used as a configuration pin if JTAG
pins are set as GPIOs.
For the LittleBee® Family of FPGA products, when MODE[2: 0]=001,
the JTAGSEL_N pin and the four JTAG pins (TCK, TMS, TDI, TDO)
can be set as GPIOs simultaneously, but the JTAG pin cannot be
recovered as a configuration pin by JTAGSEL_N. It can be
recovered when the device reenters the edit mode.
TCK
As a configuration pin, it is an input pin.