GOWIN LittleBee GW2AN-18X User manual

GW2AN-18X & 9X
Programming and Configuration Guide
UG702-1.1E, 09/06/2022

Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
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and is not responsible for any damage incurred to your hardware, software, data, or
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contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
09/10/2021
1.0E
Initial version published.
03/04/2022
1.0.1E
The default states of configuration pins updated.
07/28/2022
1.0.2E
Note about I2C configuration mode added.
09/06/2022
1.1E
Section 5.8 I2C Configuration Mode updated.
Section 6.5 Background Programming added.

Contents
UG702-1.1E
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................ 1
1.3 Terminology and Abbreviations ..........................................................................................2
1.4 Support and Feedback....................................................................................................... 3
2 Glossary ...........................................................................................................4
3 Configuration Modes.......................................................................................6
4 Configuration Pin.............................................................................................8
4.1 Configuration Pin List and Reuse Options .........................................................................8
4.1.1 Configuration Pin List ...................................................................................................... 8
4.1.2 Configuration Pin Reuse ................................................................................................. 9
4.2 Configuration Pin Function and Application ......................................................................11
5 Configuration Mode Introduction .................................................................15
5.1 Configuration Notes..........................................................................................................15
5.2 AUTO BOOT Configuration..............................................................................................18
5.3 JTAG Configuration .......................................................................................................... 19
5.3.1 JTAG Configuration Mode Pins..................................................................................... 19
5.3.2 Connection Diagram for the JTAG Configuration Mode................................................20
5.3.3 JTAG Configuration Timing ...........................................................................................21
5.3.4 JTAG Configuration Process......................................................................................... 21
5.4 SSPI ................................................................................................................................. 38
5.4.1 SSPI Mode Pins ............................................................................................................ 38
5.4.2 SSPI Configuration Timing ............................................................................................ 40
5.4.3 SSPI Configuration Instruction ...................................................................................... 40
5.4.4 SSPI Configure SRAM Flow .........................................................................................44
5.4.5 Connection Diagram for SSPI Configuration Mode ......................................................45
5.4.6 Multiple FPGA Connection View in SSPI Mode ............................................................ 46
5.5 QSSPI Configuration Mode..............................................................................................47

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5.6 CPU Configuration Mode .................................................................................................50
5.6.1 Configuration Timing ..................................................................................................... 51
5.7 SERIAL............................................................................................................................. 51
5.8 I2C Configuration Mode ....................................................................................................53
5.8.1 Configuration Instruction ...............................................................................................56
5.8.2 The Process of Configuring SRAM through I2C............................................................57
5.8.3 The Process of Configuring (Programming) Flash through I2C....................................58
6 Bitstream File Configuration.........................................................................61
6.1 Configuration Options.......................................................................................................61
6.2 Configure Data Encryption ...............................................................................................62
6.2.1 Definition .......................................................................................................................62
6.2.2 Enter Encryption KEY....................................................................................................63
6.2.3 Enter the Decrypt Key ................................................................................................... 63
6.2.4 Programming Operation................................................................................................64
6.2.5 Programming Flow ........................................................................................................66
6.3 Configuration File Size ..................................................................................................... 69
6.4 Configuration File Loading Time ......................................................................................71
6.5 Background Programming ............................................................................................... 72
7 Safety Precautions ........................................................................................73
8 Boundary Scan ..............................................................................................75

List of Figures
UG702-1.1E
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List of Figures
Figure 4-1 Configuring Pin Reuse ..................................................................................................... 11
Figure 5-1 Recommended Pin Connection........................................................................................ 17
Figure 5-2 Power Recycle Timing...................................................................................................... 17
Figure 5-3 Trigger Timing................................................................................................................... 18
Figure 5-4 Connection Diagram for JTAG Configuration Mode......................................................... 20
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode ..................................... 20
Figure 5-6 JTAG Configuration timing................................................................................................21
Figure 5-7 TAP State Machine........................................................................................................... 22
Figure 5-8 Instruction Register Access Timing .................................................................................. 23
Figure 5-9 Data Register Access Timing ...........................................................................................23
Figure 5-10 Flow Chart of Reading ID Code State Machine ............................................................. 25
Figure 5-11 Access Timing of Reading ID Code Instruction - 0x11....................................................25
Figure 5-12 Access Timing of Reading ID Code Data Register......................................................... 25
Figure 5-13 SRAM Configuration Flow ...........................................................................................27
Figure 5-14 Process of Reading SRAM............................................................................................. 29
Figure 5-15 Process of Use Boundary Scan Mode to Program SPI Flash........................................ 36
Figure 5-16 Connection Diagram of Daisy-Chain..............................................................................38
Figure 5-17 SSPI Configuration Timing .............................................................................................40
Figure 5-18 Read ID Code Timing ..................................................................................................... 41
Figure 5-19 Write Enable (0x15) Timing ............................................................................................ 42
Figure 5-20 Write Disable(0x3A00) Timing........................................................................................42
Figure 5-21 Write Data (0x3B) Timing ............................................................................................... 43
Figure 5-22 SSPI Configuration Mode Connection Diagram.................................................................. 45
Figure 5-23 Connection Diagram of Programming External Flash via SSPI..................................... 45
Figure 5-24 The Flow Chart of Flash Configuration via SSPI............................................................ 46
Figure 5-25 Multiple FPGA Connection Diagram 1............................................................................46
Figure 5-26 Multiple FPGA Connection Diagram 2............................................................................47
Figure 5-27 QSSPI Write Data (0x6B) Timing ...................................................................................48
Figure 5-28 The Flow Chart of SRAM Configuration via QSSPI .......................................................49
Figure 5-29 Connection Diagram for CPU Mode...............................................................................50
Figure 5-30 CPU Mode Configuration Timing.................................................................................... 51
Figure 5-31 Connection Diagram for SERIAL Mode..........................................................................52
Figure 5-32 SERIAL Configuration Timing......................................................................................... 52
Figure 5-33 Connection Diagram for I2C Configuration Mode........................................................... 54

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Figure 5-34 I2C Configuration timing..................................................................................................54
Figure 5-35 Reinit Timing Diagram .................................................................................................... 56
Figure 5-36 SRAM Configuration Timing Diagram ............................................................................ 56
Figure 5-37 Flash Configuration Timing Diagram..............................................................................57
Figure 5-38 Reboot Timing Diagram.................................................................................................. 57
Figure 5-39 Flow Chart of Configuring SRAM through I2C................................................................58
Figure 5-40 Flow Chart of Erasing Flash through I2C：....................................................................59
Figure 5-41 Flow Chart of Configuring Flash through I2C：..............................................................60
Figure 6-1 Configuration Options....................................................................................................... 62
Figure 6-2 Encryption Key Setting Method ........................................................................................ 63
Figure 6-3 Setting the Decryption Key............................................................................................... 64
Figure 6-4 AES Security Configure.................................................................................................... 65
Figure 6-5 Prepare............................................................................................................................. 66
Figure 6-6 Read AES Key Flow ......................................................................................................... 67
Figure 6-7 Program AES Key Flow....................................................................................................68
Figure 6-8 Lock AES Key Flow ..........................................................................................................69
Figure 6-9 Bitstream Format generation............................................................................................ 70
Figure 6-9 The Background Programming Option............................................................................. 72
Figure 8-1 Boundary Scan Operation Schematic Diagram ............................................................... 76

List of Tables
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List of Tables
Table 1-1 Terminology and Abbreviations .......................................................................................... 2
Table 2-1 Glossary ............................................................................................................................. 4
Table 3-1 Configuration Modes..........................................................................................................6
Table 4-1 Configuration Pin List.........................................................................................................8
Table 4-2 Pin Reuse Options ............................................................................................................. 9
Table 4-3 Pin Function ....................................................................................................................... 11
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 18
Table 5-2 Pin Description in JTAG Configuration Mode..................................................................... 19
Table 5-3 JTAG Configuration Timing Parameters ............................................................................ 21
Table 5-4 Gowin FPGA Device IDCODE ........................................................................................... 24
Table 5-5 Change of TDI and TMS Value in The Process of Sending Instructions ........................... 24
Table 5-6 Count of Address and Length of One Address .................................................................. 28
Table 5-7 Pin State............................................................................................................................. 36
Table 5-8 Status Register Definition ..................................................................................................37
Table 5-9 SSPI Mode Pins ................................................................................................................. 38
Table 5-10 SSPI Configuration Timing Parameters ........................................................................... 40
Table 5-11 Configuration Instruction .................................................................................................. 41
Table 5-12 QSSPI Mode Pins ............................................................................................................ 47
Table 5-13 CPU Mode Pins................................................................................................................ 50
Table 5-14 Pin Definition in SERIAL Configuration Mode..................................................................51
Table 5-15 SERIAL Configuration Timing Parameters....................................................................... 53
Table 5-16 Pin Definition in I2C Configuration Mode.......................................................................... 53
Table 5-17 I2C Configuration Timing Parameters .............................................................................. 54
Table 5-18 I2C Configuration Mode Frequency and Address............................................................. 55
Table 5-19 I2C Configuration Instruction ............................................................................................ 56
Table 6-1 Gowin FPGA GW2AN-18X/9 X Products Configuration File Size (Max.) ..........................70
Table 6-2 Loading Time in Autoboot Mode ........................................................................................ 71

1 About This Guide
1.1 Purpose
UG702-1.1E
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of the GW2AN-18X/9X device in Arora
family. It helps users to use Gowin FPGA products to their full potential.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS971, GW2AN-18X and GW2AN-9X Data Sheet
UG973, GW2AN-18X and GW2AN-9X Package & Pinout User Guide
UG972, GW2AN-18X Pinout
UG978, GW2AN-9X Pinout

1 About This Guide
1.3 Terminology and Abbreviations
UG702-1.1E
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and
Abbreviations
Full Name
LUT
Look-up Table
FPGA
Field Programmable Gate Array
JTAG
Joint Test Action Group
GPIO
Gowin Programmable I/O
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
MSPI
Master Serial Peripheral Interface
SSPI
Slave Serial Peripheral Interface
CPU
Central Processing Unit
IEEE
Institute of Electrical and Electronics Engineers
ID
Identification
CRC
Cyclic Redundancy Check
FS file
Fuses file
Configuration
Configuration
Configuration Data
Configuration Data
Bitstream
Bitstream Data
Configuration Mode
Configuration Mode
EFlash/EmbFlash
Embedded Flash
Internal Flash
Internal Flash
Programming
Programming
Edit Mode
Edit Mode
User Mode
User Mode
Background Programming
Embedded Flash Background Programming
LSB
Least Significant Bit
MSB
Most Significant Bit
TAP
Test Access Port
Security Bit
Security Bit
Bscan
Boundary Scan
I2C（I2C, IIC）
Inter-Integrated Circuits
SCL
Serial Clock
SDA
Serial Data