OMNIBYTE OB688K1A User manual

MC68000"SI NG LE BOARD- COM PUTE'R,
USER'S MANUAL .
01· OMNISvTE .

OB68K1A
MC68000 SINGLE BOARD COMPUTER
USER'S MANUAL
[]I OMNIBYTE
The information in this document has been carefully checked and is believed to be entirely
reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Omnibyte reserves
the right to make changes
to any products herein to improve reliability, function, or design.
Omnibyte does not assume any liability arising out
of the application or use of any product or cir-
cuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
The technical information contained herein is provided for reference, evaluation and repair pur-
poses only and is copyrighted. It may not
be copied or duplicated in part or in whole for any pur-
pose without the express written permission
of Omnibyte Corporation.
VERSAbug &MACSbug are trademarks of Motorola, Inc.
MULTIBUS is atrademark
of Intel Corporation
OB68K1 &OB68K1A are trademarks of Omnibyte Corporation
OMNIBYTE CORP • 245 West Roosevelt Road •West Chicago, Illinois 60185 •312/231-6880
©COPYRIGHT 1983 BY OMNIBYTE CORPORATION

TABLE OF CONTENTS
Page
1.0 Introduction IInstallation ......................................... .. 4
1.1 Introduction...................................................... 4
1.2 Unpacking Instructions. .......................................... .. 4
1.3 Inspection 4
1.4 Compatibility With Multibus Products. ............................. .. 4
1.5 Factory Standard Configuration 5-6
2.0 Overview of the Computer Board. .................................. .. 7
2.1 Summary of Features ............................................ .. 7
2.2 Power Requirements. ............................................ .. 7
3.0 General Description of 0 B6SK 1A 9
3.1 Serial Interface 9
3.2 Timer 9
3.3 Parallel Interface ................................................ .. 9
3.4 Bus Arbitration. . . . . . . . . . . . . . . . . . .. .............................. .. 9
3.5 On-board Memory 10
3.5.1 On-board Read Only Memory 10
3.5.2 On-board Dynamic RAM 10-11
3.6 Address Decoding and Memory Mapping 11
3.6.1 ROM Address Selection (SW-3) 12
3.6.2 RAM Address Selection (SW-1) 12
3.6.3 I/O Base Address Selection (SW-2) 12
3.6.4 External RAM Access Address (SW-4) 12-13
3.6.5 Operational Considerations 13
3.6.6 Undecoded Addresses 13
3.7 Transfer Acknowledge and Bus Errors 13-14
3.8 Function Codes 14
3.9 Clocks 14
3.9.1 Processor Clock 15
3.9.2 Baud Rate Clock 15
3.9.3 Bus Clockand Constant Clock 15
3.9.4 The EClock 15
3.10 Interrupts 15
3.11 Status Indicators : 16
3.12 Single-Step Mode 16

3.13 Restart Vector Accessing 16
3.14 Front Panel Connector 16
4.0 User Definable Options. ............................................ 17
4.1 Serial Port Configuration (K25, K26) 19
4.1.1 Transparent Mode (K10) 19
4.1.2 Baud Rate Selection (K18, K19) 21
4.1.2.1 Manual Baud Rate Selection 21
4.1.2.2 Software Baud Rate Selection 22
4.2 Bus Error Jumper (K6) 23
4.3 DTACK Select (K20, K21) 24
4.4 Interrupt Priority (K2) 26
4.5 CCLK and BCLK (K14, K4) 27
4.6 Bus Arbitration (K5, K7, K8, K9) 27
4.7 Initialize (K3) 29
4.8 ROM Socket Configuration (K22) : 29
4.8.1 ROM Size JumperConfiguration 30
4.9 Timer(K16, K17) 33
4.10 External RAM Access (K 12, K27) 34
4.11 Watchdog Timer for External RAM Access (K23) 35
4.12 Optional Front Panel (K1) 35
4.13 MiscellaneousJumperIdentification 37
4.14 System Configuration 42
5.0 Connector Pinouts 42
5.1 Multibus P1 and P2 Connectors 42
5.2 PIA and ACIA Connectors 45
5.3 Compatible Cable End Connectors 47
6.0 Memory Decoding 48
6.1 Memory Maps 48
6.2 I/O Address Assignments 53
6.3 Motorola MEX68KDM Compatibilty 55
6.4 OB68K1/0B68K1A Compatibility/Enhancements 55-56
6.5 68000 Memory Organization 56
6.6 OB68K1ASchematic Diagrams 58
7.0 Terminal Monitor Programs 65
8.0 Warranty Information 66
9.0 Ordering Information 67
10.0 Appendix(DATA SHEETS) 67

Figure 1.0
Figure 1.1
Table 1.5
Figure 2.0
Table 4.0
Figure 4.0
Figure 4.1
Figure 4.1.1
Figure 4.1.2
Table 4.1.2.1
Table 4.3
Figure 4.3
Figure 4.4
Figure 4.6
Figure 4.7
Figure 4.8.1
Figure 4.8.2
Figure 4.8.3
Figure 4.8.4
Figure
4.9
Figure 4.10
Figure 4.12(A)
Figure 4.12(B)
Figure 4.13
Table 5.1.1
Table 5.1.2
Table 5.2.1
Table 5.2.2
Table 5.2.3
Figure 6.1.1
Figure 6.1.2
Figure 6.1.3
Figure 6.1.4
Table 6.2
Figure 6.6(A)
Figure 6.6(8)
Figure 6.6(C)
Tabl,e 6.6
LIST OF FIGURES AND TABLES
Photograph of the OB68K1 A............................... .. 1
OB68K1A Parts Location
Diagram. ......................... .. 2
Factory JumperConfiguration 5
Block Diagram. ..........................................
.. 8
JumperOptions 17
Location of JumperOptions 18
Serial Port JumperOptions 20
Tranparentllndep. Mode Jumper Location 21
Serial Port Baud Rate Jumpers 22
Baud Rate Selection 23
ROM DTACKdeiays 25
ROM DTACKdelay Jumpers 25
Interrupt Jumpers 26
Bus Arbitration JumperConfiguration 28
Reset JumperConfiguration 29
ROM Size JumperConfiguration and Location 30
ROM Configuration Plug Layouts 31
ROM Socket Configuration 32
ROM Chip Pinout Configuration 32
TimerOption Pin Identification and Location 33
External RAM Access Size Jumpers 34
Optional Front Panel -Connector 35
Optional Front Panel -Circuit 36
Miscellaneous Jumper Locations 37-41
IEEE-796 P1 Connector Pinout 43
IEEE-796 P2 Connector Pinout 44
PIA Connector Pinout. 45
ACIA Port 0Connector Pinout 46
ACIA Port 1Connector Pinout 46
Memory Map (Factory Standard) 32K Version 49
Memory Map (Factory Standard) 128KVersion 50
Memory Map Option (MAP 0) 32K Version 51
Memory Map Option (MAP 0) 128K Version 52
Onboard I/O Address Assignments 54
OB68K1A Schematic - CPU, Decoding and Buffers 59
OB68K1A Schematic -I/O 60
OB68K1 ASchematic -Memory 61
OB68K1 AParts List 62-64

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3

1.0 INTRODUCTION IINSTALLATION
The OMNIBYTE OB68K1A 68000 Single Board Computer has been carefully
de-
signed to fulfill avariety of processing applications ranging from extremely small
one board dedicated instruments
to extremely large multi-processing systems
utilizing several processor boards with shared memory and I/O. Figure
1.0 is a
photograph
of this board and Figure 1.1 is the parts location diagram.
1.1 Introduction
This chapter provides the unpacking, inspection and configuration instructions
for the OB68K1A Single Board Computer.
1.2 Unpacking Instructions
IF THE SHIPPING CARTON
IS DAMAGED UPON RECEIPT,
REQUEST THAT CARRIER'S AGENT BE PRESENT WHILE
THE ITEMS
ARE BEING UNPACKED AND INSPECTED.
Unpack the OB68K1A Single Board Computer from its shipping carton. Save the
packing material for storing and reshipping the items in case this becomes
necessary.
1.3 Inspection
The OB68K1A Single Board Computer should
be inspected upon receipt for
broken, damaged, or missing parts, and for physical damage to the printed circuit
board or connectors.
1.4 Compatibility
with Multibus Products
The OB68K1A Single Board Computer has been carefully designed
to meet the
most current IEEE
796 bus specifications. It is advised that you become familiar
with these specifications and how they compare with the original and current
Multibus specifications. The OB68K1A implements full address and bus arbitra-
tion for single and multi-processor systems and has been designed for com-
patibility with existing Multibus products. Omnibyte assumes no liability for
non-compatibility
of certain products which do not meet published IEEE 796
specifications.
4

1.5 Factory Standard Configuration
The OB68K1A Single Board Computer may be used in several configurations.
Prior to inserting the OB68K1A in asystem, care should be taken to install the
proper jumper options where necessary for your system configuration. Refer to
Figure 4.0 for physical locations of these jumpers on the OB68K1A. Included
below is factory standard configuration information.
The OB68K1A is shipped in aconfiguration that allows it to be operated in a
single master system without modification. Factory standard jumper configura-
tions are given in Table 1.5. All cut trace options are as shown on the OB68K1A
electrical schematic (See Figure 6.6). Standard jumper connections are indicated
by dashed lines on the schematic.
JUMPER GROUP CONFIGURATION FUNCTION
K3
K3-1 TO K3-2
INITline driven by OB68K1A
K4 Installed BCLK driven by OB68K1A
K5 Installed Serial Prioritization Enabled
K6 K6-2TO K6-3 BERR enabled
K7
Installed BPRN grounded
K8 Removed
BREQ for serial arbitration
K9
K9-2 TO K9-1
CBRQ connected to Multibus
K10
K10-5 TO K10-6
Normal RTS (Circuit Board Traces)
K10-4 TO K10-5
Serial Port transparent mode enabled
K11(32K)
K11-1 TO K11-2
Onboard RAM begins on 32K
boundaries (with K29 installed)
K11(128K)
K11-2 TO K11-3
Onboard RAM begins on 128K
boundaries (with K29 removed)
K12(32K)
K12-2 TO K12-3
External access RAM address begins
at 32K boundary (with K27 installed)
K12(128K) Removed External access RAM address begins
at 128K boundary (with K27 removed)
K14
Installed CCLK driven by OB68K1A
K18 Removed Hardware selected Baud Rate
K19 K19-13 TO K19-21
Serial Port 0Baud rate set to 9600
K19 K19-9 TO K19-17 Serial Port 1Baud rate set
to 9600
K20
K20-2 TO K20-3
ROM DTACK set for 4wait states
K22
Installed 2764
PROM type
K23
Removed External access watchdog
timer
enabled
K27(32K) Installed External Access RAM begins at
64K boundary (with K12 removed)
K27(128K) Removed External Access RAM begins at
128K boundary (with K12 removed)
K29(32K) Installed Onboard RAM begins at 64K
boundary (with K11 removed)
K29(128K) Removed Onboard RAM begins at 128K
boundary (with K11 removed)
FACTORY STANDARD JUMPER CONFIGURATION
TABLE 1.5
5