OMNIBYTE OB688K1A User manual

MC68000"SI NG LE BOARD- COM PUTE'R,
USER'S MANUAL .
01· OMNISvTE .

OB68K1A
MC68000 SINGLE BOARD COMPUTER
USER'S MANUAL
[]I OMNIBYTE
The information in this document has been carefully checked and is believed to be entirely
reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Omnibyte reserves
the right to make changes
to any products herein to improve reliability, function, or design.
Omnibyte does not assume any liability arising out
of the application or use of any product or cir-
cuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
The technical information contained herein is provided for reference, evaluation and repair pur-
poses only and is copyrighted. It may not
be copied or duplicated in part or in whole for any pur-
pose without the express written permission
of Omnibyte Corporation.
VERSAbug &MACSbug are trademarks of Motorola, Inc.
MULTIBUS is atrademark
of Intel Corporation
OB68K1 &OB68K1A are trademarks of Omnibyte Corporation
OMNIBYTE CORP • 245 West Roosevelt Road •West Chicago, Illinois 60185 •312/231-6880
©COPYRIGHT 1983 BY OMNIBYTE CORPORATION

TABLE OF CONTENTS
Page
1.0 Introduction IInstallation ......................................... .. 4
1.1 Introduction...................................................... 4
1.2 Unpacking Instructions. .......................................... .. 4
1.3 Inspection 4
1.4 Compatibility With Multibus Products. ............................. .. 4
1.5 Factory Standard Configuration 5-6
2.0 Overview of the Computer Board. .................................. .. 7
2.1 Summary of Features ............................................ .. 7
2.2 Power Requirements. ............................................ .. 7
3.0 General Description of 0 B6SK 1A 9
3.1 Serial Interface 9
3.2 Timer 9
3.3 Parallel Interface ................................................ .. 9
3.4 Bus Arbitration. . . . . . . . . . . . . . . . . . .. .............................. .. 9
3.5 On-board Memory 10
3.5.1 On-board Read Only Memory 10
3.5.2 On-board Dynamic RAM 10-11
3.6 Address Decoding and Memory Mapping 11
3.6.1 ROM Address Selection (SW-3) 12
3.6.2 RAM Address Selection (SW-1) 12
3.6.3 I/O Base Address Selection (SW-2) 12
3.6.4 External RAM Access Address (SW-4) 12-13
3.6.5 Operational Considerations 13
3.6.6 Undecoded Addresses 13
3.7 Transfer Acknowledge and Bus Errors 13-14
3.8 Function Codes 14
3.9 Clocks 14
3.9.1 Processor Clock 15
3.9.2 Baud Rate Clock 15
3.9.3 Bus Clockand Constant Clock 15
3.9.4 The EClock 15
3.10 Interrupts 15
3.11 Status Indicators : 16
3.12 Single-Step Mode 16

3.13 Restart Vector Accessing 16
3.14 Front Panel Connector 16
4.0 User Definable Options. ............................................ 17
4.1 Serial Port Configuration (K25, K26) 19
4.1.1 Transparent Mode (K10) 19
4.1.2 Baud Rate Selection (K18, K19) 21
4.1.2.1 Manual Baud Rate Selection 21
4.1.2.2 Software Baud Rate Selection 22
4.2 Bus Error Jumper (K6) 23
4.3 DTACK Select (K20, K21) 24
4.4 Interrupt Priority (K2) 26
4.5 CCLK and BCLK (K14, K4) 27
4.6 Bus Arbitration (K5, K7, K8, K9) 27
4.7 Initialize (K3) 29
4.8 ROM Socket Configuration (K22) : 29
4.8.1 ROM Size JumperConfiguration 30
4.9 Timer(K16, K17) 33
4.10 External RAM Access (K 12, K27) 34
4.11 Watchdog Timer for External RAM Access (K23) 35
4.12 Optional Front Panel (K1) 35
4.13 MiscellaneousJumperIdentification 37
4.14 System Configuration 42
5.0 Connector Pinouts 42
5.1 Multibus P1 and P2 Connectors 42
5.2 PIA and ACIA Connectors 45
5.3 Compatible Cable End Connectors 47
6.0 Memory Decoding 48
6.1 Memory Maps 48
6.2 I/O Address Assignments 53
6.3 Motorola MEX68KDM Compatibilty 55
6.4 OB68K1/0B68K1A Compatibility/Enhancements 55-56
6.5 68000 Memory Organization 56
6.6 OB68K1ASchematic Diagrams 58
7.0 Terminal Monitor Programs 65
8.0 Warranty Information 66
9.0 Ordering Information 67
10.0 Appendix(DATA SHEETS) 67

Figure 1.0
Figure 1.1
Table 1.5
Figure 2.0
Table 4.0
Figure 4.0
Figure 4.1
Figure 4.1.1
Figure 4.1.2
Table 4.1.2.1
Table 4.3
Figure 4.3
Figure 4.4
Figure 4.6
Figure 4.7
Figure 4.8.1
Figure 4.8.2
Figure 4.8.3
Figure 4.8.4
Figure
4.9
Figure 4.10
Figure 4.12(A)
Figure 4.12(B)
Figure 4.13
Table 5.1.1
Table 5.1.2
Table 5.2.1
Table 5.2.2
Table 5.2.3
Figure 6.1.1
Figure 6.1.2
Figure 6.1.3
Figure 6.1.4
Table 6.2
Figure 6.6(A)
Figure 6.6(8)
Figure 6.6(C)
Tabl,e 6.6
LIST OF FIGURES AND TABLES
Photograph of the OB68K1 A............................... .. 1
OB68K1A Parts Location
Diagram. ......................... .. 2
Factory JumperConfiguration 5
Block Diagram. ..........................................
.. 8
JumperOptions 17
Location of JumperOptions 18
Serial Port JumperOptions 20
Tranparentllndep. Mode Jumper Location 21
Serial Port Baud Rate Jumpers 22
Baud Rate Selection 23
ROM DTACKdeiays 25
ROM DTACKdelay Jumpers 25
Interrupt Jumpers 26
Bus Arbitration JumperConfiguration 28
Reset JumperConfiguration 29
ROM Size JumperConfiguration and Location 30
ROM Configuration Plug Layouts 31
ROM Socket Configuration 32
ROM Chip Pinout Configuration 32
TimerOption Pin Identification and Location 33
External RAM Access Size Jumpers 34
Optional Front Panel -Connector 35
Optional Front Panel -Circuit 36
Miscellaneous Jumper Locations 37-41
IEEE-796 P1 Connector Pinout 43
IEEE-796 P2 Connector Pinout 44
PIA Connector Pinout. 45
ACIA Port 0Connector Pinout 46
ACIA Port 1Connector Pinout 46
Memory Map (Factory Standard) 32K Version 49
Memory Map (Factory Standard) 128KVersion 50
Memory Map Option (MAP 0) 32K Version 51
Memory Map Option (MAP 0) 128K Version 52
Onboard I/O Address Assignments 54
OB68K1A Schematic - CPU, Decoding and Buffers 59
OB68K1A Schematic -I/O 60
OB68K1 ASchematic -Memory 61
OB68K1 AParts List 62-64

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3

1.0 INTRODUCTION IINSTALLATION
The OMNIBYTE OB68K1A 68000 Single Board Computer has been carefully
de-
signed to fulfill avariety of processing applications ranging from extremely small
one board dedicated instruments
to extremely large multi-processing systems
utilizing several processor boards with shared memory and I/O. Figure
1.0 is a
photograph
of this board and Figure 1.1 is the parts location diagram.
1.1 Introduction
This chapter provides the unpacking, inspection and configuration instructions
for the OB68K1A Single Board Computer.
1.2 Unpacking Instructions
IF THE SHIPPING CARTON
IS DAMAGED UPON RECEIPT,
REQUEST THAT CARRIER'S AGENT BE PRESENT WHILE
THE ITEMS
ARE BEING UNPACKED AND INSPECTED.
Unpack the OB68K1A Single Board Computer from its shipping carton. Save the
packing material for storing and reshipping the items in case this becomes
necessary.
1.3 Inspection
The OB68K1A Single Board Computer should
be inspected upon receipt for
broken, damaged, or missing parts, and for physical damage to the printed circuit
board or connectors.
1.4 Compatibility
with Multibus Products
The OB68K1A Single Board Computer has been carefully designed
to meet the
most current IEEE
796 bus specifications. It is advised that you become familiar
with these specifications and how they compare with the original and current
Multibus specifications. The OB68K1A implements full address and bus arbitra-
tion for single and multi-processor systems and has been designed for com-
patibility with existing Multibus products. Omnibyte assumes no liability for
non-compatibility
of certain products which do not meet published IEEE 796
specifications.
4

1.5 Factory Standard Configuration
The OB68K1A Single Board Computer may be used in several configurations.
Prior to inserting the OB68K1A in asystem, care should be taken to install the
proper jumper options where necessary for your system configuration. Refer to
Figure 4.0 for physical locations of these jumpers on the OB68K1A. Included
below is factory standard configuration information.
The OB68K1A is shipped in aconfiguration that allows it to be operated in a
single master system without modification. Factory standard jumper configura-
tions are given in Table 1.5. All cut trace options are as shown on the OB68K1A
electrical schematic (See Figure 6.6). Standard jumper connections are indicated
by dashed lines on the schematic.
JUMPER GROUP CONFIGURATION FUNCTION
K3
K3-1 TO K3-2
INITline driven by OB68K1A
K4 Installed BCLK driven by OB68K1A
K5 Installed Serial Prioritization Enabled
K6 K6-2TO K6-3 BERR enabled
K7
Installed BPRN grounded
K8 Removed
BREQ for serial arbitration
K9
K9-2 TO K9-1
CBRQ connected to Multibus
K10
K10-5 TO K10-6
Normal RTS (Circuit Board Traces)
K10-4 TO K10-5
Serial Port transparent mode enabled
K11(32K)
K11-1 TO K11-2
Onboard RAM begins on 32K
boundaries (with K29 installed)
K11(128K)
K11-2 TO K11-3
Onboard RAM begins on 128K
boundaries (with K29 removed)
K12(32K)
K12-2 TO K12-3
External access RAM address begins
at 32K boundary (with K27 installed)
K12(128K) Removed External access RAM address begins
at 128K boundary (with K27 removed)
K14
Installed CCLK driven by OB68K1A
K18 Removed Hardware selected Baud Rate
K19 K19-13 TO K19-21
Serial Port 0Baud rate set to 9600
K19 K19-9 TO K19-17 Serial Port 1Baud rate set
to 9600
K20
K20-2 TO K20-3
ROM DTACK set for 4wait states
K22
Installed 2764
PROM type
K23
Removed External access watchdog
timer
enabled
K27(32K) Installed External Access RAM begins at
64K boundary (with K12 removed)
K27(128K) Removed External Access RAM begins at
128K boundary (with K12 removed)
K29(32K) Installed Onboard RAM begins at 64K
boundary (with K11 removed)
K29(128K) Removed Onboard RAM begins at 128K
boundary (with K11 removed)
FACTORY STANDARD JUMPER CONFIGURATION
TABLE 1.5
5

The OB68K1 Ais configured at the factory to operate in the following way;
a) BUS
The Bus Clock (BCLK), Constant Clock (CCLK) and Reset line (INIT) are driven off
the board. On-board power-on reset enabled and the bus error jumper (K6) is in-
stalled so that bus error exception processing will
be executed, if abus error is
encountered.
b) INTERRUPTS
No interrupts are connected.
c) RAM
On-board RAM begins at $000000 (HEX). Contiguous RAM continues to
$007FFF (HEX) in the 32K version and to $01 FFFF (HEX) in the 128K version.
d) ROM
All on-board ROM sockets are configured for 2764-type (8Kx8) 5volt only EPROM
and the memory map is configured to MAP 1(for 2764). ROM address begins at
$FEOOOO
(HEX) and continues to $FEFFFF (HEX). The ROM DTACK is factory
preset for
350 ns (access time) ROM chips.
e) ON-BOARD SERIAL 1/0 PORTS
On-board 1/0 begins at address $FFFEOO (HEX). See table 6.2 for specific device
address assignments. Serial Port 0is configured as amodem for direct connec-
tion to a
RS232C terminal. Serial Port 1is configured as aterminal for direct con-
nection to a
RS232C modem or another computer. The baud rates are set to 9600
BPS at the factory for testing.
f) OFF-BOARD 1/0
Off-board 1/0 begins at address $FFOOOO (HEX) and continues to $FFFDFF.
g) TRANSPARENT MODE
Transparent mode is enabled.
Please note that the above is the configuration
of the OB68K1A as shipped from
the factory and
it does not include setting-up the board in a different configura-
tion
if desired before power-up_ Adetailed list of the factory installed jumper con-
figurations is given in Table
1.5. Factory standard configuration is compatible
with Omnibyte's optional
PROM based terminal monitor routines that provide the
functionality
of Motorola's MACSbug/VERSAbug/VMEbug/TUTOR programs.
6

2.0 OVERVIEW OF THE COMPUTER BOARD
This section describes the major features of the OB68K1A. A block diagram of
this single board computer is shown in Figure 2.0.
2.1 Summary of Features
The OB68K1A
computer board provides the following features:
a. 10MHz processor & clock
b. IEEE 796 (Multibus) Compatible (MASTER D16 M24 116 VOUSLAVE M24
D16)
c. Single step circuitry
d. Dual Ported on-board RAM (32K byte or 128K byte)
e. Zero wait states for on-board RAM accesses
f.
LSI Hardware memory refresh circuit
g. On-board ROM (up to 192K bytes)
h. Two asynchronous serial ports (RS232C)
i. Hardware or software programmable baud rate generator
j. Two programmable 16-bit parallel I/O ports
k. Three 16-bit programmable timers
I. 16 Megabyte (24-bit) direct memory addressing
m. Independantly Switch Selectable RAM, ROM, EXT. RAM ACCESS, and
I/O base addresses
n. Multi-Master bus arbitration
o. Motorola MEX68KDM software compatibility
2.2 Power Requirements
The
computer receives its power through the Multibus motherboard. Typical
power requirements are as follows:
+ 5V -± 50/0
+12V -± 5%
-12V- ±5%
32K VERSION 128 KVERSION
@3.0A @3.25A
@ O.05A @0.05A
@ O.05A @ O.05A
Note: Single 5volt operation is possible with the OB68K1 A if the RS232C ports
are not used.
7

MC68000
(10 MHz)
RAM
SERIAL
PORT 0-
(TERMI
NAL)
ACIA 1
~
BAUD RATE
~
GENERATOR
I-----
~
SERIAL PORT
1-
ACIA 2
~
(HOS
T)
BUS CLOCK
CONST.CLOCK
MUL TI-MASTER
BUS ARBITRATION
EXTERNAL RAM
ACCESS ARBITRATION
I
ADDRESS
DECODING-
ROM
-PAO-7
PIA 1 -PBO-7
-CONTROL
1...- __ ---1
PARALLEL PORTS
t--PAO-7
PIA 2 ~PBO-7
~CONTROL
'------I
TIMER
IEEE- 796 INTERFACE
(MULTIBUS)
I I 1
DAT A( 16) CONTROL ADDRESS(24)
OB68K1A BLOCK DIAGRAM
FIGURE 2.0
8

3.0 GENERAL DESCRIPTION OF OB68K1A
The OB68K1A is designed
to be both simple and flexible to use. Only general pur-
pose memory and I/O are included on the board. Special purpose facilities such
as disk controllers can
be added as additional Multibus boards to configure
larger systems.
3.1 Serial Interface
The two asynchronous serial ports are implemented using MC6850 Asyn-
chronous Communication Interface Adapter (ACIA) chips. The baud rates are in-
dividually selectable for standard frequencies between
50 and 19,200 baud. The
baud rate selection for each port may be determined either by hardware jumpers
or by software setting. Both ports are factory configured
to transmit and receive
without handshake lines although jumper options are provided for the normal
CTS, RTS, and DCD interface signals. All signals are received and transmitted
through
RS232C compatible buffers. The interface is made through individual,
standarp 26 pin header connectors.
3.2 Timer
Athree channel 16-bit timer (MC6840) is available on the board. This timer is in-
tended primarily for processor housekeeping. No connector is provided for input
or output signals to or from the timer -the clock, gate and output pins for each
timer are terminated on wire wrap posts near the chip. For normal applications
the timer counts the processor
"E" clock, a 1 MHz signal generated by the 68000.
3.3 Parallel Interface
Two
MC6821 Peripheral Interface Adapters (PIA) are provided on the OB68K1A.
All the interface lines are brought out on astandard
50 pin header connector. Five
volt power is also brought to this connector. The
two 8-bit PIA's are configured to
straddle the 16-bit data bus so that 16-bit data may be transferred using the A
ports or Bports
of both PIA's. Byte operations are supported on both PIA's.
3.4 Bus Arbitration
The bus arbitration circuit allows this computer to share the Multibus with other
processors or master controllers.
RAM memory that resides on this board may be
made available to other masters on the Multibus. The address of the Multibus
port
of the onboard RAM is independently selected.
9

3.5 On-Board Memory
3.5.1 On-Board Read Only Memory
The six memory sockets contained on the board are organized as three pairs
of
byte-wide memories. A minimum of 64K bytes of memory space is always
allocated
for on-board ROM. However, for ROMs of less than 64K bits each, the
total
ROM memory space will not be utilized. Only EPROM's that are pin compati-
ble with the
pinout shown in Figure 4.8.4 can be utilized on the OB68K1 A. Some
compatible memories are 2716,2732,2764,27128 and 272565 volt only, 24/28 pin
EPROM's containing 2K, 4K, 8K, 16Kand
32 Kbytes respectively. Each socket pair
is selected
with its base address and range within the allocated space arranged
so that the PROM sockets form a
contiguous block of memory. All three socket
pairs
occupy the same amount of memory. Asmall prewired PC plug is inserted in
the location provided
to configure the board for various sizes of ROM memories.
Note that 28-PINsockets are used
for all ROMs to allow for alarger base of usable
ROM chips. The base address of the ROM is selected as asingle memory block
using switch SW-3. Note that although various ROM sizes can be accommodated,
all
ROM sockets are configured for the same ROM size. Also see section 3.6.1.
3.5.2 On-Board Dynamic RAM
The OB68K1A has sixteen dynamic RAM chips.
If configured for 16Kx1 parts, a
total of 32K bytes are available. If configured for 64Kx1 parts, a total of 128K
bytes are available. The board is offered
with either the 16K or 64K parts. The
RAM is selected as a
block by the main address decoding circuit and may be ad-
dressed either in the byte
or word mode.
The on-board
dynamic RAM chips are accessed and refreshed using an LSI
DRAM controller, the DP8409. This 48-pin bipolar circuit generates the Row Ad-
dress Strobes (RAS), Column Address Strobes (CAS), drives the multiplexed ad-
dress lines, and performs the necessary refresh cycles. Under normal operation
the RAM
controller receives the processor address strobes and becomes
selected when the asserted address falls
within the RAM memory space. A 555
clock generates a 15 us pulse train to provide the basic refresh timing. The con-
troller monitors both the Address Strobe and its Chip Select inputs. When a
refresh cycle is needed the
controller waits for an Address Strobe to occur with
no Chip Select -an indication that the processor is accessing other memory or
I/O. The
controller will then perform a "hidden" refresh cycle, that is, arefresh cy-
cle
that does not take time away from the processor. If, during the 15 us period of
the refresh clock, the RAM is accessed on all Address Strobes, the controller will
request the use
of the bus, cause the processor to relinquish the bus and the
RAM
controller wi II then perform aforced refresh cycle.
10

The duration of forced refresh cycle is about 500 ns. Under most conditions the
refresh overhead
of the OB68K1A will be very low. Note that because the entire
RAM refresh task is implemented in hardware no processor code-execution
cycles are wasted to perform
RAM refresh by software.
When the processor performs aMultibus cycle, the duration
of the cycle will de-
pend on the availability of the bus and the response time of the addressed device.
During these offboard cycles, no address strobes are applied to the
RAM con-
troller and forced refreshes are then implemented when needed. The XACK signal
output by the OB68K1A signals the external master that data from the onboard
RAM has been placed on the Multibus
or the data to be written has been stored.
Shortly thereafter the external master should terminate the cycle by removing the
read or write command. If the cycle is not terminated after several microseconds,
data in the dynamic
RAM could be lost. Atimeout circuit is included on the
OB68K1A that interrupts the external access so arefresh can occur. The offboard
master is not required to wait for the completion
of an instruction. The LOCK
feature
of Multibus is implemented so an offboard master may do atest-and-set
operation to the onboard
RAM. Also see sections 3.6.2 and 3.6.4.
3.6 Address Decoding and Memory Mapping
The OB68K1A has been designed so that the memory mapping is switch selec-
table by the user. No fusible link devices are needed to change the memory map.
Four separate address decoders are included on the board to individually select
the base address
of onboard RAM, onboard ROM, I/O and the Multibus access to
the onboard
RAM. For each of these four blocks, the base address is selected by
the setting
of an 8-bit DIP switch. The dip switches have been socketed so that
dip jumpers can
be used to fix addressing for production purposes, these dip
jumpers are available through OMNIBYTE.
See section 9.0 for ordering informa-
tion. The switch setting is compared with the upper address lines to determine
when the various blocks are being selected (SWITCH BIT 1=L.S.B., SWITCH BIT
o=M.S.B.; ON = 0, OFF = 1). Much of the random logic associated with ad-
dress decoding and strobe timing has been consolidated into Programmable Ar-
ray Logic (PAL)* chips. These circuits are programmed
at the factory and cannot
be changed by the user.
*PAL is atrademark of Monolithic Memories, Inc.
11

3.6.1 ROM Address Selection (SW-3)
The 8-bit DIP switch (SW-3) is used to select the base address of the onboard
ROM. Address lines A16-23 are compared with the switch setting resulting in a
minimum
ROM block size of 64K bytes. The minimum block size will accom-
modate memories through 8K bytes per chip. For larger
ROM chips, larger
memory block sizes
of 128K and 256K bytes may be selected by removing A16 and
A
17 from the comparator inputs, respectively. All the necessary connections are
made by inserting pre-wired plugs in the location provided. Various jumper
models are available from the factory. Note
that within the ROM block, there are
addresses for which no memory exists. For example, using 8K byte PROMs, the
six sockets provided will occupy 48K
of the minimum 64K byte block size. The re-
mainder of this block is not accessable and cannot be assigned to other memory
or devices.
3.6.2
RAM Address Selection (SW-1)
The 8-bit DIP switch (SW-1) is used to select the base address of the onboard
RAM. Jumpers and cut traces at
A15 and A16 are factory configured for either32K
or 128K RAM. For 32K
RAM switch SW-1 selects base addresses on the lower 32K
block
of 64K byte boundary. For 128K RAM switch (SW-1) selects base address on
128K byte blocks. For 128K
RAM, BIT 1 of SW-1 is a "don't care" bit, since pins 13
and 14 on U28 are tied together and the cut trace option at A 16 is opened.
3.6.3 I/O Base Address Selection
(SW-2)
Because the 68000 accesses I/O the same as memory, a64K byte block of
memory space is decoded and assigned to the I/O space defined in the IEEE 796
bus specification. No options exist on the board to change the size of the I/O ad-
dress space, but the base address may be located at any 64K byte boundary
within the available
16 megabyte address range. The onboard I/O devices occupy
the uppermost
512 bytes of the I/O space; all other addresses within the block
default
to offboard I/O. Table 6.2 gives the addresses of the onboard I/O devices.
3.6.4 EXTERNAL
RAM Access Address (SW-4)
Aseparate 8-bit DIP switch and comparator are used to determine the base ad-
dress of the onboard RAM when that RAM is accessed by another Multibus
master. The
RAM is then accessed at independently selected addresses chosen
to satisfy requirements
of both the offboard master and the OB68K1 A. Address
line
A15 can be used to gate the comparator in order to decode a32K byte block
size and jumper options allow the block size to
be increased. Notice that it is
possible to
limit the amount of memory that can be accessed from offboard.
12

A128K byte OB68K1A may allow offboard masters to access 32K, 64K or all 128K
bytes
of its onboard RAM. This feature allows portions of the onboard RAM to be
protected from otheroffboard masters. Although limiting blocks of RAM from off-
board access is possible, this option has not been implemented by the factory
and should
be selected by the user if desired. Also note that in addition to the
jumper and cut trace option on
A16, pins 13 and 14 on U31 have been jumpered
and bit 1
of SW-4 is a "don't care" bit. (See Section 3.6.2).
3.6.5 Operational Considerations
When the user is setting the base address switches
of the OB68K1A care must be
exercised to avoid overlap of the onboard memory spaces of RAM ROM, and 1/0.
The offboard access to the dual-ported RAM may arbitrarily overlap any or all of
the onboard RAM, ROM, or 1/0 space.
In systems that use multiple OB68K1A computers, the onboard base address
selections may
be the same for all boards.
The external access to the OB68K1A dual-ported
RAM appears as asimple RAM
board to an external Multibus Master. Therefore, the base address of the external
access
(SW 4) must be selected to avoid overlap of the dual-ported memory space
with any other memory space on the Multibus. External access spaces
of Multiple
OB68K1A boards must not overlap. The OB68K1A is protected from accessing
its
own RAM via the Multibus by negating onboard access while performing offboard
accesses.
3.6.6 Undecoded Addresses
The
OB68K1 Ais designed so that all memory accesses default to offboard
Multibus accesses unless the address that is asserted falls within the onboard
RAM,
ROM or onboard 1/0 space.
3.7 Transfer Acknowledge and Bus Errors
The 68000's data transfers are asynchronous - A Data Transfer ACKnowledge
(DTACK) signal is required to complete
an access. For Multibus cycles this signal
is provided naturally by the Multibus Transfer ACKnowledge (XACK). For on-
board
ROM cycles, aDTACK generator is provided to terminate the cycle afixed
time after
an on-board memory access is started. The delay time is selectable to
match the access time
of the on-board ROM memory chips. (See Section 4.3).
The DTACK signal for onboard RAM access cycles is also provided by the ROM
DTACK generator and has also been optimzed for the RAM. The OB68K1A must
generate
an XACK signal when other Multibus masters access the onboard RAM.
This signal serves to terminate the bus cycle for the offboard master. Atap
on the
ROM DTACK generator is used to generate this signal at adelayed time that has
been optimized for the offboard
RAM access time and no user adjustment is per-
mitted.
13

When the OB68K1A accesses external Multibus memory or 1/0, the cycle is ter-
minated by the XACK signal returned by the board that was addressed.
In the event that unimplemented off-board memory is accessed, no DTACK will be
generated. An on-board "watchdog" timer is included to detect alack of
response, and apulse is generated that may be jumpered to the 68000 Bus Error
input pin. Asignal asserted on this pin will initiate bus error exception processing
and auser-supplied routine is executed
to allow the system to analyze the report
or recover from this condition.
Notice that the 68000 itself will patiently wait forever,
~f desired, for aDTACK
response to come. No restriction is placed on the speed
of response of the ad-
dressed memory or device. The watchdog timer delay is user determined and its
implementation is optional. It is included
to keep the system from hanging up if
no response is received.
Conditions that will cause abus error are:
a) Access to off-board memory addresses that have no responding memory (not
plugged in, or not working).
b) Access to oft-board I/O addresses that have no responsing device (not
plugged in, or not working).
An access to an on-board memory address will not cause abus error even if a
memory chip is not installed. On-board I/O uses the 68000 synchronous transfer
capability and no DTACK is required.
3.8 Function Codes
The
68000 processor outputs three function code bits, FCO, FC1, and FC2 that
allow external circuitry to know the internal operating mode
of the processor. The
~tate of these outputs indicates whether the processor is in the supervisor or user
state, whether the present access is aprogram or data reference, or
if the pro-
cessor is responding to
an interrupt. The standard configuration of the OB68K1A
makes use
of various function code values only to recognize interrupt
acknowledge cycles.
3.9 Clocks
Four clocks are generated on-board.
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3.9.1 Processor Clock
A
10 MHz crystal oscillator provides the processor clock. It connects directly to
the 68000 clock input pin. The
10 MHz clock is also used as the time base for the
DT ACK generator.
3.9.2 Baud Rate Clock
A5.0688 M Hz crystal and aCOM8116 comprise the baud rate generator. This
baud rate selection can
be done by setting four jumpers for each serial port, or by
storing the baud rate setting in the COM8116 chip under software control. These
jumper options allow the processor to dynamically control the baud rate
of either
one or both serial ports.
3.9.3 Bus Clock and Constant Clock
The
10 MHz processor clock may be used as the Multibus BCLK and CCLK.
Because only one card in aMultibus system can assert these signals, jumpers are
provided
to remove these clocks from the bus. With these jumpers removed, the
card uses the BCLK and CCLK generated by another master in the Multibus bin.
3.9.4 The EClock
The
68000 outputs an Eclock that is one-tenth the processor clock frequency.
Synchronous transfers to the on-board Motorola peripherals are made using this
1MHz clock. Accordingly, it is connected to the enable input
of the PIA, ACIA and
timer chips. This frequency is used by the timer chip when it is configured
to
count the Eclock.
3.10 Interrupts
The 68000 provides for seven levels
of prioritized auto-vectored interrupts. A
74148 priority encoder is included for inputting low active interrupts. The output
of the 74148 directly connects to the IPLO, IPL 1, IPL2 inputs of the processor. In-
terrupts outputs from the on-board peripherals and the Multibus interrupt lines
must be connected to the priority encoder by the user. Wire wrap pins are pro-
vided for each interrupt source.
The 68000 feature
of reading an interrupt vector number from the interrupting
device has not been implemented on this board.
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