Pericom PI7C7100 User manual

09/18/00 Rev1.1
PI7C7100
3-Port
PCI Bridge
The Complete Interface Solution
2380 Bering Drive, San Jose, California 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: [phone], E-mail: [email protected]
Internet: http://www.pericom.com
© 2000 Pericom Semiconductor Corporation
Pericom Semiconductor Corporation
Rev 1.1
查询PI7C7100供应商 捷多邦，专业PCB打样工厂，24小时加急出货

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
LIFESUPPORTPOLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or
systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an
officer of PSC.
1.Life support devices or systems are devices or systems which:
a) are intended for surgical implant into the body or
b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expectedtocausethefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectiveness.PericomSemiconductor
Corporationreserves therighttomakechanges toits productsorspecificationsatany time,without notice,inordertoimprove
design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility
foruse ofanycircuitrydescribedotherthanthecircuitryembodied ina PericomSemiconductor product.TheCompanymakes
no representations that circuitry described herein is free from patent infringement or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom
Semiconductor Corporation.
All other trademarks are of their respective companies.

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
1. Introduction/ProductFeatures ...............................................................................................................................1
2. PI7C7100BlockDiagram ......................................................................................................................................3
3. SignalDefinitions ...................................................................................................................................................4
3.1 Signal Types ............................................................................................................................................................4
3.2 Signals ......................................................................................................................................................................4
3.2.1 PrimaryBusInterfaceSignals ..................................................................................................................................4
3.2.2 Secondary Bus Interface Signals .............................................................................................................................6
3.2.3 ClockSignals............................................................................................................................................................8
3.2.4 Miscellaneous Signals .............................................................................................................................................8
3.2.5 JTAG Boundary Scan Signals..................................................................................................................................9
3.2.6 Power and Ground....................................................................................................................................................9
3.3 PI7C7100PBGAPinListing .....................................................................................................................................9
4. PCIBusOperation ................................................................................................................................................ 13
4.1 Types of Transactions ........................................................................................................................................... 13
4.2 Single Address Phase ............................................................................................................................................ 14
4.3 DeviceSelect(DEVSEL#)Generation .................................................................................................................... 14
4.4 Data Phase ............................................................................................................................................................. 14
4.5 Write Transactions ................................................................................................................................................ 14
4.5.1 Posted Write Transactions .................................................................................................................................... 14
4.5.2 Memory Write and Invalidate Transactions.......................................................................................................... 15
4.5.3 Delayed Write Transactions .................................................................................................................................. 15
4.5.4 Write Transaction Address Boundaries ................................................................................................................ 16
4.5.5 Buffering Multiple Write Transactions .................................................................................................................. 16
4.5.6 Fast Back-to-Back Write Transactions .................................................................................................................. 16
4.6 Read Transactions ................................................................................................................................................. 17
4.6.1 Prefetchable Read Transactions ............................................................................................................................ 17
4.6.2 Non-prefetchable Read Transactions .................................................................................................................... 17
4.6.3 Read Pre-fetch Address Boundaries...................................................................................................................... 17
4.6.4 Delayed Read Requests ......................................................................................................................................... 18
4.6.5 DelayedReadCompletionwith Target .................................................................................................................. 18
4.6.6 Delayed Read Completion on Initiator Bus ........................................................................................................... 18
4.7 Configuration Transactions ................................................................................................................................... 19
4.7.1 Type 0 Access to PI7C7100 ................................................................................................................................... 19
4.7.2 Type 1 to Type 0 Conversion ................................................................................................................................ 20
4.7.3 Type 1 to Type 1 Forwarding ................................................................................................................................ 21
4.7.4 SpecialCycles ........................................................................................................................................................ 22
4.8 TransactionTermination ........................................................................................................................................ 22
4.8.1 MasterTerminationInitiatedbyPI7C7100 ............................................................................................................ 23
4.8.2 MasterAbortReceived byPI7C7100 ..................................................................................................................... 23
4.8.3 TargetTerminationReceivedbyPI7C7100 ............................................................................................................ 24
4.8.3.1 Delayed Write Target Termination Response ....................................................................................................... 24
4.8.3.2 Posted Write Target Termination Response ......................................................................................................... 24
4.8.3.3 Delayed Read Target Termination Response ........................................................................................................ 25
4.8.4 TargetTerminationInitiatedbyPI7C7100 ............................................................................................................. 26
4.8.4.1 Target Retry ........................................................................................................................................................... 26
4.8.4.2 Target Disconnect.................................................................................................................................................. 27
Table of Contents

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
4.8.4.3 Target Abort .......................................................................................................................................................... 27
4.9 Concurrent Mode Operation.................................................................................................................................. 27
5. AddressDecoding.................................................................................................................................................. 28
5.1 Address Ranges..................................................................................................................................................... 28
5.2 I/O Address Decoding ........................................................................................................................................... 28
5.2.1 I/O Base and Limit Address Registers ................................................................................................................... 28
5.2.2 ISA Mode............................................................................................................................................................... 29
5.3 Memory Address Decoding................................................................................................................................... 29
5.3.1 Memory-Mapped I/O Base and Limit Address Registers...................................................................................... 30
5.3.2 Prefetchable Memory Base and Limit Address Registers...................................................................................... 30
5.4 VGASupport.......................................................................................................................................................... 31
5.4.1 VGAMode ............................................................................................................................................................. 31
5.4.2 VGA Snoop Mode.................................................................................................................................................. 31
6. TransactionOrdering ........................................................................................................................................... 32
6.1 Transactions Governed by Ordering Rules ........................................................................................................... 32
6.2 GeneralOrderingGuidelines .................................................................................................................................. 32
6.3 OrderingRules ....................................................................................................................................................... 33
6.4 DataSynchronization............................................................................................................................................. 34
7. ErrorHandling ...................................................................................................................................................... 35
7.1 Address Parity Errors............................................................................................................................................. 35
7.2 DataParityErrors ................................................................................................................................................... 35
7.2.1 Configuration Write Transactions to Configuration Space................................................................................... 35
7.2.2 Read Transactions ................................................................................................................................................. 36
7.2.3 Delayed Write Transactions .................................................................................................................................. 36
7.2.4 Posted Write Transactions .................................................................................................................................... 38
7.3 DataParityErrorReportingSummary .................................................................................................................... 39
7.4 SystemError(SERR#)Reporting ........................................................................................................................... 45
8. ExclusiveAccess ................................................................................................................................................... 46
8.1 ConcurrentLocks................................................................................................................................................... 46
8.2 AcquiringExclusiveAccessacrossPI7C7100....................................................................................................... 46
8.3 EndingExclusive Access ....................................................................................................................................... 47
9. PCIBusArbitration .............................................................................................................................................. 48
9.1 PrimaryPCIBusArbitration................................................................................................................................... 48
9.2 Secondary PCI Bus Arbitration ............................................................................................................................. 48
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter.......................................................................................... 48
9.2.2 Secondary Bus Arbitration Using an External Arbiter........................................................................................... 49
9.2.3 BusParking ............................................................................................................................................................ 49
10. Clocks .................................................................................................................................................................... 50
10.1 PrimaryClockInputs .............................................................................................................................................. 50
10.2 Secondary Clock Outputs ...................................................................................................................................... 50
11. Reset ...................................................................................................................................................................... 51
11.1 PrimaryInterfaceReset .......................................................................................................................................... 51
11.2 Secondary Interface Reset ..................................................................................................................................... 51
11.3 Chip Reset .............................................................................................................................................................. 51
12. SupportedCommands ............................................................................................................................................ 52
12.1 PrimaryInterface .................................................................................................................................................... 52
12.2 Secondary Interface ............................................................................................................................................... 54
13. ConfigurationRegisters ....................................................................................................................................... 55

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
13.1 ConfigRegister1.................................................................................................................................................... 55
13.2 ConfigRegister2.................................................................................................................................................... 56
13.2.1 ConfigRegister 1or2:Vendor IDRegister(read only,bit15-0;offset00h) .......................................................... 57
13.2.2 ConfigRegister1:DeviceIDRegister (readonly,bit 31-16;offset00h) ............................................................... 57
13.2.3 ConfigRegister2:DeviceIDRegister (readonly,bit 31-16;offset00h) ............................................................... 57
13.2.4 ConfigRegister1:CommandRegister(bit15-0;offset04h) .................................................................................. 57
13.2.5 ConfigRegister2:CommandRegister(bit15-0;offset04h) .................................................................................. 58
13.2.6 ConfigRegister 1 or2: StatusRegister(for primarybus, bit31-16;offset 04h)..................................................... 59
13.2.7 ConfigRegister1 or2: Revision IDRegister (read only,bit 7-0;offset08h) ......................................................... 60
13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 60
13.2.9 ConfigRegister1or2:CacheLineSizeRegister(read/write,bit7-0;offset0Ch) ................................................. 60
13.2.10 ConfigRegister1:PrimaryLatencyTimerRegister(read/write,bit15-8;offset0Ch)............................................60
13.2.11 ConfigRegister2:PrimaryLatencyTimerRegister(read/write,bit15-8;offset0Ch)............................................60
13.2.12 ConfigRegister 1: HeaderType Register(read only,bit23-16; offset0Ch).......................................................... 60
13.2.13 ConfigRegister 2: HeaderType Register(read only,bit23-16; offset0Ch).......................................................... 60
13.2.14 ConfigRegister1:PrimaryBusNumberRegister(read/write,bit7-0;offset18h) ................................................. 60
13.2.15 ConfigRegister2:PrimaryBusNumberRegister(read/write,bit7-0;offset18h) ................................................. 60
13.2.16 ConfigRegister 1or 2:Secondary BusNumberRegister (read/write,bit 15-8;offset 18h) ................................... 60
13.2.17 ConfigRegister 1or2: SubordinateBus NumberRegister(read/write, bit23-16;offset 18h)............................... 60
13.2.18 ConfigRegister1or2:SecondaryLatencyTimer(read/write,bit31-24;offset18h) ............................................ 60
13.2.19 ConfigRegister 1or2:I/OBase Register(read/write, bit7-0;offset 1Ch) ............................................................ 60
13.2.20 ConfigRegister1or2:I/OLimitRegister(read/write,bit15-8;offset1Ch)........................................................... 60
13.2.21 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 61
13.2.22 ConfigRegister1 or2:Memory BaseRegister(read/write,bit 15-0;offset20h) ................................................... 62
13.2.23 ConfigRegister1or2:MemoryLimitRegister(read/write,bit31:16;offset20h) ................................................. 62
13.2.24 ConfigRegister1 or2: PrefetchableMemory BaseRegister(read/write,bit 15-0;offset24h)............................... 62
13.2.25 ConfigRegister1or2:PrefetchableMemoryLimitRegister(read/write,bit31-16;offset24h) ............................ 62
13.2.26 Config Register1 or2: I/O BaseAddress Upper16 Bits Register(read/write, bit15-0; offset 30h)...................... 62
13.2.27 ConfigRegister 1or 2:I/OLimit AddressUpper 16BitsRegister (read/write,bit 31-16;offset30h) .................... 62
13.2.28 ConfigRegister 1or2: SubsystemVendorID(read/write,bit 15-0;offset34h) .................................................... 62
13.2.29 ConfigRegister 1or2: SubsystemID(read/write, bit31-16;offset34h)............................................................... 62
13.2.30 ConfigRegister 1 or2: Interrupt PinRegister (readonly, bit 15-8;offset 3Ch) ..................................................... 62
13.2.31 ConfigRegister1or2: BridgeControlRegister (bit31-16;offset 3Ch) ................................................................. 63
13.2.32 ConfigRegister1or2:Diagnostic/Chip ControlRegister(bit 15-0;offset40h).................................................... 64
13.2.33 ConfigRegister1 or2:ArbiterControl Register(bit31-16;offset40h)................................................................. 64
13.2.34 ConfigRegister1:PrimaryPrefetchable MemoryBaseRegister(Read/Write,bit15-0;offset44h) ..................... 65
13.2.35 ConfigRegister2:PrimaryPrefetchable MemoryBaseRegister(Read/Write,bit15-0;offset44h) ..................... 65
13.2.36 ConfigRegister1:PrimaryPrefetchableMemoryLimitRegister(Read/Write,bit31-16;offset44h).................... 65
13.2.37 ConfigRegister2:PrimaryPrefetchableMemoryLimitRegister(Read/Write,bit31-16;offset44h).................... 65
13.2.38 ConfigRegister1or2:P_SERR#EventDisableRegister(bit 7-0;offset64h) ...................................................... 65
13.2.39 ConfigRegister1: SecondaryClockControlRegister(bit15-0;offset68h).......................................................... 66
13.2.40 ConfigRegister2: SecondaryClockControlRegister(bit15-0;offset68h).......................................................... 66
13.2.41 Config Register1 or2: Non-PostedMemory BaseRegister (read/write,bit 15-0;offset 70h) .............................. 67
13.2.42 ConfigRegister1or2:Non-Posted MemoryLimitRegister(read/write,bit31-16;offset70h)............................. 67
13.2.43 ConfigRegister 1:PortOption Register(bit15-0; offset74h) ............................................................................... 67
13.2.44 ConfigRegister 2:PortOption Register(bit15-0; offset74h) ............................................................................... 68
13.2.45 Config Register1 or2: MasterTimeout CounterRegister (read/write,bit 31-16;offset 74h)................................ 69
13.2.46 ConfigRegister1 or2:Retry CounterRegister(read/write,bit31-0;offset78h) .................................................. 69
13.2.47 ConfigRegister1or2:SamplingTimerRegister(read/write,bit31-0;offset7Ch) ................................................ 69
13.2.48 Config Register1 or2: SuccessfulI/O Read CountRegister (read/write,bit 31-0;offset 80h) ............................. 69

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
13.2.49 Config Register1 or2: SuccessfulI/O Write CountRegister (read/write,bit 31-0;offset 84h)............................. 69
13.2.50 Config Register1 or2: SuccessfulMemory ReadCount Register(read/write, bit 31-0;offset 88h) ..................... 69
13.2.51 Config Register1 or2: SuccessfulMemory WriteCount Register(read/write, bit31-0; offset8Ch).................... 69
13.2.52 ConfigRegister1: PrimarySuccessful I/OReadCountRegister (read/write,bit 31-0;offset 90h) ....................... 69
13.2.53 ConfigRegister1: PrimarySuccessful I/OWriteCountRegister (read/write,bit 31-0;offset 94h)....................... 69
13.2.54 ConfigRegister1: PrimarySuccessful MemoryRead CountRegister (read/write,bit 31-0;offset98h) ............... 69
13.2.55 ConfigRegister1:Primary SuccessfulMemory WriteCount Register(read/write, bit31-0; offset9Ch).............. 69
14. BridgeBehavior .................................................................................................................................................... 70
14.1 Bridge Actions for Various Cycle Types ............................................................................................................... 70
14.2 Transaction Ordering ............................................................................................................................................. 70
14.3 Abnormal Termination(InitiatedbyBridge Master) ............................................................................................. 71
14.3.1 Master Abort ......................................................................................................................................................... 71
14.3.2 Parityand ErrorReporting ..................................................................................................................................... 71
14.3.3 ReportingParityErrors........................................................................................................................................... 71
14.3.4 SecondaryIDSELmapping .................................................................................................................................... 71
15. IEEE1149.1CompatibleJTAGController ........................................................................................................... 72
15.1 Boundary Scan Architecture ................................................................................................................................. 72
15.1.1 TAP Pins ................................................................................................................................................................ 72
15.1.2 Instruction Register ............................................................................................................................................... 72
15.2 Boundary Scan Instruction Set .............................................................................................................................. 73
15.3 TAP Test Data Registers ....................................................................................................................................... 74
15.4 Bypass Register ..................................................................................................................................................... 74
15.5 Boundary-Scan Register......................................................................................................................................... 74
15.6 TAP Controller ....................................................................................................................................................... 74
16. ElectricalandTimingSpecifications.................................................................................................................... 79
16.1 MaximumRatings ................................................................................................................................................... 79
16.2 3.3VDCSpecifications ........................................................................................................................................... 79
16.3 3.3VACSpecifications........................................................................................................................................... 80
16.4 Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 80
16.5 PowerConsumption ............................................................................................................................................... 80
17. 256-PinPBGAPackage........................................................................................................................................... 81
17.1 PartNumberOrderingInformation ........................................................................................................................ 81

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
List of Figures
1-1. PI7C7100ontheSystemBoard....................................................................................................................................2
1-2. PI7C7100inRedundantApplications ..........................................................................................................................2
1-3. PI7C7100onNetworkSwitchingHub ..........................................................................................................................2
2-1. PI7C7100BlockDiagram ..............................................................................................................................................3
9-1. SecondaryArbiterExample ....................................................................................................................................... 48
15-1. Test Access Port Block Diagram ............................................................................................................................... 72
16-1. PCISignalTimingMeasurementConditions ............................................................................................................ 80
17-1. 256-PinPBGAPackageDrawing................................................................................................................................ 81
List of Tables
4-1. PCITransaction ......................................................................................................................................................... 13
4-2. Write Transaction Forwarding .................................................................................................................................. 14
4-3. Write Transaction Disconnect Address Boundaries ................................................................................................ 16
4-4. Read Pre-fetch Address Boundaries ......................................................................................................................... 17
4-5. Read Transaction Pre-fetching .................................................................................................................................. 18
4-6. DeviceNumbertoIDSELS1_ADorS2_ADPinMapping ....................................................................................... 21
4-7. Delayed Write Target Termination Response ........................................................................................................... 24
4-8. Responses to Posted Write Target Termination ....................................................................................................... 25
4-9. Responses to Delayed Read Target Termination...................................................................................................... 25
6-1. SummaryofTranactionOrdering .............................................................................................................................. 33
7-1. SettingthePrimary InterfaceDetectedParityErrorBit ............................................................................................. 39
7-2. Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 40
7-3. Settingthe PrimaryInterfaceData ParityDetected Bit.............................................................................................. 40
7-4. Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41
7-5. Assertionof P_PERR#............................................................................................................................................... 42
7-6. Assertionof S_PERR#............................................................................................................................................... 43
7-7. Assertionof P_SERR# forData Parity Errors ........................................................................................................... 44
15-1. TAP Pins .................................................................................................................................................................... 73
15-2. JTAGBoundaryRegister Order ................................................................................................................................ 75

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
Appendix A - Timing Diagrams
1. Configuration Read Transaction .................................................................................................................................A-3
2. Configuration Write Transaction ................................................................................................................................A-3
3. Type 1 to Type 0 Configuration Read Transaction (P →S) ......................................................................................A-3
4. Type 1 to Type 0 Configuration Write Transaction (P →S) .....................................................................................A-4
5. Upstream Type 1 to Special Cycle Transaction (S →P) .............................................................................................A-4
6. Downstream Type 1 to Special Cycle Transaction (P →S) ........................................................................................A-5
7. Downstream Type 1 to Type 1 Configuration Read Transaction (P →S) ..................................................................A-5
8. Downstream Type 1 to Type 1 Configuration Write Transaction (P →S) .................................................................A-6
9. Upstream Delayed Burst Memory Read Transaction (S →P) ...................................................................................A-6
10. Downstream Delayed Burst Memory Read Transaction (P →S) ..............................................................................A-7
11. Downstream Delayed Memory Read Transaction (P/33MHz →S/33MHz)...............................................................A-7
12. Downstream Delayed Memory Read Transaction (S2/33MHz →S1/33MHz)...........................................................A-8
13. Downstream Delayed Memory Read Transaction (S1/33MHz →S2/33MHz)...........................................................A-8
14. Upstream Delayed Memory Read Transaction (S/33MHz →P/33MHz) ...................................................................A-9
15. Downstream Posted Memory Write Transaction (P/33MHz →S/33MHz)................................................................A-9
16. Downstream Posted Memory Write Transaction (S2/33MHz →S1/33MHz) ...........................................................A-10
17. Downstream Posted Memory Write Transaction (S1/33MHz →S2/33MHz) ...........................................................A-10
18. Upstream Posted Memory Write Transaction (S/33MHz →P/33MHz) ...................................................................A-11
19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz →S/33MHz)........................................A-11
20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz →S1/33MHz)....................................A-12
21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz →S2/33MHz)....................................A-12
22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz →P/33MHz) ............................................A-13
23. Downstream Delayed I/O Read Transaction (P →S) ...............................................................................................A-13
24. Downstream Delayed I/O ReadTransaction (S2/33MHz →S1/33MHz) ..................................................................A-14
25. Downstream Delayed I/O ReadTransaction (S1/33MHz →S2/33MHz) ..................................................................A-14
26. Downstream Delayed I/O Read Transaction (S/33MHz →P/33MHz) ......................................................................A-15
27. Downstream Delayed I/O Write Transaction (P →S) ..............................................................................................A-15
28. Downstream DelayedI/OWrite Transaction(S2/33MHz →S1/33MHz) .................................................................A-16
29. Downstream DelayedI/OWrite Transaction(S1/33MHz →S2/33MHz) .................................................................A-16
30. Upstream Delayed I/O Write Transaction (S →P) ...................................................................................................A-17
Appendix B - Evaluation Board User's Manual
GeneralInformation ........................................................................................................................................................... B-3
Frequently Asked Questions ............................................................................................................................................ B-5
Appendix C - Three-Port PCI Bridge Evaluation Board Schematics
PCIChip ............................................................................................................................................................................. C-3
PCIEdgeConnector .......................................................................................................................................................... C-4
Secondary 1 PCI Bus ......................................................................................................................................................... C-5
Secondary 2 PCI Bus ......................................................................................................................................................... C-6
TopView ............................................................................................................................................................................ C-7
Appendix D - Representatives and Distributors

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Product Features
• 32-bit Primary & two Secondary Ports run up to 33 MHz
• All three ports compliant with the PCI Local Bus
Specification,Revision2.1
• CompliantwithPCI-to-PCIBridgeArchitectureSpecification,Revision1.0.
- All I/O and memory commands
- Type1toType0configurationconversion
- Type1toType1configurationforwarding
- Type1configuration-writetospecialcycleconversion
• Concurrentprimarytosecondarybusoperationandindependentintra-secondaryport
channelto reducetraffic onthe primary port
• Provides internal arbitration for two sets of eight secondary bus masters
- Programmable 2-level priority arbiter
- Disable control for use of external arbiter
• Supportspostedwritebufferson all directions
• Three128byteFIFOs for delaytransactions
• Three128byteFIFOsforpostedmemorytransactions
• Enhancedaddressdecoding
- 32-bitI/Oaddressrange
- 32-bit memory-mapped I/O address range
- VGA addressing and VGA palette snooping
- ISA-aware mode for legacy support in the first 64KB
ofI/Oaddressrange
• InterruptHandling
- PCIinterruptsareroutedthroughanexternalinterruptconcentrator
• Supportssystem transaction orderingrules
• Hot-plugsupportonsecondarybuses
- 3-Statecontrolofoutputbuffers
• IEEE1149.1JTAGinterfacesupport
• 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant
• 256-pin plastic BGA package
Product Description
PI7C7100isthefirsttripleportPCI-to-PCIBridgedevicedesignedtobefullycompliantwiththe32-bit,
33 MHz implementation of the PCI Local Bus Specification, Revision 2.1 . PI7C7100 supports only
synchronousbustransactionsbetweendevicesontheprimary33MHzbusandthesecondarybuses
operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode,
resultinginaddedincreaseinsystemperformance. Concurrentbusoperationoff-loadsandisolates
unnecessarytrafficfromtheprimarybus;therebyenablingamasterandatargetdeviceonthesame
secondary PCI bus to communicate even while the primary bus is busy.
1. Introduction

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Figure 1-2. PI7C7100 in Redundant Application
Figure 1-1. PI7C7100 on the System Board
S1 PCI Bus
S2 PCI Bus
PI7C7100
CPU
NB
Slot Slot
System
Memory
PCI
Device
PCI
Device
PI7C7100
System Primary
PCI Bus
PI7C7100
S1 PCI Bus
Master Controller Redundant Controller
S2 PCI Bus
System Primary
PCI Bus
S1 S1 S2
S2
Figure 1-3. PI7C7100 on Network Switching Hub
CPU
PCI Bus 32/33
PI7C7100
PCI Bus 32/33
Core
Logic
L2
Cache
I/O Daughter
Board to
IsolateTraffic
PI7C7100 PI7C7100
Fast
Ethernet
Internal
Slot

309/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Configuration
Register #1
Arbiter
Arbiter
Secondary
Interface B
Secondary
Interface A
Secondary
PCI Bus A
Transaction
Queue #1
Transaction
Queue #2
Transaction
Queue #3
Configuration
Register #2
Primary
PCI Bus
Secondary
PCI Bus B
Primary
Interface
2. PI7C7100 Block Diagram
Figure 2-1. PI7C7100 Block Diagram

409/18/00 Rev1.1
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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
epyTlangiSnoitpircseD
IP)tnarelotV5,V3.3(tupnIICP
UIPpu-llupkaewhtiw)tnarelotV5,V3.3(tupnIICP
BP)tnarelotV5,V3.3(lanoitceridibetats-3ICP
OP)V3.3(tuptuOICP
STSP elcycenorofevitcaninevirdebtsumhcihwlangisWOLevitcA(lanoitceridibetats-3deniatsuSICP )enillangisderahsanoecnamrofrepHGIHerusneotdetats-3gnieberofeb
STPtuptuOetats-3ICP
DOP detats-3ro)etatsevitca(WOLsevirdrehtiehcihwtuptuOICP
ICtupnISOMC
UICpu-llupkaewhtiwtupnISOMC
DICnwod-llupkaewhtiwtupnISOMC
OTCtuptuOetats-3SOMC
3. Signal Definitions
3.1 Signal Types
emaN#niPepyTnoitpircseD
]0:13[DA_P,8V,8W,8Y,7W,7Y ,01W,9W,9Y,8U ,11U,11V,11Y,01V ,61V,21V,21W,21Y ,71W,61Y,61W ,81Y,81W,81U,71Y ,02U,91Y,91W,91U 71R,71T,02Y,02V BP .ataD/sserddAyramirP sisserddA.subataddnasserddadexelpitluM nehwdilavdnaelbatssiatadetirW.noitressa#EMARF_Pybdetacidni si#YDRT_Pnehwdilavdnaelbatssiataddaerdnadetressasi#YDRI_P dna#YDRI_PhtobnehwsegdekcolcgnisirnoderrefsnartsiataD.detressa dilavaotDA_Psevird0017C7IP,eldisubgniruD.detressaera#YDRT_P .detressasi#TNG_Pnehwlevelcigol
]0:3[EBC_P91V,61U,21U,9VBP.selbanEetyB/dnammoCyramirP etybdnadleifdnammocdexelpitluM epytnoitcasnartehtsevirdrotaitinieht,esahpsserddagniruD.dleifelbane atadgnirudselbaneetybehtsevirdrotaitiniehttahtretfA.snipesehtno levelcigoldilavaot]0:3[EBC_Psevird0017C7IP,eldisubgniruD.sesahp .detressasi#TNG_Pnehw
RAP_P51UBP.ytiraPyramirP dna,]0:3[EBC_P,]0:13[DA_PssorcanevesiytiraP dnadilavsidnatupninasiRAP_P.)s'1'forebmunnevena.e.i(RAP_P fonoitressaybdetacidni(esahpsserddaehtretfaelcycenoelbats tupninasiRAP_P,sesahpatadetirwroF.ytirapsserddarof)#EMARF_P ,esahpataddaerroF.detressasi#YDRI_Pretfakcolcenodilavsidna .detressasi#YDRT_PretfakcolcenodilavsidnatuptuonasiRAP_P gniruD.detats-3erasenilDAPehtretfaelcycenodetats-irtsiRAP_PlangiS si#TNG_PnehwlevelcigoldilavaotRAPPsevird0017C7IP,eldisub .detressa
#EMARF_P31WSTSP .)WOLevitcA(EMARFyramirP otnoitcasnartaforotaitiniehtybnevirD fonoitressa-edehT.sseccanafonoitaruddnagninnigebehtetacidni erofeB.rotaitiniehtybdetseuqeresahpatadlanifehtsetacidni#EMARF_P .elcycenorofetatsdetressa-edaotnevirdsiti,detats-3gnieb
3.2 Signals (Note: Signal name that ends with character ‘#’ is active LOW.)
3.2.1PrimaryBusInterfaceSignals

509/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
emaN#niPepyTnoitpircseD
#YDRI_P31VSTSP otytilibastietacidniotnoitcasnartaforotaitiniehtybnevirD.)WOLevitcA(YDRIyramirP tonsiti,esahpatadanidetressaecnO.edisyramirpehtnoesahpatadtnerrucetelpmoc detressa-edaotnevirdsiti,detats-3gnieberofeB.esahpatadfodnelitnudetressa-ed .elcycenorofetats
#YDRT_P31USTSP otytilibastietacidniotnoitcasnartafotegratehtybnevirD.)WOLevitcA(YDRTyramirP tonsiti,esahpatadanidetressaecnO.edisyramirpehtnoesahpatadtnerrucetelpmoc detressa-edaotnevirdsiti,detats-3gnieberofeB.esahpatadfodnelitnudetressa-ed .elcycenorofetats
#LESVED_P41YSTSP .)WOLevitcA(tceleSeciveDyramirP ecivedehttahtgnitacidnitegratehtybdetressA langissihtfonoitressaehtrofstiaw0017C7IP,retsamasA.noitcasnartehtgnitpeccasi erofeB.trobaretsamhtiwetanimret,esiwrehto;noitressa#EMARF_Pfoselcyc5nihtiw .elcycenorofetatsdetressa-edaotnevirdsiti,detats-3gnieb
#POTS_P41WSTSP .)WOLevitcA(POTSyramirP sitegratehttahtgnitacidnitegratehtybdetressA nevirdsiti,detats-3gnieberofeB.noitcasnarttnerrucehtpotsotrotaitiniehtgnitseuqer .elcycenorofetatsdetressa-edaot
#KCOL_P41VSTSP .)WOLevitcA(KCOLyramirP .etelpmocotsnoitcasnartelpitlumrofretsamybdetressA
LESDI_P01YIP.tceleSDIyramirP 0017C7IPotsseccanoitarugifnoc0epyTrofeniltcelespihcsadesU
.ecapsnoitarugifnoc
#RREP_P51YSTSP rorrEytiraPyramirP.)WOLevitcA( rofdetcetedsirorreytirapatadanehwdetressA -edaotnevirdsiti,detats-3gnieberofeB.ecafretniyramirpehtnodevieceratad .elcycenorofetatsdetressa
#RRES_P51WDOP .)WOLevitcA(rorrEmetsySyramirP aetacidniotecivedynaybWOLnevirdebnaC :nonipsihtsevird0017C7IP,noitidnocrorremetsys rorreytirapsserddA• subtegratnororreytirapatadetirwdetsoP• detressa#RRES_2Sro#RRES_1SyradnoceS• noitcasnartetirwdetsopgnirudtrobaretsaM• noitcasnartetirwdetsopgnirudtrobategraT• dedracsidnoitcasnartetirwdetsoP• dedracsidtseuqeretirwdeyaleD• dedracsidtseuqerdaerdeyaleD• tuoemitretsamnoitcasnartdeyaleD• .noitareporeporprofrotsiserpu-lluplanretxenaseriuqerlangissihT
#QER_P6WSTP .)WOLevitcA(tseuqeRyramirP stnawtitahtetacidniot0017C7IPybdetressasisihT ICP2tsaeltarofnipsihtstressa-ed0017C7IP.subyramirpehtnonoitcasnartatratsot .niagatignitressaerofebselcyckcolc
#TNG_P7UIP)WOLevitcA(tnarGyramirP .subyramirpehtsseccanac0017C7IP,detressanehW. otRAP_PdnaEBC_P,DA_Pevirdlliw0017C7IP,detressa#TNG_PdnaeldigniruD .slevelcigoldilav
#TESER_P5YIP.)WOLevitcA(TESERyramirP ebdluohsslangisICPlla,evitcasi#TESER_PnehW
.detats-3ylsuonorhcnysa
#HSULF_P5WIP.)WOLevitcA(HSULFOFIFyramirP )s(OFIFyramirplla,evitcasi#HSULF_PnehW citatsaotdellupebdluohslangissihT.)snoitcasnartyramirpllaetadilavni(deraelcera ".hgih"
NE66M_P81V– .esUerutuFrofdevreseR .dnuorgotdeitebtsuM
3.2.1PrimaryBusInterfaceSignals(continued)

609/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
emaN#niPepyTnoitpircseD
,]0:13[DA_1S
]0:13[DA_2S
,91C,02C,91B,02B ,71D,91D,02D,81C ,02F,71E,81E,91E ,91G,02G,71F,91F ,02M,81L,91L,02L ,91N,02N,71M,91M ,02R,71P,71N,81N 91T,02T,81R,91R ,1G,4H,3H,2H,1H,4J ,1E,4F,3F,2F,4G,3G ,5B,5C,1B,1C,1D,4E ,7B,7C,6A,6B,6C,6D ,9A,9B,9C,9D,8C,8D 01C,01D BP .ataD/sserddAyradnoceS .subataddnasserddadexelpitluM .noitressa#EMARF_2Sro#EMARF_1SybdetacidnisisserddA si#YDRI_2Sro#YDRI_1SnehwdilavdnaelbatssiatadetirW ro#YDRT_1Snehwdilavdnaelbatssiataddaerdnadetressa segdekcolcgnisirnoderrefsnartsiataD.detressasi#YDRT_2S dna#YDRI_2Sro#YDRT_1Sdna#YDRI_1Shtobnehw sevird0017C7IP,eldisubgniruD.detressaera#YDRT_2S ro#TNG_1SehtnehwlevelcigoldilavaotDA_2SroDA_1S .ylevitcepserdetressasi#TNG_2S
,]0:3[EBC_1S ]0:3[EBC_2S 02P,71K,81G,02E 7A,4A,1A,1F BP .selbanEetyB/dnammoCyradnoceS dnammocdexelpitluM rotaitinieht,esahpsserddaehtgniruD.dleifelbaneetybdnadleif rotaitiniehttahtretfA.snipesehtnoepytnoitcasnartehtsevird ,eldisubgniruD.sesahpatadgnirudselbaneetybehtsevird cigoldilavaot]0:3[EBC_2Sro]0:3[EBC_1Ssevird0017C7IP .detressasitnarglanretniehtnehwlevel
,RAP_1S RAP_2S ,81K4B BP .ytiraPyradnoceS ,]0:13[DA_1SssorcanevesiytiraP dna,]0:3[EBC_2S,]0:13[DA_2SroRAP_1Sdna,]0:3[EBC_1S nasiRAP_2SroRAP_1S.)s'1'forebmunnevena.e.i(RAP_2S esahpsserddaehtretfaelcycenoelbatsdnadilavsidnatupni rof)#EMARF_2Sro#EMARF_1Sfonoitressaybdetacidni( nasiRAP_2SroRAP_1S,sesahpatadetirwroF.ytirapsserdda si#YDRI_2Sro#YDRI_1Sretfakcolcenodilavsidnatupni tuptuonasiRAP_2SroRAP_1S,esahpataddaerroF.detressa .detressasi#YDRT_2Sro#YDRT_1Sretfakcolcenodilavsidna DA_1Sehtretfaelcycenodetats-3siRAP_2SroRAP_1SlangiS sevird0017C7IP,eldisubgniruD.detats-irterasenilDA_2Sro sitnarglanretniehtnehwlevelcigoldilavaotRAP_2SroRAP_1S .detressa
,#EMARF_1S #EMARF_2S ,02H2D STSP .)WOLevitcA(EMARFyradnoceS aforotaitiniehtybnevirD .sseccanafonoitaruddnagninnigebehtetacidniotnoitcasnart lanifehtsetacidni#EMARF_2Sro#EMARF_1Sfonoitressa-eD siti,detats-3gnieberofeB.rotaitiniybdetseuqeresahpatad .elcycenorofetatsdetressa-edaotnevird
,#YDRI_1S #YDRI_2S ,91H2B STSP .)WOLevitcA(YDRIyradnoceS aforotaitiniehtybnevirD atadtnerrucehtetelpmocotytilibastietacidniotnoitcasnart siti,esahpatadanidetressaecnO.edisyramirpehtnoesahp ,detats-3gnieberofeB.esahpatadehtfodnelitnudetressa-edton .elcycenorofetatsdetressa-edaotnevirdsiti
,#YDRT_1S #YDRT_2S ,81H2A STSP .)WOLevitcA(YDRTyradnoceS afotegratehtybnevirD atadtnerrucehtetelpmocotytilibastietacidniotnoitcasnart siti,esahpatadanidetressaecnO.edisyramirpehtnoesahp ,detats-3gnieberofeB.esahpatadehtfodnelitnudetressa-edton .elcycenorofetatsdetressa-edaotnevirdsiti
,#LESVED_1S #LESVED_2S ,02J 3D STSP .)WOLevitcA(tceleSeciveDyradnoceS tegratehtybdetressA asA.noitcasnartehtgnitpeccasiecivedehttahtgnitacidni 5nihtiwlangissihtfonoitressaehtrofstiaw0017C7IP,retsam ,esiwrehto;noitressa#EMARF_2Sro#EMARF_1Sfoselcyc aotnevirdsiti,detats-3gnieberofeB.trobaretsamhtiwetanimret .elcycenorofetatsdetressa-ed
3.2.2SecondaryBusInterface Signals

709/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
emaN#niPepyTnoitpircseD
,#POTS_1S #POTS_2S ,91J 3C STSP .)WOLevitcA(POTSyradnoceS ehttahtgnitacidnitegratehtybdetressA gnieberofeB.noitcasnarttnerrucehtpotsotrotaitiniehtgnitseuqersitegrat .elcycenorofetatsdetressa-edaotnevirdsiti,detats-3
,#KCOL_1S #KCOL_2S ,81J3B STSP .)WOLevitcA(KCOLyradnoceS snoitcasnartelpitlumrofretsamybdetressA
.etelpmocot
,#RREP_1S #RREP_2S ,71J 4D STSP .)WOLevitcA(rorrEytiraPyradnoceS sirorreytirapatadanehwdetressA ti,detats-3gnieberofeB.ecafretniyradnocesehtnodevieceratadrofdetceted .elcycenorofetatsdetressa-edaotnevirdsi
,#RRES_1S #RRES_2S ,02K4C IP .)WOLevitcA(rorrEmetsySyradnoceS otecivedynaybWOLnevirdebnaC
.noitidnocrorremetsysaetacidni
,]0:7[#QER_1S
]0:7[#QER_2S
,21A,11B ,31C,31D ,61A,51C 71B,71C ,2P,3R,2T ,1M,2M,1P 3K,1K UIP .)WOLevitcA(tseuqeRyradnoceS otecivedlanretxenaybdetressasisihT situpniehT.subyradnoceSehtnonoitcasnartatratsotstnawtitahtetacidni .DDVotrotsiserahguorhtpudellupyllanretxe
,]0:7[#TNG_1S
]0:7[#TNG_2S
,21B,11C ,41A,31B ,61B,41D 81B,61D ,1R,4P,1U ,4L,3M,4N 2K,1L OP .)WOLevitcA(tnarGyradnoceS ehtsseccaotnipsihtstressa0017C7IP selcyckcolcICP2tsaeltarofnipsihtstressa-ed0017C7IP.subyradnoces ,detressa#TNG_2Sro#TNG_1SdnaeldigniruD.niagatignitressaerofeb dnaEBC_2S,DA_2SroRAP_1SdnaEBC_1S,DA_1Sevirdlliw0017C7IP .slevelcigoldilavotRAP_2S
,#TESER_1S #TESER_2S ,01B4T OP .)WOLevitcA(TESERyradnoceS gniwollofehtfoynanehwdetressA
:temerasnoitidnoc .detressasi#TESER_PlangiS.1 noitarugifnocniretsigerlortnocegdirbnitibteseryradnoceS.2 .tessiecaps nevirderasorezdnadetats-3eraslangislortnoclla,detressanehW .RAP_2Sdna,EBC_2S,DA_2SroRAP_1Sdna,EBC_1S,DA_1Sno
,NE_1S NE_2S ,3W4W UIP .)HGIHevitcA(elbanEyradnoceS ,evitcanisiNE_2SroNE_1SnehW .detats-3ylsuonorhcnysaeblliwsub2Sro1SICPyradnoces
NE66M_S7D– .esUerutuFrofdevreseR .dnuorgotdeitebtsuM
#NFC_S2YUIC .niPlortnoCnoitcnuFlartneCsuByradnoceS selbaneti,WOLdeitnehW .desuebtsumretibralanretxena,HGIHdeitnehW.retibralanretnieht ,tupnitnargsubyradnocesehtebotderugifnocersi#0QER_2Sro#0QER_1S tseuqersubyradnocesehtebotderugifnocersi#0TNG_2Sro#0TNG_1Sdna .tuptuo
3.2.2SecondaryBusInterfaceSignals(continued)

809/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
emaN#niPepyTnoitpircseD
KLC_P6VIPtupnIkcolCyramirP .ecafretniyramirpnonoitcasnartllarofgnimitsedivorP.
TUOKLC_S ]0:51[ ,3P,1T,3T ,2L,3L,4M,3N ,21C,11A,1J ,41B,31A ,61C,51B 91A,81A STP .tuptuOkcolCyradnoceS htiwsuonorhcnysesahpskcolcyradnocessedivorP
.KLC_Peht
3.2.3 Clock Signals
emaN#niPepyTnoitpircseD
SSAPYB4Y– .esUerutuFrofdevreseR .HGIHdeitebtsuM
MT_LLP3Y– .esUerutuFrofdevreseR .WOLdeitebtsuM
NIKLC_S5VIP.tupnIkcolCtseTyradnoceS oslatI.edomlamronniWOLotdeitebdluohstI dna#MT_NACShtobfisesubyradnocesehtroftupnikcolcyradnocesaebyam ."1"cigolotdetcennoceraNE_NACS
#MT_NACS4VIC.)WOLevitcA(elbaneedoMtseTnacs-lluF eht,evitcasi#MT_NACSnehW dnastupninacsehT.KLC_PsikcolcnacsehT.delbaneeblliwsniahcnacsevlewt :swollofsaerastuptuo ,]2[QER_1S,]3[QER_1S,]4[QER_1S,]5[QER_1S,]6[QER_1S,]7[QER_1S dna]2[QER_2S,]3[QER_2S,]4[QER_2S,]5[QER_2S,]6[QER_2S,]7[QER_2S ,]2[TNG_1S,]3[TNG_1S,]4[TNG_1S,]5[TNG_1S,]6[TNG_1S,]7[TNG_1S ]2[TNG_2S,]3[TNG_2S,]4[TNG_2S,]5[TNG_2S,]6[TNG_2S,]7[TNG_2S ylevitcepser
NE_NACS5UUIC .lortnoCelbanEnacs-lluF noitarepotfihsnisinacs-lluf,WOLsiNE_NACSnehW noitarepolellarapnisinacs-lluf,HGIHsiNE_NACSnehW.evitcasi#MT_NACSfi fI.edomlamronniWOLdeitebdluohsNE_NACS.evitcasi#MT_NACSfi kcolcehtsiNIKLC_S,"1"cigolotdetcennoceraNE_NACSdna#MT_NACS dna"1"cigolotdetcennocsi#MT_NACSfI.kcolcyradnoceslanretniehtrofecruos lanretniehtrofecruoskcolcehtsiKLC_P,"0"cigolotdetcennocsiNE_NACS .kcolcyradnoces :etoN .LLPpihc-noehtroflangisteserehtsiNE_NACS,pu-rewopgniruD
1OPMC6U– .esUerutuFrofdevreseR
devreseR4RdevreseR
3.2.4 Miscellaneous Signals
3.2.5 JTAGBoundaryScanSignals
emaN#niPepyTnoitpircseD
KCT2VUIC .kcolCtseT gnirud0017C7IPehtfotuodnaotniataddnanoitamrofnietatskcolcotdesU.nacsyradnuob
SMT1WUIC tceleSedoMtseT .rellortnoctroPsseccAtseTehtfoetatsehtlortnocotdesU.
ODT3VOTC .tuptuOataDtseT atadtfihsot)KCThtiwnoitcnujnocni(desusitiHGIHsiNENACSnehW .maertstiblairesani)PAT(troPsseccAtseTehtfotuo
IDT2WUIC .tupnIataDtseT atadtfihsot)KCThtiwnoitcnujnocni(desusitiHGIHsiNENACSnehW .maertstiblairesa)PAT(troPsseccAtseTehtotnisnoitcurtsnidna
#TSRT3UUIC .teseRtseT naotnirellortnoc)PAT(troPsseccAtseTehtteserotlangisWOLevitcA.etatsdezilaitini

909/18/00 Rev1.1
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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
emaN#niPepyTnoitpircseD
DDV,91P,2N,71L,3J,81F,2E,51D,11D,5D,41C,8B 02W,51V,7V,1V,01U rewoPlatigiDV3.3+
SSV,81D,21D,2C,02A,71A,51A,01A,8A,5A,3A ,2R,81P,1N,81M,91K,4K,2J,71H,71G,2G,3E 31Y6Y11W71V71U,41U,9U,2U,81T dnuorGlatigiD
CCVA1YLLProfV3.3golanA
DNGA4ULLProfdnuorGgolanA
3.2.6 PowerandGround
3.3 PI7C7100 PBGA Pin List
.oNniPemaNepyT.oNniPemaNepyT
1A]2[EBC_2SBP2A#YDRT_2SSTSP
3ASSV– 4A]1[EBC_2SBP
5ASSV– 6A]01[DA_2SBP
7A]0[EBC_2SBP8ASSV–
9A]2[DA_2SBP01ASSV–
11A]7[TUOKLC_SSTP21A]6[#QER_1SUIP
31A]5[TUOKLC_SSTP41A]6[#TNG_1SOP
51ASSV– 61A]2[#QER_1SUIP
71ASSV– 81A]1[TUOKLC_SSTP
91A]0[TUOKLC_SSTP02ASSV–
1B]61[DA_2SBP2B#YDRI_2SSTSP
3B#KCOL_2SSTSP4BRAP_2SBP
5B]41[DA_2SBP6B]11[DA_2SBP
7B]8[DA_2SBP8BDDV–
9B]3[DA_2SBP01B#TESER_1SOP
11B]7[#QER_1SUIP21B]6[#TNG_1SOP
31B]7[#TNG_1SOP41B]4[TUOKLC_SSTP
51B]3[TUOKLC_SSTP61B]2[#TNG_1SOP
71B]0[#QER_1SUIP81B]0[#TNG_1SOP
91B]03[DA_1SBP02B]13[DA_1SBP
1C]71[DA_2SBP2CSSV–
3C#POTS_2SSTSP4C#RES_2SIP
5C]51[DA_2SBP6C]21[DA_2SBP
7C]9[DA_2SBP8C]6[DA_2SBP
9C]4[DA_2SBP01C]0[DA_2SBP
11C]7[#TNG_1SOP21C]6[TUOKLC_SSTP
31C]4[#QER_1SUIP41CDDV–
51C]3[#QER_1SUIP61C]2[TUOKLC_SSTP

10 09/18/00 Rev1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
.oNniPemaNepyT.oNniPemaNepyT
71C]1[#QER_1SUIP81C]72[DA_1SBP
91C]82[DA_1SBP02C]92[DA_1SBP
1D]81[DA_2SBP2D#EMARF_2SSTSP
3D#LESVED_2SSTSP4D#RREP_2SSTSP
5DDDV– 6D]31[DA_2SBP
7DNE66M_S– 8D]7[DA_2SBP
9D]5[DA_2SBP01D]1[DA_2SBP
11DDDV– 21DSSV–
31D]5[#QER_1SUIP41D]3[#TNG_1SOP
51DDDV– 61D]1[#TNG_1SOP
71D]42[DA_1SBP81DSSV–
91D]52[DA_1SBP02D]62[DA_1SBP
1E]02[DA_2SBP2EDDV–
3ESSV– 4E]91[DA_2SBP
71E]12[DA_1SBP81E]22[DA_1SBP
91E]32[DA_1SBP02E]3[EBC_1SBP
1F]3[EBC_2SBP2F]32[DA_2SBP
3F]22[DA_2SBP4F]12[DA_2SBP
71F]81[DA_1SBP81FDDV–
91F]91[DA_1SBP02F]02[DA_1SBP
1G]62[DA_2SBP2GSSV–
3G]52[DA_2SBP4G]42[DA_2SBP
71GSSV– 81G]2[EBC_1SBP
91G]61[DA_1SBP02G]71[DA_1SBP
1H]03[DA_2SBP2H]92[DA_2SBP
3H]82[DA_2SBP4H]72[DA_2SBP
71HSSV– 81H#YDRT_1SSTSP
91H#YDRI_1SSTSP02H#EMARF_1SSTSP
1J]8[TUOKLC_SSTP2JSSV–
3JDDV– 4J]13[DA_2SBP
71J#RREP_1SSTSP81J#KCOL_1SSTSP
91J#POTS_1SSTSP02J#LESVED_1SSTSP
3.3 PI7C7100 PBGA Pin List (continued)

11 09/18/00 Rev1.1
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
.oNniPemaNepyT.oNniPemaNepyT
1K]1[#QER_2SUIP2K]0[#TNG_2SOP
3K]0[#QER_2SUIP4KSSV–
71K]1[EBC_1SBP81KRAP_1SBP
91KSSV– 02K#RRES_1SIP
1L]1[#TNG_2SOP2L]9[TUOKLC_SSTP
3L]01[TUOKLC_SSTP4L]2[#TNG_2SOP
71LDDV– 81L]31[DA_1SBP
91L]41[DA_1SBP02L]51[DA_1SBP
1M]2[#QER_2SUIP2M]3[#QER_2SUIP
3M]3[#TNG_2SOP4M]11[TUOKLC_SSTP
71M]01[DA_1SBP81MSSV–
91M]11[DA_1SBP02M]21[DA_1SBP
1NSSV– 2NDDV–
3N]21[TUOKLC_SSTP4N]4[#TNG_2SOP
71N]6[DA_1SBP81N]7[DA_1SBP
91N]8[DA_1SBP02N]9[DA_1SBP
1P]4[#QER_2SUIP2P]5[#QER_2SUIP
3P]31[TUOKLC_SSTP4P]6[#TNG_2SOP
71P]5[DA_1SBP81PSSV–
91PDDV– 02P]0[EBC_1SBP
1R]5[#TNG_2SOP2RSSV–
3R]6[#QER_2SUIP4RdevreseR–
71R]0[DA_PBP81R]2[DA_1SBP
91R]3[DA_1SBP02R]4[DA_1SBP
1T]41[TUOKLC_SSTP2T]7[#QER_2SUIP
3T]51[TUOKLC_SSTP4T#TESER_2SOP
71T]1[DA_PBP81TSSV–
91T]0[DA_1SBP02T]1[DA_1SBP
1U]7[#TNG_2SOP2USSV–
3U#TSRTUIC4UDNGA–
5UNE_NACSUIC6U1OPMC–
7U#TNG_PIP8U]62[DA_PBP
3.3 PI7C7100 PBGA Pin List (continued)

12 09/18/00 Rev1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
.oNniPemaNepyT.oNniPemaNepyT
9USSV– 01UDDV–
11U]91[DA_PBP21U]2[EBC_P
31U#YDRT_PBP41USSV–
51URAP_PBP61U]1[EBC_PBP
71USSV– 81U]01[DA_PBP
91U]7[DA_PBP02U]4[DA_PBP
1VDDV– 2VKCTUIC
3VODTOTC4V#MT_NACSIC
5VNIKLC_SIP6VKLC_PIP
7VDDV– 8V]72[DA_PBP
9V]3[EBC_PBP01V]22[DA_PBP
11V]02[DA_PBP21V]61[DA_PBP
31V#YDRI_PBP41V#KCOL_PSTSP
51VDDV– 61V]51[DA_PBP
71VSSV– 81VNE66M_P–
91V]0[EBC_PBP02V]3[DA_PBP
1WSMTUIC2WIDTUIC
3WNE_1SUIP4WNE_2SUIP
5W#HSULF_PIP6W#QER_PSTP
7W]03[DA_PBP8W]82[DA_PBP
9W]42[DA_PBP01W]32[DA_PBP
11WSSV– 21W]71[DA_PBP
31W#EMARF_PBP41W#POTS_PSTSP
51W#RRES_PDOP61W]41[DA_PBP
71W]21[DA_PBP81W]9[DA_PBP
91W]6[DA_PBP02WDDV–
1YCCVA– 2Y#NFC_SUIC
3YMT_LLP– 4YSSAPYB–
5Y#TESER_PIP6YSSV–
7Y]13[DA_PBP8Y]92[DA_PBP
9Y]52[DA_PBP01YLESDI_PIP
11Y]12[DA_PBP21Y]81[DA_PBP
31YSSV– 41Y#LESVED_PSTSP
51Y#RREP_PSTSP61Y]31[DA_PBP
71Y]11[DA_PBP81Y]8[DA_PBP
91Y]5[DA_PBP02Y]2[DA_PBP
3.3 PI7C7100 PBGA Pin List (continued)