Pericom PI7C7100 User manual

09/18/00 Rev1.1
PI7C7100
3-Port
PCI Bridge
The Complete Interface Solution
2380 Bering Drive, San Jose, California 95131
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: [phone], E-mail: [email protected]
Internet: http://www.pericom.com
© 2000 Pericom Semiconductor Corporation
Pericom Semiconductor Corporation
Rev 1.1
查询PI7C7100供应商 捷多邦，专业PCB打样工厂，24小时加急出货

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
LIFESUPPORTPOLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or
systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an
officer of PSC.
1.Life support devices or systems are devices or systems which:
a) are intended for surgical implant into the body or
b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expectedtocausethefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectiveness.PericomSemiconductor
Corporationreserves therighttomakechanges toits productsorspecificationsatany time,without notice,inordertoimprove
design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility
foruse ofanycircuitrydescribedotherthanthecircuitryembodied ina PericomSemiconductor product.TheCompanymakes
no representations that circuitry described herein is free from patent infringement or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom
Semiconductor Corporation.
All other trademarks are of their respective companies.

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
1. Introduction/ProductFeatures ...............................................................................................................................1
2. PI7C7100BlockDiagram ......................................................................................................................................3
3. SignalDefinitions ...................................................................................................................................................4
3.1 Signal Types ............................................................................................................................................................4
3.2 Signals ......................................................................................................................................................................4
3.2.1 PrimaryBusInterfaceSignals ..................................................................................................................................4
3.2.2 Secondary Bus Interface Signals .............................................................................................................................6
3.2.3 ClockSignals............................................................................................................................................................8
3.2.4 Miscellaneous Signals .............................................................................................................................................8
3.2.5 JTAG Boundary Scan Signals..................................................................................................................................9
3.2.6 Power and Ground....................................................................................................................................................9
3.3 PI7C7100PBGAPinListing .....................................................................................................................................9
4. PCIBusOperation ................................................................................................................................................ 13
4.1 Types of Transactions ........................................................................................................................................... 13
4.2 Single Address Phase ............................................................................................................................................ 14
4.3 DeviceSelect(DEVSEL#)Generation .................................................................................................................... 14
4.4 Data Phase ............................................................................................................................................................. 14
4.5 Write Transactions ................................................................................................................................................ 14
4.5.1 Posted Write Transactions .................................................................................................................................... 14
4.5.2 Memory Write and Invalidate Transactions.......................................................................................................... 15
4.5.3 Delayed Write Transactions .................................................................................................................................. 15
4.5.4 Write Transaction Address Boundaries ................................................................................................................ 16
4.5.5 Buffering Multiple Write Transactions .................................................................................................................. 16
4.5.6 Fast Back-to-Back Write Transactions .................................................................................................................. 16
4.6 Read Transactions ................................................................................................................................................. 17
4.6.1 Prefetchable Read Transactions ............................................................................................................................ 17
4.6.2 Non-prefetchable Read Transactions .................................................................................................................... 17
4.6.3 Read Pre-fetch Address Boundaries...................................................................................................................... 17
4.6.4 Delayed Read Requests ......................................................................................................................................... 18
4.6.5 DelayedReadCompletionwith Target .................................................................................................................. 18
4.6.6 Delayed Read Completion on Initiator Bus ........................................................................................................... 18
4.7 Configuration Transactions ................................................................................................................................... 19
4.7.1 Type 0 Access to PI7C7100 ................................................................................................................................... 19
4.7.2 Type 1 to Type 0 Conversion ................................................................................................................................ 20
4.7.3 Type 1 to Type 1 Forwarding ................................................................................................................................ 21
4.7.4 SpecialCycles ........................................................................................................................................................ 22
4.8 TransactionTermination ........................................................................................................................................ 22
4.8.1 MasterTerminationInitiatedbyPI7C7100 ............................................................................................................ 23
4.8.2 MasterAbortReceived byPI7C7100 ..................................................................................................................... 23
4.8.3 TargetTerminationReceivedbyPI7C7100 ............................................................................................................ 24
4.8.3.1 Delayed Write Target Termination Response ....................................................................................................... 24
4.8.3.2 Posted Write Target Termination Response ......................................................................................................... 24
4.8.3.3 Delayed Read Target Termination Response ........................................................................................................ 25
4.8.4 TargetTerminationInitiatedbyPI7C7100 ............................................................................................................. 26
4.8.4.1 Target Retry ........................................................................................................................................................... 26
4.8.4.2 Target Disconnect.................................................................................................................................................. 27
Table of Contents

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
4.8.4.3 Target Abort .......................................................................................................................................................... 27
4.9 Concurrent Mode Operation.................................................................................................................................. 27
5. AddressDecoding.................................................................................................................................................. 28
5.1 Address Ranges..................................................................................................................................................... 28
5.2 I/O Address Decoding ........................................................................................................................................... 28
5.2.1 I/O Base and Limit Address Registers ................................................................................................................... 28
5.2.2 ISA Mode............................................................................................................................................................... 29
5.3 Memory Address Decoding................................................................................................................................... 29
5.3.1 Memory-Mapped I/O Base and Limit Address Registers...................................................................................... 30
5.3.2 Prefetchable Memory Base and Limit Address Registers...................................................................................... 30
5.4 VGASupport.......................................................................................................................................................... 31
5.4.1 VGAMode ............................................................................................................................................................. 31
5.4.2 VGA Snoop Mode.................................................................................................................................................. 31
6. TransactionOrdering ........................................................................................................................................... 32
6.1 Transactions Governed by Ordering Rules ........................................................................................................... 32
6.2 GeneralOrderingGuidelines .................................................................................................................................. 32
6.3 OrderingRules ....................................................................................................................................................... 33
6.4 DataSynchronization............................................................................................................................................. 34
7. ErrorHandling ...................................................................................................................................................... 35
7.1 Address Parity Errors............................................................................................................................................. 35
7.2 DataParityErrors ................................................................................................................................................... 35
7.2.1 Configuration Write Transactions to Configuration Space................................................................................... 35
7.2.2 Read Transactions ................................................................................................................................................. 36
7.2.3 Delayed Write Transactions .................................................................................................................................. 36
7.2.4 Posted Write Transactions .................................................................................................................................... 38
7.3 DataParityErrorReportingSummary .................................................................................................................... 39
7.4 SystemError(SERR#)Reporting ........................................................................................................................... 45
8. ExclusiveAccess ................................................................................................................................................... 46
8.1 ConcurrentLocks................................................................................................................................................... 46
8.2 AcquiringExclusiveAccessacrossPI7C7100....................................................................................................... 46
8.3 EndingExclusive Access ....................................................................................................................................... 47
9. PCIBusArbitration .............................................................................................................................................. 48
9.1 PrimaryPCIBusArbitration................................................................................................................................... 48
9.2 Secondary PCI Bus Arbitration ............................................................................................................................. 48
9.2.1 Secondary Bus Arbitration Using the Internal Arbiter.......................................................................................... 48
9.2.2 Secondary Bus Arbitration Using an External Arbiter........................................................................................... 49
9.2.3 BusParking ............................................................................................................................................................ 49
10. Clocks .................................................................................................................................................................... 50
10.1 PrimaryClockInputs .............................................................................................................................................. 50
10.2 Secondary Clock Outputs ...................................................................................................................................... 50
11. Reset ...................................................................................................................................................................... 51
11.1 PrimaryInterfaceReset .......................................................................................................................................... 51
11.2 Secondary Interface Reset ..................................................................................................................................... 51
11.3 Chip Reset .............................................................................................................................................................. 51
12. SupportedCommands ............................................................................................................................................ 52
12.1 PrimaryInterface .................................................................................................................................................... 52
12.2 Secondary Interface ............................................................................................................................................... 54
13. ConfigurationRegisters ....................................................................................................................................... 55

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
13.1 ConfigRegister1.................................................................................................................................................... 55
13.2 ConfigRegister2.................................................................................................................................................... 56
13.2.1 ConfigRegister 1or2:Vendor IDRegister(read only,bit15-0;offset00h) .......................................................... 57
13.2.2 ConfigRegister1:DeviceIDRegister (readonly,bit 31-16;offset00h) ............................................................... 57
13.2.3 ConfigRegister2:DeviceIDRegister (readonly,bit 31-16;offset00h) ............................................................... 57
13.2.4 ConfigRegister1:CommandRegister(bit15-0;offset04h) .................................................................................. 57
13.2.5 ConfigRegister2:CommandRegister(bit15-0;offset04h) .................................................................................. 58
13.2.6 ConfigRegister 1 or2: StatusRegister(for primarybus, bit31-16;offset 04h)..................................................... 59
13.2.7 ConfigRegister1 or2: Revision IDRegister (read only,bit 7-0;offset08h) ......................................................... 60
13.2.8 Config Register 1 or 2: Class Code Register (read only, bit 31-8; offset 08h) ........................................................ 60
13.2.9 ConfigRegister1or2:CacheLineSizeRegister(read/write,bit7-0;offset0Ch) ................................................. 60
13.2.10 ConfigRegister1:PrimaryLatencyTimerRegister(read/write,bit15-8;offset0Ch)............................................60
13.2.11 ConfigRegister2:PrimaryLatencyTimerRegister(read/write,bit15-8;offset0Ch)............................................60
13.2.12 ConfigRegister 1: HeaderType Register(read only,bit23-16; offset0Ch).......................................................... 60
13.2.13 ConfigRegister 2: HeaderType Register(read only,bit23-16; offset0Ch).......................................................... 60
13.2.14 ConfigRegister1:PrimaryBusNumberRegister(read/write,bit7-0;offset18h) ................................................. 60
13.2.15 ConfigRegister2:PrimaryBusNumberRegister(read/write,bit7-0;offset18h) ................................................. 60
13.2.16 ConfigRegister 1or 2:Secondary BusNumberRegister (read/write,bit 15-8;offset 18h) ................................... 60
13.2.17 ConfigRegister 1or2: SubordinateBus NumberRegister(read/write, bit23-16;offset 18h)............................... 60
13.2.18 ConfigRegister1or2:SecondaryLatencyTimer(read/write,bit31-24;offset18h) ............................................ 60
13.2.19 ConfigRegister 1or2:I/OBase Register(read/write, bit7-0;offset 1Ch) ............................................................ 60
13.2.20 ConfigRegister1or2:I/OLimitRegister(read/write,bit15-8;offset1Ch)........................................................... 60
13.2.21 Config Register 1 or 2: Secondary Status Register (bit 31-16; offset 1Ch) ............................................................ 61
13.2.22 ConfigRegister1 or2:Memory BaseRegister(read/write,bit 15-0;offset20h) ................................................... 62
13.2.23 ConfigRegister1or2:MemoryLimitRegister(read/write,bit31:16;offset20h) ................................................. 62
13.2.24 ConfigRegister1 or2: PrefetchableMemory BaseRegister(read/write,bit 15-0;offset24h)............................... 62
13.2.25 ConfigRegister1or2:PrefetchableMemoryLimitRegister(read/write,bit31-16;offset24h) ............................ 62
13.2.26 Config Register1 or2: I/O BaseAddress Upper16 Bits Register(read/write, bit15-0; offset 30h)...................... 62
13.2.27 ConfigRegister 1or 2:I/OLimit AddressUpper 16BitsRegister (read/write,bit 31-16;offset30h) .................... 62
13.2.28 ConfigRegister 1or2: SubsystemVendorID(read/write,bit 15-0;offset34h) .................................................... 62
13.2.29 ConfigRegister 1or2: SubsystemID(read/write, bit31-16;offset34h)............................................................... 62
13.2.30 ConfigRegister 1 or2: Interrupt PinRegister (readonly, bit 15-8;offset 3Ch) ..................................................... 62
13.2.31 ConfigRegister1or2: BridgeControlRegister (bit31-16;offset 3Ch) ................................................................. 63
13.2.32 ConfigRegister1or2:Diagnostic/Chip ControlRegister(bit 15-0;offset40h).................................................... 64
13.2.33 ConfigRegister1 or2:ArbiterControl Register(bit31-16;offset40h)................................................................. 64
13.2.34 ConfigRegister1:PrimaryPrefetchable MemoryBaseRegister(Read/Write,bit15-0;offset44h) ..................... 65
13.2.35 ConfigRegister2:PrimaryPrefetchable MemoryBaseRegister(Read/Write,bit15-0;offset44h) ..................... 65
13.2.36 ConfigRegister1:PrimaryPrefetchableMemoryLimitRegister(Read/Write,bit31-16;offset44h).................... 65
13.2.37 ConfigRegister2:PrimaryPrefetchableMemoryLimitRegister(Read/Write,bit31-16;offset44h).................... 65
13.2.38 ConfigRegister1or2:P_SERR#EventDisableRegister(bit 7-0;offset64h) ...................................................... 65
13.2.39 ConfigRegister1: SecondaryClockControlRegister(bit15-0;offset68h).......................................................... 66
13.2.40 ConfigRegister2: SecondaryClockControlRegister(bit15-0;offset68h).......................................................... 66
13.2.41 Config Register1 or2: Non-PostedMemory BaseRegister (read/write,bit 15-0;offset 70h) .............................. 67
13.2.42 ConfigRegister1or2:Non-Posted MemoryLimitRegister(read/write,bit31-16;offset70h)............................. 67
13.2.43 ConfigRegister 1:PortOption Register(bit15-0; offset74h) ............................................................................... 67
13.2.44 ConfigRegister 2:PortOption Register(bit15-0; offset74h) ............................................................................... 68
13.2.45 Config Register1 or2: MasterTimeout CounterRegister (read/write,bit 31-16;offset 74h)................................ 69
13.2.46 ConfigRegister1 or2:Retry CounterRegister(read/write,bit31-0;offset78h) .................................................. 69
13.2.47 ConfigRegister1or2:SamplingTimerRegister(read/write,bit31-0;offset7Ch) ................................................ 69
13.2.48 Config Register1 or2: SuccessfulI/O Read CountRegister (read/write,bit 31-0;offset 80h) ............................. 69

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
13.2.49 Config Register1 or2: SuccessfulI/O Write CountRegister (read/write,bit 31-0;offset 84h)............................. 69
13.2.50 Config Register1 or2: SuccessfulMemory ReadCount Register(read/write, bit 31-0;offset 88h) ..................... 69
13.2.51 Config Register1 or2: SuccessfulMemory WriteCount Register(read/write, bit31-0; offset8Ch).................... 69
13.2.52 ConfigRegister1: PrimarySuccessful I/OReadCountRegister (read/write,bit 31-0;offset 90h) ....................... 69
13.2.53 ConfigRegister1: PrimarySuccessful I/OWriteCountRegister (read/write,bit 31-0;offset 94h)....................... 69
13.2.54 ConfigRegister1: PrimarySuccessful MemoryRead CountRegister (read/write,bit 31-0;offset98h) ............... 69
13.2.55 ConfigRegister1:Primary SuccessfulMemory WriteCount Register(read/write, bit31-0; offset9Ch).............. 69
14. BridgeBehavior .................................................................................................................................................... 70
14.1 Bridge Actions for Various Cycle Types ............................................................................................................... 70
14.2 Transaction Ordering ............................................................................................................................................. 70
14.3 Abnormal Termination(InitiatedbyBridge Master) ............................................................................................. 71
14.3.1 Master Abort ......................................................................................................................................................... 71
14.3.2 Parityand ErrorReporting ..................................................................................................................................... 71
14.3.3 ReportingParityErrors........................................................................................................................................... 71
14.3.4 SecondaryIDSELmapping .................................................................................................................................... 71
15. IEEE1149.1CompatibleJTAGController ........................................................................................................... 72
15.1 Boundary Scan Architecture ................................................................................................................................. 72
15.1.1 TAP Pins ................................................................................................................................................................ 72
15.1.2 Instruction Register ............................................................................................................................................... 72
15.2 Boundary Scan Instruction Set .............................................................................................................................. 73
15.3 TAP Test Data Registers ....................................................................................................................................... 74
15.4 Bypass Register ..................................................................................................................................................... 74
15.5 Boundary-Scan Register......................................................................................................................................... 74
15.6 TAP Controller ....................................................................................................................................................... 74
16. ElectricalandTimingSpecifications.................................................................................................................... 79
16.1 MaximumRatings ................................................................................................................................................... 79
16.2 3.3VDCSpecifications ........................................................................................................................................... 79
16.3 3.3VACSpecifications........................................................................................................................................... 80
16.4 Primary and Secondary buses at 33 MHz clock timing .......................................................................................... 80
16.5 PowerConsumption ............................................................................................................................................... 80
17. 256-PinPBGAPackage........................................................................................................................................... 81
17.1 PartNumberOrderingInformation ........................................................................................................................ 81

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
List of Figures
1-1. PI7C7100ontheSystemBoard....................................................................................................................................2
1-2. PI7C7100inRedundantApplications ..........................................................................................................................2
1-3. PI7C7100onNetworkSwitchingHub ..........................................................................................................................2
2-1. PI7C7100BlockDiagram ..............................................................................................................................................3
9-1. SecondaryArbiterExample ....................................................................................................................................... 48
15-1. Test Access Port Block Diagram ............................................................................................................................... 72
16-1. PCISignalTimingMeasurementConditions ............................................................................................................ 80
17-1. 256-PinPBGAPackageDrawing................................................................................................................................ 81
List of Tables
4-1. PCITransaction ......................................................................................................................................................... 13
4-2. Write Transaction Forwarding .................................................................................................................................. 14
4-3. Write Transaction Disconnect Address Boundaries ................................................................................................ 16
4-4. Read Pre-fetch Address Boundaries ......................................................................................................................... 17
4-5. Read Transaction Pre-fetching .................................................................................................................................. 18
4-6. DeviceNumbertoIDSELS1_ADorS2_ADPinMapping ....................................................................................... 21
4-7. Delayed Write Target Termination Response ........................................................................................................... 24
4-8. Responses to Posted Write Target Termination ....................................................................................................... 25
4-9. Responses to Delayed Read Target Termination...................................................................................................... 25
6-1. SummaryofTranactionOrdering .............................................................................................................................. 33
7-1. SettingthePrimary InterfaceDetectedParityErrorBit ............................................................................................. 39
7-2. Setting the Secondary Interface Detected Parity Error Bit ........................................................................................ 40
7-3. Settingthe PrimaryInterfaceData ParityDetected Bit.............................................................................................. 40
7-4. Setting the Secondary InterfaceData Parity Detected Bit ......................................................................................... 41
7-5. Assertionof P_PERR#............................................................................................................................................... 42
7-6. Assertionof S_PERR#............................................................................................................................................... 43
7-7. Assertionof P_SERR# forData Parity Errors ........................................................................................................... 44
15-1. TAP Pins .................................................................................................................................................................... 73
15-2. JTAGBoundaryRegister Order ................................................................................................................................ 75

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
09/18/00 Rev1.1
Appendix A - Timing Diagrams
1. Configuration Read Transaction .................................................................................................................................A-3
2. Configuration Write Transaction ................................................................................................................................A-3
3. Type 1 to Type 0 Configuration Read Transaction (P →S) ......................................................................................A-3
4. Type 1 to Type 0 Configuration Write Transaction (P →S) .....................................................................................A-4
5. Upstream Type 1 to Special Cycle Transaction (S →P) .............................................................................................A-4
6. Downstream Type 1 to Special Cycle Transaction (P →S) ........................................................................................A-5
7. Downstream Type 1 to Type 1 Configuration Read Transaction (P →S) ..................................................................A-5
8. Downstream Type 1 to Type 1 Configuration Write Transaction (P →S) .................................................................A-6
9. Upstream Delayed Burst Memory Read Transaction (S →P) ...................................................................................A-6
10. Downstream Delayed Burst Memory Read Transaction (P →S) ..............................................................................A-7
11. Downstream Delayed Memory Read Transaction (P/33MHz →S/33MHz)...............................................................A-7
12. Downstream Delayed Memory Read Transaction (S2/33MHz →S1/33MHz)...........................................................A-8
13. Downstream Delayed Memory Read Transaction (S1/33MHz →S2/33MHz)...........................................................A-8
14. Upstream Delayed Memory Read Transaction (S/33MHz →P/33MHz) ...................................................................A-9
15. Downstream Posted Memory Write Transaction (P/33MHz →S/33MHz)................................................................A-9
16. Downstream Posted Memory Write Transaction (S2/33MHz →S1/33MHz) ...........................................................A-10
17. Downstream Posted Memory Write Transaction (S1/33MHz →S2/33MHz) ...........................................................A-10
18. Upstream Posted Memory Write Transaction (S/33MHz →P/33MHz) ...................................................................A-11
19. Downstream Flow-Through Posted Memory Write Transaction (P/33MHz →S/33MHz)........................................A-11
20. Downstream Flow-Through Posted Memory Write Transaction (S2/33MHz →S1/33MHz)....................................A-12
21. Downstream Flow-Through Posted Memory Write Transaction (S1/33MHz →S2/33MHz)....................................A-12
22. Upstream Flow-Through Posted Memory Write Transaction (S/33MHz →P/33MHz) ............................................A-13
23. Downstream Delayed I/O Read Transaction (P →S) ...............................................................................................A-13
24. Downstream Delayed I/O ReadTransaction (S2/33MHz →S1/33MHz) ..................................................................A-14
25. Downstream Delayed I/O ReadTransaction (S1/33MHz →S2/33MHz) ..................................................................A-14
26. Downstream Delayed I/O Read Transaction (S/33MHz →P/33MHz) ......................................................................A-15
27. Downstream Delayed I/O Write Transaction (P →S) ..............................................................................................A-15
28. Downstream DelayedI/OWrite Transaction(S2/33MHz →S1/33MHz) .................................................................A-16
29. Downstream DelayedI/OWrite Transaction(S1/33MHz →S2/33MHz) .................................................................A-16
30. Upstream Delayed I/O Write Transaction (S →P) ...................................................................................................A-17
Appendix B - Evaluation Board User's Manual
GeneralInformation ........................................................................................................................................................... B-3
Frequently Asked Questions ............................................................................................................................................ B-5
Appendix C - Three-Port PCI Bridge Evaluation Board Schematics
PCIChip ............................................................................................................................................................................. C-3
PCIEdgeConnector .......................................................................................................................................................... C-4
Secondary 1 PCI Bus ......................................................................................................................................................... C-5
Secondary 2 PCI Bus ......................................................................................................................................................... C-6
TopView ............................................................................................................................................................................ C-7
Appendix D - Representatives and Distributors

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Product Features
• 32-bit Primary & two Secondary Ports run up to 33 MHz
• All three ports compliant with the PCI Local Bus
Specification,Revision2.1
• CompliantwithPCI-to-PCIBridgeArchitectureSpecification,Revision1.0.
- All I/O and memory commands
- Type1toType0configurationconversion
- Type1toType1configurationforwarding
- Type1configuration-writetospecialcycleconversion
• Concurrentprimarytosecondarybusoperationandindependentintra-secondaryport
channelto reducetraffic onthe primary port
• Provides internal arbitration for two sets of eight secondary bus masters
- Programmable 2-level priority arbiter
- Disable control for use of external arbiter
• Supportspostedwritebufferson all directions
• Three128byteFIFOs for delaytransactions
• Three128byteFIFOsforpostedmemorytransactions
• Enhancedaddressdecoding
- 32-bitI/Oaddressrange
- 32-bit memory-mapped I/O address range
- VGA addressing and VGA palette snooping
- ISA-aware mode for legacy support in the first 64KB
ofI/Oaddressrange
• InterruptHandling
- PCIinterruptsareroutedthroughanexternalinterruptconcentrator
• Supportssystem transaction orderingrules
• Hot-plugsupportonsecondarybuses
- 3-Statecontrolofoutputbuffers
• IEEE1149.1JTAGinterfacesupport
• 3.3V core; 3.3V PCI I/O interface with 5V I/O Tolerant
• 256-pin plastic BGA package
Product Description
PI7C7100isthefirsttripleportPCI-to-PCIBridgedevicedesignedtobefullycompliantwiththe32-bit,
33 MHz implementation of the PCI Local Bus Specification, Revision 2.1 . PI7C7100 supports only
synchronousbustransactionsbetweendevicesontheprimary33MHzbusandthesecondarybuses
operating at 33 MHz. The primary and the secondary buses can also operate in concurrent mode,
resultinginaddedincreaseinsystemperformance. Concurrentbusoperationoff-loadsandisolates
unnecessarytrafficfromtheprimarybus;therebyenablingamasterandatargetdeviceonthesame
secondary PCI bus to communicate even while the primary bus is busy.
1. Introduction

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PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Figure 1-2. PI7C7100 in Redundant Application
Figure 1-1. PI7C7100 on the System Board
S1 PCI Bus
S2 PCI Bus
PI7C7100
CPU
NB
Slot Slot
System
Memory
PCI
Device
PCI
Device
PI7C7100
System Primary
PCI Bus
PI7C7100
S1 PCI Bus
Master Controller Redundant Controller
S2 PCI Bus
System Primary
PCI Bus
S1 S1 S2
S2
Figure 1-3. PI7C7100 on Network Switching Hub
CPU
PCI Bus 32/33
PI7C7100
PCI Bus 32/33
Core
Logic
L2
Cache
I/O Daughter
Board to
IsolateTraffic
PI7C7100 PI7C7100
Fast
Ethernet
Internal
Slot