Plura PCIe 3G User manual

Operating Manual
Version: 5.35
September 25, 2019
Time Code Reader Board
PCIe 3G, LV, L
PCIe 3G

Operating Manual PCIe 3G, LV, L
TABLE OF CONTENTS Page
A1 REVISION HISTORY
A2 SAFETY INSTRUCTIONS
A3 COPYRIGHT
A4 CE DECLARATION
B FUNCTIONS 7
B1 OVERVIEW 7
B2 TIME CODE FEATURES 8
Time Code register 8
Frame rate 9
Error checks 9
Flying wheel 10
VITC level matching 10
DVITC level matching 10
B3 CONNECTIONS AND TECHNICAL DATA 11
PCIe L, LV, D, HD, 3G 12
PCI L, LV, D, HD 13
B4 INSTALLATION 14
B5 FIRMWARE UPDATE 15
C PROGRAMMING 16
C1 AVPCL32 DRIVER 16
Windows Driver Structure 16
Driver Files 16
SDK Files and Linux Driver 17
C2 DATA ACCESS 19
Memory vs. I/O access 19
Register set 19
Register 20
Commands 21
D OPTIONS 36
D1 OPTION “GPI OUT“: TWO SIGNAL OUTPUTS 36
Description 36
Commands 37
Connections and Technical Data 38
Availability 39

Operating Manual PCIe 3G, LV, L
A1 Revision History
No.
Date
Subject
3.37
December 3, 2008
4.67
November 29, 2011
Added PCIe 3G board.
Added firmware update procedure.
4.68
January 12, 2012
Added Windows 7 support.
Added functions pclGetVideoStandard, pclGetGpi, pclGetPayloadIdentifier and pclSetUsePay-
loadIdentifier.
4.72
August 27, 2012
Added Windows 8 support.
4.75
October 9, 2012
Added function pclGetAncDataTab.
4.77
March 20, 2015
Changed PCL PCI / PCL PCIe to PCI / PCIe.
5.34
November 16, 2017
Added Windows 10 support.
Added Linux installation.
Corrected RJ45 orientation in PCIe drawing.
5.35
September 25, 2019
Changed address of Plura Europe GmbH.
A2 Safety Instructions
General rules Only use the device as directed in a dry atmosphere. Treat the
PCIe 3G, LV, L board with the same care as other PC boards.
Please follow the advice in the following operator’s manual.
Damages in transit In case the device shows obvious damages from transit the shipper
in question must be notified and the dealer must be informed.
Repairs The PCIe 3G, LV, L board does not require any extra maintenance.
There are no user serviceable parts at the device. Repairs should
be sent to an authorized service partner.
EMC The EMC regulations are observed only under the following condi-
tion: use high quality shielded cables at data inputs and outputs.

Operating Manual PCIe 3G, LV, L
A3 Copyright
No part of this publication may be reproduced, translated into another language, stored in a
retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photo-
copying, recording, or otherwise without the prior written consent of Plura Europe GmbH.
Technical changes are reserved. All brand and product names mentioned herein are used for
identification purposes only and are trademarks or registered trademarks of their respective
holders.
Information in this publication replaces all previously published information. Plura Europe
GmbH assumes no responsibility for errors or omissions. Neither is any liability assumed for
damages resulting from the use of the information contained herein. Whenever it is likely that
safe operation is impaired, the instrument must be made inoperative and secured against
unintended operation. The appropriate service authority must then be informed.
Copyright © Plura Europe GmbH 1999-2019. All rights reserved.
For further information please contact your local dealer or:
Plura Europe GmbH
Binger Weg 12
D- 55437 Ockenheim
Phone: [phone]
Fax: [phone]
E-Mail: [e-mail]
Internet: http://www.plurainc.com

Operating Manual PCIe 3G, LV, L
A4 CE Declaration
We,
Plura Europe GmbH
Binger Weg 12
D- 55437 Ockenheim
declare under our sole responsibility that the
PCIe 3G, LV, L
meets the intent of the following directives, standards and specifications:
89/336/EEC Electromagnetic Compatibility
EN 50081-1 Emissions
•EN 55022
•EN 55103-1
EN 50082-1 Immunity
•EN 55024
•EN 55103-2

Operating Manual PCIe 3G, LV, L
Page 7
B Functions
B1 Overview
Models
The PCIe 3G, LV, L are Time Code reader boards for PC’s with a PCI Bus. This is an easy,
fast, professional, and technically advanced way for the user to integrate Time Code into its
applications. The board has its own processor system with a register set for data transfer.
Thus, the critical time routines are completely decoupled from the PC’s CPU.
The PCI / PCIe board range consists basically of the following models:
PCIe 3G High-Speed LTC, DVITC and ATC reader, 3G/HD/SD video, PCIe bus
PCIe LV High-Speed LTC and VITC (CVBS video) reader, PCIe bus
PCIe L High-Speed LTC reader, PCIe bus
And the discontinued models:
PCIe HD High-Speed LTC, DVITC and ATC reader, HD/SD video, PCIe bus
PCIe D High-Speed LTC and DVITC (SD video) reader, PCIe bus
PCI HD High-Speed LTC, DVITC and ATC reader, HD/SD video, universal 3.3V
/ 5V PCI bus
PCI D High-Speed LTC and DVITC (SD video) reader, universal 3.3V / 5V PCI
bus
PCI LV High-Speed LTC and VITC (CVBS video) reader, universal 3.3V / 5V
PCI bus
PCI L High-Speed LTC reader, universal 3.3V / 5V PCI bus
Variants of the models are available upon request.
LTC reader
Reads Linear Time Code according to ANSI/SMPTE 12M-1995. Reader accepts slow and
high speed from 1 to 2500 frames per second (fps), in forward and reverse directions. Simul-
taneous decoding of time and user information. Input 100mV to 5Vpp, balanced or unbal-
anced, 2 x RCA connector. Automatic detection of the frame rate (can be switched off).
VITC reader
Reads Vertical Interval Time Code according to ANSI/SMPTE 12M-1995. Reader accepts
VITC from still picture to search speed. Simultaneous decoding of time and user information.
Automatic adaptation at the VITC data level. 1 x BNC connector, 75 termination can be
switched off. Automatic VITC lines detection, but a single line, 2 lines or a range of lines can
be selected as well. Automatic detection of the frame rate (can be switched off).
DVITC reader
Reads Digital Vertical Interval Time Code according to SMPTE 266M-1994. Automatic level
matching at DVITC data level can be selected. Simultaneous decoding of time and user in-
formation. Input SD video (4:2:2 component, SMPTE 259M-1997), 1 x BNC connector with
75 termination. Automatic DVITC lines detection, but a single line, 2 lines or a range of
lines can be selected as well. Automatic detection of the frame rate (can be switched off).

Operating Manual PCIe 3G, LV, L
Page 8
ATC reader
Reads Ancillary Time Code (SMPTE RP 188-1999) and HANC Time Code (SMPTE RP 196-
1997). Simultaneous decoding of time and user information. Input SD video (4:2:2 compo-
nent, SMPTE 259M-1997), HD video (SMPTE 292M-1998), or 3G Video (SMPTE 424M-
2006), 1 x BNC connector with 75 termination. Automatic detection of the frame rate (can
be switched off).
PC interface
32-Byte-register set for data transfer to PCI interface. Parallel operating of several PCIe 3G,
LV, L boards is possible. Selectable interrupt control. Board for the PCI local bus, 32Bit / 33
MHz slot.
Driver support
Drivers and example programs are included for Windows Vista / 7 / 8 / 10, server 2008 /
2012 / 2016, and Linux, in 32-bit and 64-bit versions, respectively. DLL functions for reading
Time Code rates and configuration are given. C/C++, Delphi and Visual Basic are support-
ed.
Linux driver are included in source code.
B2 Time Code features
Time Code register
Time Code data transfer from the PCIe 3G, LV, L to the PC takes place by using a register
(command 0x43: pclGetRegister).
The LTC register holds the data from the LTC reader. The reader checks for plausible time
information, detects the direction (forward or reverse) or checks for a still LTC. In case of a still
LTC the time values do not change frame by frame, this data is then transferred to the regis-
ter. In all other cases the time will be counted + 1 frame during forward, - 1 frame during
reverse, and then transferred to the register. A flag bit indicates the direction of the LTC.
The VITC register holds the data of the VITC/DVITC reader. Having passed the plausibility
check the data is transferred to the register immediately. This takes place every field. A flag bit
indicates the first and second field.
The mixed register holds LTC or VITC/DVITC data, controlled by the commands 0x20
(pclMixedEnable) and 0x21 (pclPriority). Command 0x20 enables LTC or VITC/DVITC for us-
ing the mixed register. Command 0x21 sets the priority, if both LTC and VITC/DVITC is read
simultaneously.
The ATC reader receives data packets and checks the type of Time Code. The decoded data
will then be transferred to the special registers, as there are ATC LTC, ATC VITC, HANC LTC
and HANC VITC. These Time Codes cannot be transferred to the mixed register.

Operating Manual PCIe 3G, LV, L
Page 9
Frame rate
The automatic frame rate detection sets the frame rate to 24, 25, 30 (without drop) or 30
drop mode, individual for LTC and VITC/DVITC. After power-on the frame rate is pre-set to
25 and the automatic frame rate detection is turned on. The automatic frame rate detection
can be switched off by setting the frame rate manually. Command 0x30 (pclTcFrames) does
this for LTC and VITC/DVITC simultaneously. Command 0x31 alters the LTC frame rate
mode, command 0x32 the VITC frame rate mode.
Error checks
The read Time Code values are checked of plausible time data and of a correct time se-
quence without breaks or drop-outs. Plausible data will be transferred to the Time Code regis-
ters and announced as new data. Any errors are indicated with an error counter. This enables
you to verify that a Time Code source is free of errors.
The LTC error counter can be read by command 0x17 (pclLtcError). Errors counted are: im-
plausible time data and/or a discontinuity of the time sequence (new frame should be 1
frame of previous frame).
The VITC/DVITC error counter can be read by command 0x18 (pclVitcError). Errors counted
are: implausible time data and/or a discontinuity of the time sequence (check at every 1st
field: time of new frame should be + 1 of previous frame, check at every 2nd field: time
should be equal to 1st field). In case the automatic level matching is switched on (see chapter
below), further errors will be counted while the automatic is active (after a loss of video or a
time-out of VITC/DVITC).
The error check with the flying wheel feature (see next chapter) enabled at same time does not
give a valid result with regard to the continuity check of the time sequence.
The ATC error counters can be read by commands 0x22 (pclAtcLtcError), 0x23 (pclAtcVitcEr-
ror), 0x25 (pclHancLtcError) and 0x26 (pclHancVitcError). Errors counted are: implausible
time data and/or a discontinuity of the time sequence (in case of LTC: new frame should be +
1 frame of previous frame; in case of VITC: new field should be equal to or + 1 frame of
previous field).
The following access modes are provided for the commands:
•CMDD0 = $00: request and automatic reset and initialization of the error counter. After
this command the error counter will be set to zero and the first Time Code will not count
an error. This command should be used to start with a new error check.
•CMDD0 = $01: request only. The error counter has a maximum value of 255, at further
errors the counter will remain at this maximum value. This command may be used to ver-
ify that Time Code can be read without errors. The exact amount of errors may not be of
special interest.
•CMDD0 = $02: request and automatic reset to zero. If a large number of errors is ex-
pected and the amount of errors is of interest, the application software should use this
command and create an own error counter.

Operating Manual PCIe 3G, LV, L
Page 10
Flying wheel
The flying wheel serves as a drop-out compensation for a continuous up-counting Time Code.
Command 0x19 (pclFlyWheel) enables or disables this feature for LTC and VITC/DVITC sepa-
rately. It is not available for any ATC Time Code. After power-on the flying wheel is disabled.
If enabled, an internal counter can continue to transfer new time data to the Time Code regis-
ters if the Time Code source has drop-outs. The flying wheel only works if the last read Time
Code was free of errors, i.e. in a correct timing sequence and within a specific frequency
range. The flying wheel is not a precise clock; its goal is to overcome a few seconds of miss-
ing Time Code.
With LTC the flying wheel is able to synchronize to the incoming LTC frequency in a range of
15 - 60 frames/second. The accuracy will be 1 frame each minute.
With VITC/DVITC the flying wheel transfers data corresponding to the first field only. The cur-
rent frame rate determines the television system: 25 = 625/50 (PAL), 30 = 525/60 (NTSC).
The accuracy will be better than 1 frame in ten minutes.
VITC level matching
After power-on the automatic level matching is switched on. The VITC reader analyzes the
VITC level and adjusts the threshold to an optimal value. This assures readability of VITC over
a wide range of video or VITC levels. In case of a lack of VITC or of cumulative errors the
process starts again. This procedure requires a few seconds to find the best value. If the video
signal is very bad (for example working in the jog or shuttle mode with a VHS recorder), the
automatic level matching feature on one hand can help make it possible to read the VITC, or
on the other hand it can produce additional errors during adjustment. So, whether the auto-
matic mode gives better results or not depends on the application and should be tested. Us-
ing command 0x16 (pclVitcLevelControl) the automatic can be switched on and off, further-
more the current threshold value can be requested and can be set explicitly. The values must
be within range 0x00 to 0x5A, this corresponds to a voltage level from -100mV to +1400mV
approximately (0V = black level of the video). The default value is 0x16 (270mV).
DVITC level matching
Similar to the analogue VITC, the best threshold value for the DVITC can be adjusted auto-
matically as well. But after power-on the automatic level matching is switched off, and an
average value is pre-set. Using command 0x16 (pclVitcLevelControl) the automatic can be
switched on and off, furthermore the current threshold value can be requested and can be set
explicitly. The input values must be within range 0x00 to 0x5A; this will be transformed to
values of the digital video from 0x10 to 0xC4. The default value is 0x32 (corresponding to
0x74).