Plura PCIe 3G User manual

Operating Manual
Version: 5.35
September 25, 2019
Time Code Reader Board
PCIe 3G, LV, L
PCIe 3G

Operating Manual PCIe 3G, LV, L
TABLE OF CONTENTS Page
A1 REVISION HISTORY
A2 SAFETY INSTRUCTIONS
A3 COPYRIGHT
A4 CE DECLARATION
B FUNCTIONS 7
B1 OVERVIEW 7
B2 TIME CODE FEATURES 8
Time Code register 8
Frame rate 9
Error checks 9
Flying wheel 10
VITC level matching 10
DVITC level matching 10
B3 CONNECTIONS AND TECHNICAL DATA 11
PCIe L, LV, D, HD, 3G 12
PCI L, LV, D, HD 13
B4 INSTALLATION 14
B5 FIRMWARE UPDATE 15
C PROGRAMMING 16
C1 AVPCL32 DRIVER 16
Windows Driver Structure 16
Driver Files 16
SDK Files and Linux Driver 17
C2 DATA ACCESS 19
Memory vs. I/O access 19
Register set 19
Register 20
Commands 21
D OPTIONS 36
D1 OPTION “GPI OUT“: TWO SIGNAL OUTPUTS 36
Description 36
Commands 37
Connections and Technical Data 38
Availability 39

Operating Manual PCIe 3G, LV, L
A1 Revision History
No.
Date
Subject
3.37
December 3, 2008
4.67
November 29, 2011
Added PCIe 3G board.
Added firmware update procedure.
4.68
January 12, 2012
Added Windows 7 support.
Added functions pclGetVideoStandard, pclGetGpi, pclGetPayloadIdentifier and pclSetUsePay-
loadIdentifier.
4.72
August 27, 2012
Added Windows 8 support.
4.75
October 9, 2012
Added function pclGetAncDataTab.
4.77
March 20, 2015
Changed PCL PCI / PCL PCIe to PCI / PCIe.
5.34
November 16, 2017
Added Windows 10 support.
Added Linux installation.
Corrected RJ45 orientation in PCIe drawing.
5.35
September 25, 2019
Changed address of Plura Europe GmbH.
A2 Safety Instructions
General rules Only use the device as directed in a dry atmosphere. Treat the
PCIe 3G, LV, L board with the same care as other PC boards.
Please follow the advice in the following operator’s manual.
Damages in transit In case the device shows obvious damages from transit the shipper
in question must be notified and the dealer must be informed.
Repairs The PCIe 3G, LV, L board does not require any extra maintenance.
There are no user serviceable parts at the device. Repairs should
be sent to an authorized service partner.
EMC The EMC regulations are observed only under the following condi-
tion: use high quality shielded cables at data inputs and outputs.

Operating Manual PCIe 3G, LV, L
A3 Copyright
No part of this publication may be reproduced, translated into another language, stored in a
retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photo-
copying, recording, or otherwise without the prior written consent of Plura Europe GmbH.
Technical changes are reserved. All brand and product names mentioned herein are used for
identification purposes only and are trademarks or registered trademarks of their respective
holders.
Information in this publication replaces all previously published information. Plura Europe
GmbH assumes no responsibility for errors or omissions. Neither is any liability assumed for
damages resulting from the use of the information contained herein. Whenever it is likely that
safe operation is impaired, the instrument must be made inoperative and secured against
unintended operation. The appropriate service authority must then be informed.
Copyright © Plura Europe GmbH 1999-2019. All rights reserved.
For further information please contact your local dealer or:
Plura Europe GmbH
Binger Weg 12
D- 55437 Ockenheim
Phone: [phone]
Fax: [phone]
E-Mail: [e-mail]
Internet: http://www.plurainc.com

Operating Manual PCIe 3G, LV, L
A4 CE Declaration
We,
Plura Europe GmbH
Binger Weg 12
D- 55437 Ockenheim
declare under our sole responsibility that the
PCIe 3G, LV, L
meets the intent of the following directives, standards and specifications:
89/336/EEC Electromagnetic Compatibility
EN 50081-1 Emissions
•EN 55022
•EN 55103-1
EN 50082-1 Immunity
•EN 55024
•EN 55103-2

Operating Manual PCIe 3G, LV, L
Page 7
B Functions
B1 Overview
Models
The PCIe 3G, LV, L are Time Code reader boards for PC’s with a PCI Bus. This is an easy,
fast, professional, and technically advanced way for the user to integrate Time Code into its
applications. The board has its own processor system with a register set for data transfer.
Thus, the critical time routines are completely decoupled from the PC’s CPU.
The PCI / PCIe board range consists basically of the following models:
PCIe 3G High-Speed LTC, DVITC and ATC reader, 3G/HD/SD video, PCIe bus
PCIe LV High-Speed LTC and VITC (CVBS video) reader, PCIe bus
PCIe L High-Speed LTC reader, PCIe bus
And the discontinued models:
PCIe HD High-Speed LTC, DVITC and ATC reader, HD/SD video, PCIe bus
PCIe D High-Speed LTC and DVITC (SD video) reader, PCIe bus
PCI HD High-Speed LTC, DVITC and ATC reader, HD/SD video, universal 3.3V
/ 5V PCI bus
PCI D High-Speed LTC and DVITC (SD video) reader, universal 3.3V / 5V PCI
bus
PCI LV High-Speed LTC and VITC (CVBS video) reader, universal 3.3V / 5V
PCI bus
PCI L High-Speed LTC reader, universal 3.3V / 5V PCI bus
Variants of the models are available upon request.
LTC reader
Reads Linear Time Code according to ANSI/SMPTE 12M-1995. Reader accepts slow and
high speed from 1 to 2500 frames per second (fps), in forward and reverse directions. Simul-
taneous decoding of time and user information. Input 100mV to 5Vpp, balanced or unbal-
anced, 2 x RCA connector. Automatic detection of the frame rate (can be switched off).
VITC reader
Reads Vertical Interval Time Code according to ANSI/SMPTE 12M-1995. Reader accepts
VITC from still picture to search speed. Simultaneous decoding of time and user information.
Automatic adaptation at the VITC data level. 1 x BNC connector, 75 termination can be
switched off. Automatic VITC lines detection, but a single line, 2 lines or a range of lines can
be selected as well. Automatic detection of the frame rate (can be switched off).
DVITC reader
Reads Digital Vertical Interval Time Code according to SMPTE 266M-1994. Automatic level
matching at DVITC data level can be selected. Simultaneous decoding of time and user in-
formation. Input SD video (4:2:2 component, SMPTE 259M-1997), 1 x BNC connector with
75 termination. Automatic DVITC lines detection, but a single line, 2 lines or a range of
lines can be selected as well. Automatic detection of the frame rate (can be switched off).

Operating Manual PCIe 3G, LV, L
Page 8
ATC reader
Reads Ancillary Time Code (SMPTE RP 188-1999) and HANC Time Code (SMPTE RP 196-
1997). Simultaneous decoding of time and user information. Input SD video (4:2:2 compo-
nent, SMPTE 259M-1997), HD video (SMPTE 292M-1998), or 3G Video (SMPTE 424M-
2006), 1 x BNC connector with 75 termination. Automatic detection of the frame rate (can
be switched off).
PC interface
32-Byte-register set for data transfer to PCI interface. Parallel operating of several PCIe 3G,
LV, L boards is possible. Selectable interrupt control. Board for the PCI local bus, 32Bit / 33
MHz slot.
Driver support
Drivers and example programs are included for Windows Vista / 7 / 8 / 10, server 2008 /
2012 / 2016, and Linux, in 32-bit and 64-bit versions, respectively. DLL functions for reading
Time Code rates and configuration are given. C/C++, Delphi and Visual Basic are support-
ed.
Linux driver are included in source code.
B2 Time Code features
Time Code register
Time Code data transfer from the PCIe 3G, LV, L to the PC takes place by using a register
(command 0x43: pclGetRegister).
The LTC register holds the data from the LTC reader. The reader checks for plausible time
information, detects the direction (forward or reverse) or checks for a still LTC. In case of a still
LTC the time values do not change frame by frame, this data is then transferred to the regis-
ter. In all other cases the time will be counted + 1 frame during forward, - 1 frame during
reverse, and then transferred to the register. A flag bit indicates the direction of the LTC.
The VITC register holds the data of the VITC/DVITC reader. Having passed the plausibility
check the data is transferred to the register immediately. This takes place every field. A flag bit
indicates the first and second field.
The mixed register holds LTC or VITC/DVITC data, controlled by the commands 0x20
(pclMixedEnable) and 0x21 (pclPriority). Command 0x20 enables LTC or VITC/DVITC for us-
ing the mixed register. Command 0x21 sets the priority, if both LTC and VITC/DVITC is read
simultaneously.
The ATC reader receives data packets and checks the type of Time Code. The decoded data
will then be transferred to the special registers, as there are ATC LTC, ATC VITC, HANC LTC
and HANC VITC. These Time Codes cannot be transferred to the mixed register.

Operating Manual PCIe 3G, LV, L
Page 9
Frame rate
The automatic frame rate detection sets the frame rate to 24, 25, 30 (without drop) or 30
drop mode, individual for LTC and VITC/DVITC. After power-on the frame rate is pre-set to
25 and the automatic frame rate detection is turned on. The automatic frame rate detection
can be switched off by setting the frame rate manually. Command 0x30 (pclTcFrames) does
this for LTC and VITC/DVITC simultaneously. Command 0x31 alters the LTC frame rate
mode, command 0x32 the VITC frame rate mode.
Error checks
The read Time Code values are checked of plausible time data and of a correct time se-
quence without breaks or drop-outs. Plausible data will be transferred to the Time Code regis-
ters and announced as new data. Any errors are indicated with an error counter. This enables
you to verify that a Time Code source is free of errors.
The LTC error counter can be read by command 0x17 (pclLtcError). Errors counted are: im-
plausible time data and/or a discontinuity of the time sequence (new frame should be 1
frame of previous frame).
The VITC/DVITC error counter can be read by command 0x18 (pclVitcError). Errors counted
are: implausible time data and/or a discontinuity of the time sequence (check at every 1st
field: time of new frame should be + 1 of previous frame, check at every 2nd field: time
should be equal to 1st field). In case the automatic level matching is switched on (see chapter
below), further errors will be counted while the automatic is active (after a loss of video or a
time-out of VITC/DVITC).
The error check with the flying wheel feature (see next chapter) enabled at same time does not
give a valid result with regard to the continuity check of the time sequence.
The ATC error counters can be read by commands 0x22 (pclAtcLtcError), 0x23 (pclAtcVitcEr-
ror), 0x25 (pclHancLtcError) and 0x26 (pclHancVitcError). Errors counted are: implausible
time data and/or a discontinuity of the time sequence (in case of LTC: new frame should be +
1 frame of previous frame; in case of VITC: new field should be equal to or + 1 frame of
previous field).
The following access modes are provided for the commands:
•CMDD0 = $00: request and automatic reset and initialization of the error counter. After
this command the error counter will be set to zero and the first Time Code will not count
an error. This command should be used to start with a new error check.
•CMDD0 = $01: request only. The error counter has a maximum value of 255, at further
errors the counter will remain at this maximum value. This command may be used to ver-
ify that Time Code can be read without errors. The exact amount of errors may not be of
special interest.
•CMDD0 = $02: request and automatic reset to zero. If a large number of errors is ex-
pected and the amount of errors is of interest, the application software should use this
command and create an own error counter.

Operating Manual PCIe 3G, LV, L
Page 10
Flying wheel
The flying wheel serves as a drop-out compensation for a continuous up-counting Time Code.
Command 0x19 (pclFlyWheel) enables or disables this feature for LTC and VITC/DVITC sepa-
rately. It is not available for any ATC Time Code. After power-on the flying wheel is disabled.
If enabled, an internal counter can continue to transfer new time data to the Time Code regis-
ters if the Time Code source has drop-outs. The flying wheel only works if the last read Time
Code was free of errors, i.e. in a correct timing sequence and within a specific frequency
range. The flying wheel is not a precise clock; its goal is to overcome a few seconds of miss-
ing Time Code.
With LTC the flying wheel is able to synchronize to the incoming LTC frequency in a range of
15 - 60 frames/second. The accuracy will be 1 frame each minute.
With VITC/DVITC the flying wheel transfers data corresponding to the first field only. The cur-
rent frame rate determines the television system: 25 = 625/50 (PAL), 30 = 525/60 (NTSC).
The accuracy will be better than 1 frame in ten minutes.
VITC level matching
After power-on the automatic level matching is switched on. The VITC reader analyzes the
VITC level and adjusts the threshold to an optimal value. This assures readability of VITC over
a wide range of video or VITC levels. In case of a lack of VITC or of cumulative errors the
process starts again. This procedure requires a few seconds to find the best value. If the video
signal is very bad (for example working in the jog or shuttle mode with a VHS recorder), the
automatic level matching feature on one hand can help make it possible to read the VITC, or
on the other hand it can produce additional errors during adjustment. So, whether the auto-
matic mode gives better results or not depends on the application and should be tested. Us-
ing command 0x16 (pclVitcLevelControl) the automatic can be switched on and off, further-
more the current threshold value can be requested and can be set explicitly. The values must
be within range 0x00 to 0x5A, this corresponds to a voltage level from -100mV to +1400mV
approximately (0V = black level of the video). The default value is 0x16 (270mV).
DVITC level matching
Similar to the analogue VITC, the best threshold value for the DVITC can be adjusted auto-
matically as well. But after power-on the automatic level matching is switched off, and an
average value is pre-set. Using command 0x16 (pclVitcLevelControl) the automatic can be
switched on and off, furthermore the current threshold value can be requested and can be set
explicitly. The input values must be within range 0x00 to 0x5A; this will be transformed to
values of the digital video from 0x10 to 0xC4. The default value is 0x32 (corresponding to
0x74).

Operating Manual PCIe 3G, LV, L
Page 11
B3 Connections and Technical Data
Connections
Input
Connector
Signal description
LTC-1
LTC-2
(PCI Boards)
2 x RCA jack
LTC input, balanced or unbalanced, 100 mVpp to 5 Vpp , fre-
quency 1 to 2500 frames/sec.
LTC / GPI
(PCIe
Boards)
RJ45
LTC input, balanced or unbalanced, 100 mVpp to 5 Vpp , fre-
quency 1 to 2500 frames/sec.
Video Input
(PCI LV,
PCIe LV)
BNC, 75 
(IEC 169-8)
Composite video input, 75 termination can be switched off.
Television system 525/60 (NTSC) or 625/50 (PAL).
DC offset: < 12V, sync amplitude = 300mV 6dB (150mV-
600mV).
VITC data level: Vmin (“1”) = 200mV, Vmax (“0”) = 500mV, V1-0
(“1” - “0”) 200mV.
Video Input
(PCI D,
PCIe D)
BNC, 75 
(IEC 169-8)
SD input, 8/10 bit according to SMPTE 259M-C: 270 Mb/s,
525/625 components.
Video Input
(PCI HD,
PCIe HD)
BNC, 75 
(IEC 169-8)
SD input, 8/10 bit according to SMPTE 259M-C: 270 Mb/s,
525/625 components.
HD input, 8/10 bit according to SMPTE 292M-1998: 1.485
Gb/s.
Video Input
(PCIe 3G)
BNC, 75 
(IEC 169-8)
SD input, 8/10 bit according to SMPTE 259M-C: 270 Mb/s,
525/625 components.
HD input, 8/10 bit according to SMPTE 292M-1998: 1.485
Gb/s.
3G input, 8/10 bit according to SMPTE 422M-2006: 2.970
Gb/s.

Operating Manual PCIe 3G, LV, L
Page 12
PCIe L, LV, D, HD, 3G
1 2
LTC / GPI
Pin
Signal
Pin
Signal
3
LTC Input LTC-1
1
GPI 1 GND
6
LTC Input LTC-2
2
GPI 1 I/O
4
LTC GND
7
GPI 2 GND
5
8
GPI 2 I/O
Switches
SW1
LTC Input
SW2
PCI LV:
Video Input Termina-
tion
PCIe 3G
PCIe HD
PCIe D
ON
Unbalanced LTC input to LTC-2
ON
75 termination
n/a
OFF
Balanced LTC input to LTC-1
and LTC-2
OFF
no termination
n/a
Technical data
Dimensions over all
(Length x Height x Width)
PCIe 3G:
150 x 120 x 22 mm (standard profile slot)
150 x 80 x 22 mm (low profile slot)
PCIe L / LV / D / HD:
191 x 120 x 22 mm (standard profile slot)
191 x 80 x 22 mm (low profile slot)
Weight
≈80 g
Operating voltage
3.3 VDC and 12 VDC
Power consumption
3 W
Ambient temperature
5 –40 °C
Relative humidity
35 –85 %
1……8
LTC / GPI SW1 SW2 Video Input

Operating Manual PCIe 3G, LV, L
Page 13
PCI L, LV, D, HD
1 2
ON
LTC-1 LTC-2 SW1 SW2 Video Input
Switches
SW1
LTC Input
ON
Unbalanced LTC input to LTC-2
OFF
Balanced LTC input to LTC-1 and LTC-2
SW2
PCI LV:
Video Input Termination
PCI D:
Equalization
PCI HD:
ON
75 termination
Gain equalization 270 Mb/s automatic up
to 100m (Belden 8281, PSF 1/3 or equiva-
lent)
n/a
OFF
no termination
Equalization bypass, used for short cable
length (< 10m)
n/a
Technical data
Dimensions over all
(Length x Height x Width)
141 x 120 x 22 mm
Weight
≈110 g
Operating voltage
3.3 VDC and 5 VDC
Power consumption
2 W
Ambient temperature
5 –40 °C
Relative humidity
35 –85 %

Operating Manual PCIe 3G, LV, L
Page 14
B4 Installation
For an installation in a PC with a Windows operating system please follow these instructions:
•Log in as Administrator and run the script “Install Driver.bat” from the CD-ROM
shipped with the board. This installs the device driver for the PCIe 3G, LV, L board.
•Set the DIP switch to match the input signals of the PCIe 3G, LV, L board according to
the previous passage. You can change the setting if required, even after the board
has been installed.
•Shut down the PC and switch it off.
•Slide the PCIe 3G, LV, L board into a free slot. Ensure a proper fit in the PCI slot and
then tighten the board into the slot, with the existing screw.
•Switch on the PC, boot it up and log in as Administrator.
•Windows will detect the new board automatically. If it asks for the driver disk, insert
the CD-ROM shipped with the PCIe 3G, LV, L board. Alternatively you may download
the latest version from https://www.plurainc.com (under the menu “Downloads”), un-
pack it and choose it as source for the driver.
•With this step the installation of the driver is complete. You may now test the PCIe 3G,
LV, L board using PclTest.exe or IntTest.exe.
For an installation in a PC with Linux operating system please follow these instructions:
•Download and unzip the “PCI SDK and Linux Driver” (file avpcisdk.zip) to a new folder
on your hard disk.
•Change to folder “Linux”. Check that there are no spaces (blanks) in the path to this
folder.
•The Linux driver is shipped as C source code and has to be compiled before first use.
•Open file “README” with a text editor and follow the instructions.

Operating Manual PCIe 3G, LV, L
Page 15
B5 Firmware Update
The PCIe and the PCI HD cards come with flash memory and can get firmware updates. That
is described in this chapter. With the PCI LV, PCI L, PCI V and PCI TS cards a chip change is
needed in to do that. Please contact Plura in this case.
Firmware updates require a computer with Windows or Linux operating system and the
PCLFlash program. You can download the latest version of the program from
https://plurainc.com.
Store the new firmware as a .tcf file on a local hard drive of your computer.
For Windows operating system please follow these steps:
1. Start the computer with the PCL card plugged in, log in as Administrator and install the
current driver (if not already done).
2. Execute PCLFlash on your computer. The program scans the computer for PCL cards and
gives a list of all devices found. Select the PCL card you with to update from the drop-
down list.
3. Open the .tcf file with “Browse”. A click to “Flash!” starts the update. The program
checks whether the new firmware matches the correct type of the device. In case there is
no match an error message appears: “Incompatible Flash Update File”. Update starts
automatically if everything is ok. Click the OK button at the end.
4. The Update is finished now. You may flash other cards or close PCLFlash.
For Linux operating system, open the “Linux” folder and follow the instructions in the
“README” file.

Operating Manual PCIe 3G, LV, L
Page 16
C Programming
C1 AVPCL32 Driver
Windows Driver Structure
The Windows driver for the PCIe 3G, LV, L consists of two parts:
•AvPcl32.dll is the interface for the user program. It implements functions like pclO-
pen(), pclClose(), pclGetTc(), etc.
•Avpcl6.sys is the Low-Level-driver. It processes the access to the PCI bus.
Driver Files
The following directories and files are in the file “avpci.zip”:
Root Directory
The root contains test programs that check the function of the PCIe 3G, LV, L as well as the
driver installation.
•PclTest.exe is a simple WIN32 console application, that displays the PCIe 3G, LV, L
Time Code. The source code is in the SDK in the „Samples“directory.
•IntTest.exe is a simple WIN32 console application, that displays the PCIe 3G, LV, L
Time Code. Opposite to PclTest.exe it uses interrupts. The source code is in the SDK in
the „Samples“directory.
“Driver” Directory
This directory and its sub directories contain all files needed for an installation of the PCIe 3G,
LV, L on a PC with Windows operating system.
•Avpcl6.inf is the description of the device driver for installation.
•Avpcl6.cat is the digital signature of avpcl6.inf for 32-bit Windows operating systems.
•Avpcl6.ntamd64.cat is the digital signature of avpcl6.inf for 64-bit Windows operating
systems.
•Install Driver.bat is a script to install the device driver. It checks if it is running on a
32-bit or 64-bit Windows operating system and, depending on the result, calls one of
the scripts in the i386 or amd64 directory.
•Pcl-Pci.inf is the description of the PCIe 3G, LV, L driver for installation.
•Pcl-Pci.cat is the digital signature of pcl-pci.inf for 32-bit Windows operating systems.
•Pcl-Pci.ntamd64.cat is the digital signature of pcl-pci.inf for 64-bit Windows operating
systems.
•Update Driver.bat is a script to update the driver. It checks if it is running on a 32-bit
or 64-bit Windows operating system and, depending on the result, calls one of the
scripts in the i386 or amd64 directory.

Operating Manual PCIe 3G, LV, L
Page 17
“Driver \ i386” Directory
This directory contains parts of the driver for 32-bit Windows operating systems.
•AvPcl32.dll is the interface between user programs and the Low-Level-driver av-
pcl6.sys. During installation it will be copied to the \Windows\system32 directory.
•Avpcl6.sys is the device driver. During installation it will be copied to the
\Windows\system32\driver directory.
•Difxapi.dll is used by wdreg_gui.exe and wdreg.exe.
•Install Driver.bat is a script to install the device driver. It calls wdreg_gui.exe with ap-
propriate parameters.
•Update Driver.bat is a script to update the driver. It calls wdreg_gui.exe with appro-
priate parameters.
•Wdreg_gui.exe is a program that installs device drivers.
•Wdreg.exe is the command line version of wdreg_gui.exe.
“Driver \ amd64” Directory
This directory contains parts of the driver for 64-bit Windows operating systems.
•AvPcl32.dll is the interface between 64-bit user programs and the Low-Level-driver
avpcl6.sys. During installation it will be copied to the \Windows\system32 directory.
•AvPcl64.dll is the interface between 32-bit user programs and the Low-Level-driver
avpcl6.sys, by using the WoW64 subsystem (Windows on Windows 64-bit). During in-
stallation it will be copied to the \Windows\sysWow64 directory and renamed to av-
pcl32.dll.
•Avpcl6.sys is the device driver. During installation it will be copied to the
\Windows\system32\driver directory.
•Difxapi.dll is used by wdreg_gui.exe and wdreg.exe.
•Install Driver.bat is a script to install the device driver. It calls wdreg_gui.exe with ap-
propriate parameters.
•Update Driver.bat is a script to update the driver. It calls wdreg_gui.exe with appro-
priate parameters.
•Wdreg_gui.exe is a program that installs device drivers.
•Wdreg.exe is the command line version of wdreg_gui.exe.
SDK Files and Linux Driver
The SDK files are located separate from the driver files in the file “avpcisdk.zip”. It contains
all necessary files to write PCIe 3G, LV, L user programs as well as the Linux driver.
Root Directory
•History.txt contains a brief history of the driver.

Operating Manual PCIe 3G, LV, L
Page 18
“Lib” Directory
This directory contains libraries shared by the sample code.
•AvPcl.h contains all declarations of the library AvPcl32.dll. The file is extensively
commented and serves as a reference for the user.
•AvPcl32.def is the module definition file to AvPcl32.dll.
“Lib \ i386” Directory
This directory contains libraries to write 32-bit application programs.
•AvPcl32.lib is the 32-bit version of the import library to AvPcl32.dll.
“Lib \ amd64” Directory
This directory contains libraries to write 64-bit application programs.
•AvPcl32.lib is the 64-bit version of the import library to AvPcl32.dll.
“Samples“ Directory
This directory contains the source code of simple PCIe 3G, LV, L test programs. They are writ-
ten as WIN32 console applications and explain the general use of the PCIe 3G, LV, L.
•AvPcl.h is a link to the file AvPcl.h in the directory above.
•PclTest.cpp is the source code of the test program PclTest.exe.
•IntTest.cpp is the source code of the test program IntTest.exe.
“Samples \ msdev_5” Directory
This directory contains workspace and project files for Microsoft Visual C++ 5.0.
•Sample.dsw is the workspace file for both sample programs.
•PclTest \ PclTest.dsp is the project file for the PclTest sample program.
•IntTest \ IntTest.dsp is the project file for the PclTest sample program.
“Samples \ msdev_2008” Directory
This directory contains workspace and project files for Microsoft Visual Studio 2008.
•Sample.sln is the solution file for both sample programs.
•PclTest \ PclTest.vcproj is the project file for the PclTest sample program.
•IntTest \ IntTest.vcproj is the project file for the PclTest sample program.
“Pascal” Directory
This directory contains the necessary files to access the PCIe 3G, LV, L with Turbo/Borland
Pascal or Delphi.
•AvPcl.pas contains the declarations for the access to AvPcl32.dll.
•PclTest.pas is a simple test program as WIN32 console application.

Operating Manual PCIe 3G, LV, L
Page 19
“Basic” Directory
This directory contains the information required to use the PCIe 3G, LV, L with Visual Basic.
•AvPcl32.vb contains all declarations for 32-Bit Visual-Basic-Programs.
“Linux” Directory
This directory contains the Linux driver in source code. Please read the file “README” for
additional information.
C2 Data access
This chapter explains the access to the PCIe 3G, LV, L on a hardware level. As far as one of
the supported operating systems is used, this information is not needed, since the board will
be accessed by the driver shipped with the board, as described in the chapter above.
Memory vs. I/O access
There are three blocks inserted in the memory resp. I/O address space by the PCIe 3G, LV, L:
Block
Memory or I/O
Size
Description
BAR0
Memory
PCI: 0x80, PCIe: 0x100
Local configuration register
BAR1
I/O
PCI: 0x80, PCIe: 0x100
Local configuration register
BAR2
Memory
0x100
PCIe 3G, LV, L register set
The local configuration registers are used to configure the PCI interface chips. They should
not be modified.
The PCI register set is mapped memory address space only.
Register set
Only the least significant byte of all the 64 long words is used. Therefore, only addresses,
which can be divided by four, can be accessed with one byte cycles. This results in a maxi-
mum of 64 bytes, but presently only 21 bytes are used.
The PCIe 3G, LV, L register set is defined as following:
PCIe 3G, LV, L
Register
Description
Offset
r/w
0x00
r
DATA0
Data from PCIe 3G, LV, L
0x04
r
DATA1
"
0x08
r
DATA2
"
0x0C
r
DATA3
"
0x10
r
DATA4
"
0x14
r
DATA5
"
0x18
r
DATA6
"
0x1C
r
DATA7
"

Operating Manual PCIe 3G, LV, L
Page 20
PCIe 3G, LV, L
Register
Description
0x20
r
DATA8
"
0x24
r
DATA9
"
0x28
r
DATAA
"
0x2C
r
INTFLGL
Interrupt flags L
0x30
r
CMDR
Command response
0x34
r
ACK
Acknowledge from PCL
0x38
w
CMD
Command to PCL
0x3C
w
CMDD0
Data to PCIe 3G, LV, L
0x40
w
CMDD1
"
0x44
w
CFG
PCL configuration
0x48
r
INTFLGH
Interrupt flags H
0x4C
w
INTACK
Interrupt acknowledge
0x7C
r
VERSION
PCIe 3G, LV, L chip version
Every register permits data transfers only in one direction, either reading or writing. A read
only register must not be written to, a write only register must not be read from.
Register
The registers in particular:
DATA0 to DATAA
The commands will return data via these registers.
INTFLGL
This register contains the interrupt flags. For every interrupt source the corresponding flag
indicates, that an interrupt condition has occurred (see also INTFLGH). The bits are coded as
following:
Bit
Hex
Interrupt Request
0
0x01
Mixed register
2
0x04
LTC register
3
0x08
VITC register
6
0x40
Odd video field (1st field)
7
0x80
Even video field (2nd field)
E.g. if bit ‘2’ is set, a new LTC has been read. It doesn’t matter if the interrupt request was
masked (enabled) or not (see command pclIntMask), i.e. if it initiated a hardware interrupt or
not. With that, it’s possible to use this register for polling mode.
Interrupt requests have to be acknowledged. This is done by reading the appropriate register
for Mixed-, LTC- and VITC-bits. The other bits can be acknowledged by the pclIntAck com-
mand.
CMDR
After servicing the command, PCIe 3G, LV, L returns the command number into this register.
With that it can be verified, that the last command has been executed correctly. With the