Dynamic Engineering SpaceWire BK User manual

DYNAMIC ENGINEERING
150 DuBois St., Suite B/C Santa Cruz, CA 95060
[phone]
https://www.dyneng.com
[email protected]
Est. 1988
User Manual
SpaceWire “BK” Model
Hardware Manual
Four-Channel SpaceWire Interface
PCIe, PCI, PC104p, PMC Versions
Manual Revision 03p4
PCI-SpaceWire
Corresponding Hardware: 10-2006-01(04)

PMC-SpaceWire
Corresponding Hardware: 10-2004-08(08,09)
PCIe-SpaceWire
Corresponding Hardware: 10-2018-18(01-03)

Corresponding Hardware: 10-2008-09(03-04)

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SpaceWireBK
PMC, PCIe, PCI, PC104p versions
Four-Channel SpaceWire Interface
Dynamic Engineering
150 DuBois St., Suite B/C
Santa Cruz, CA 95060
[phone]
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right to
make improvements or changes in the product
described in this document at any time and
without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
Connection of incompatible hardware is likely to
cause serious damage.
©2004-2023 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned by their respective manufacturers.
Revised 04/06/2023

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PRODUCT DESCRIPTION 8!
THEORY OF OPERATION 13!
PROGRAMMING 18!
Register Definitions 22!
SPWR_BASE_CNTL 22!
SPWR_USER_SWITCH 24!
SPWR_TIME_CNTRL 26!
SPWR_TIME_COUNT 27!
SPWR_PLL_FIFO 28!
SPWR_PLL_STATUS 28!
SPWR_CHAN_CNTRL_0-3 30!
SPWR_CHAN_STATUS_0-3 34!
SPWR_CHAN_FIFO_0-3 38!
SPWR_CHAN_WR_DMA_PNTR_0-3 38!
SPWR_CHAN_TX_FIFO_COUNT_0-3 40!
SPWR_CHAN_RD_DMA_PNTR_0-3 41!
SPWR_CHAN_RX_FIFO_COUNT_0-3 42!
SPWR_CHAN_TX_PKT_LEN_0-3 43!
SPWR_CHAN_RX_PKT_LEN_0-3 43!
SPWR_CHAN_TX_AMT_0-3 44!
SPWR_CHAN_RX_AFL_0-3 44!
SPWR_CHAN_CREDIT_AND_TIMECODE_STATUS_0-3 45!
SPWR_CHAN_RX_PKT_FF_FULL_CNTRL_0-3 46!
(CC)PMC (PCI) PN1 INTERFACE PIN ASSIGNMENT 48!
(CC)PMC (PCI) PN2 INTERFACE PIN ASSIGNMENT 49!
(CC)PMC PN4 USER INTERFACE PIN ASSIGNMENT 50!
APPLICATIONS GUIDE 51!
Interfacing 51!
CONSTRUCTION AND RELIABILITY 52!
Table of Contents

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THERMAL CONSIDERATIONS 53!
WARRANTY AND REPAIR 53!
Service Policy 53!
Out of Warranty Repairs 53!
For Service Contact: 53!
SPECIFICATIONS 54!
ORDER INFORMATION 56!

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FIGURE 1!SPACEWIRE BLOCK DIAGRAM 9!
FIGURE 2!SPACEWIRE DATA STROBE ENCODING 15!
FIGURE 3!SPACEWIRE ADDRESS MAP 21!
FIGURE 4!SPACEWIRE BASE CONTROL REGISTER 22!
FIGURE 5!SPACEWIRE USER SWITCH PORT 24!
FIGURE 6!SPACEWIRE TIME CONTROL REGISTER 26!
FIGURE 7!SPACEWIRE TIME COUNT REGISTER 27!
FIGURE 8!SPACEWIRE PLL DATA FIFO 28!
FIGURE 9!SPACEWIRE PLL STATUS REGISTER 28!
FIGURE 10!SPACEWIRE CHANNEL CONTROL REGISTER 30!
FIGURE 11!SPACEWIRE CHANNEL STATUS REGISTER 34!
FIGURE 12!SPACEWIRE CHANNEL RX/TX FIFO PORTS 38!
FIGURE 13!SPACEWIRE CHANNEL WRITE DMA POINTER PORT 38!
FIGURE 14!SPACEWIRE CHANNEL TX FIFO DATA COUNT PORT 40!
FIGURE 15!SPACEWIRE CHANNEL READ DMA POINTER PORT 41!
FIGURE 16!SPACEWIRE CHANNEL RX FIFO DATA COUNT PORT 42!
FIGURE 17!SPACEWIRE TX PACKET LENGTH FIFO PORTS 43!
FIGURE 18!SPACEWIRE RX PACKET LENGTH FIFO PORTS 43!
FIGURE 19!SPACEWIRE CHANNEL TX ALMOST EMPTY LEVEL REGISTER 44!
FIGURE 20!SPACEWIRE CHANNEL RX ALMOST FULL LEVEL REGISTER 44!
FIGURE 21! SPACEWIRE CHANNEL TIMECODE AND CREDIT STATUS REGISTER 45!
FIGURE 22 SPACEWIRE CHANNEL RX PACKET FIFO FULL CONTROL REGISTER 46!
FIGURE 23!MDM I/O CONNECTOR PINOUTS 47!
FIGURE 24!(CC)PMC-SPACEWIRE PN1 INTERFACE 48!
FIGURE 25!(CC)PMC-SPACEWIRE PN2 INTERFACE 49!
FIGURE 26!(CC)PMC-SPACEWIRE PN4 INTERFACE 50!
List of Figures

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Product Description
SpaceWire is part of the Dynamic Engineering family of modular I/O. This manual
describes the “BK” family of SpaceWire. Currently the PCIe, PCI, PC104p, and PMC
versions are available. Please refer to the K family manual for information about the
original memory map models.
Each has identical functionality with some variation in the IO connectors. Four ports are
supported per card, each with internal FIFO and separate DMA engines to support high
speed operation.
To receive the newer version covered in this manual add “-BK” to the part number.
K refers to the last planned updated to the original SpaceWire design. Beyond K “BK” is
the new version. Since the original PN is called out in client documentation and since
the BK version has an updated memory map Dynamic Engineering decided to require
the –BK addition to the PN to avoid mistakes in ordering.
External FIFO’s can be installed for additional storage capability. Options are available
to have the external FIFO attached to channel 0 RX and TX or channels 0 and 1 RX
only.
Revision 04 and later PCI-SpaceWire fab required for BK
Revision 08 and later PMC-SpaceWire fab required for BK
Revision 01 and later PCIe-SpaceWire fab required for BK
Additional features of BK models:
1. Larger - 16Kx32 FIFO’s for Rx and Tx data storage per channel
2. Updated PLL programming interface
3. Updated memory map to allow for additional features
4. Expanded Time Code time base - 32 bits instead of 20
5. Larger possible segment size for DMA.
6. 200 MHz operation 70C [PLL output is limited to 166 MHz for 85C]
7. Industrial Temperature components
8. Big Endian lane swapping for DMA transfers – selectable option in SW.

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The following diagram shows the “BK” SpaceWire configuration:
FIGURE 1 SPACEWIRE BLOCK DIAGRAM
Note: Not shown in diagram are the Packet FIFO’s which are 1K x 32 per channel per
direction [8] to store packet sizes for transmission or definitions from reception and the
PLL support FIFO’s and/programming engine.
PCI IF
FIFO A
16K x 32
FIFO B
16K x 32
SpaceWire
0
SpaceWire
1
Data Flow
Control
LVDS
buffers
MDM
LVDS
buffers
MDM
RX TX RX TX
FIFO C
16K x 32
SpaceWire
2
LVDS
buffers
MDM
RX TX
FPGA
Optional
FIFO
128Kx32
x2
x2
FIFO D
16K x 32
RX TX
SpaceWire
3
x2
x2
x2
2 2
4 4 44
22
4 4
22
LVDS
buffers
2 2
PN4
4 4

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The port 3 connector implementation varies depending on the format. The PMC version
can be configured with 3 MDM connectors, and have 1 channel on Pn4 or all 4 channels
routed to Pn4. In all cases, high speed, differential routing with controlled impedance
and matched lengths are used for the SpaceWire signaling. It is recommended to use a
SpaceWire compatible cable to interconnect your hardware. Dynamic Engineering has
several standard lengths of cable and offers custom lengths as well.
http://www.dyneng.com/SpaceWireCable.html
If you can use the SpaceWire hardware set but need an alternate protocol please
contact Dynamic Engineering. We will redesign the state machines and create a
custom interface protocol. See our web page for current protocols offered. Please
contact Dynamic Engineering with your custom application.
The SpaceWire protocol implemented provides Low Voltage Differential Signaling
(LVDS) data inputs and outputs. The transmit data rate is selected by a combination of
the programmed output frequencies of the PLL and the divisor values in the channel
control registers. The PLL is programmed via software over a serial I2C interface.
Transmit data rates are selectable from 2 Mbps to 200 Mbps. The receiver will
automatically adjust to the data rate seen.
The SpaceWire specification requires that the transmit frequency be 10 Mbps during the
link connection process. In order to accommodate this, the PLL frequency should be at
least close to a multiple of 10 MHz. Once the link protocol has established a
connection, the transmit speed will convert to the desired transmit rate specified in the
channel control registers.
Four independent SpaceWire channels are provided per card. Each SpaceWire
channel has two LVDS signal pairs for input and two LVDS signal pairs for output. The
electrical interface for SpaceWire is as specified in document ECSS-E-50-12C,
published by the European Cooperation for Space Standardization dated 31 July 2008.
Connections for the first three SpaceWire channels on the card are with MDM style
connectors as required by the specification. The fourth PMC channel is only available
on the PN4 connector. Any or all of the four channels can be routed to the PN4
connector (PMC only) rather than the MDM connectors by selecting which 0W resistors
are installed on the board.