Dynamic Engineering SpaceWire BK User manual

DYNAMIC ENGINEERING
150 DuBois St., Suite B/C Santa Cruz, CA 95060
[phone]
https://www.dyneng.com
[email protected]
Est. 1988
User Manual
SpaceWire “BK” Model
Hardware Manual
Four-Channel SpaceWire Interface
PCIe, PCI, PC104p, PMC Versions
Manual Revision 03p4
PCI-SpaceWire
Corresponding Hardware: 10-2006-01(04)

PMC-SpaceWire
Corresponding Hardware: 10-2004-08(08,09)
PCIe-SpaceWire
Corresponding Hardware: 10-2018-18(01-03)

Corresponding Hardware: 10-2008-09(03-04)

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SpaceWireBK
PMC, PCIe, PCI, PC104p versions
Four-Channel SpaceWire Interface
Dynamic Engineering
150 DuBois St., Suite B/C
Santa Cruz, CA 95060
[phone]
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right to
make improvements or changes in the product
described in this document at any time and
without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
Connection of incompatible hardware is likely to
cause serious damage.
©2004-2023 by Dynamic Engineering.
Other trademarks and registered trademarks are
owned by their respective manufacturers.
Revised 04/06/2023

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PRODUCT DESCRIPTION 8!
THEORY OF OPERATION 13!
PROGRAMMING 18!
Register Definitions 22!
SPWR_BASE_CNTL 22!
SPWR_USER_SWITCH 24!
SPWR_TIME_CNTRL 26!
SPWR_TIME_COUNT 27!
SPWR_PLL_FIFO 28!
SPWR_PLL_STATUS 28!
SPWR_CHAN_CNTRL_0-3 30!
SPWR_CHAN_STATUS_0-3 34!
SPWR_CHAN_FIFO_0-3 38!
SPWR_CHAN_WR_DMA_PNTR_0-3 38!
SPWR_CHAN_TX_FIFO_COUNT_0-3 40!
SPWR_CHAN_RD_DMA_PNTR_0-3 41!
SPWR_CHAN_RX_FIFO_COUNT_0-3 42!
SPWR_CHAN_TX_PKT_LEN_0-3 43!
SPWR_CHAN_RX_PKT_LEN_0-3 43!
SPWR_CHAN_TX_AMT_0-3 44!
SPWR_CHAN_RX_AFL_0-3 44!
SPWR_CHAN_CREDIT_AND_TIMECODE_STATUS_0-3 45!
SPWR_CHAN_RX_PKT_FF_FULL_CNTRL_0-3 46!
(CC)PMC (PCI) PN1 INTERFACE PIN ASSIGNMENT 48!
(CC)PMC (PCI) PN2 INTERFACE PIN ASSIGNMENT 49!
(CC)PMC PN4 USER INTERFACE PIN ASSIGNMENT 50!
APPLICATIONS GUIDE 51!
Interfacing 51!
CONSTRUCTION AND RELIABILITY 52!
Table of Contents

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THERMAL CONSIDERATIONS 53!
WARRANTY AND REPAIR 53!
Service Policy 53!
Out of Warranty Repairs 53!
For Service Contact: 53!
SPECIFICATIONS 54!
ORDER INFORMATION 56!

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FIGURE 1!SPACEWIRE BLOCK DIAGRAM 9!
FIGURE 2!SPACEWIRE DATA STROBE ENCODING 15!
FIGURE 3!SPACEWIRE ADDRESS MAP 21!
FIGURE 4!SPACEWIRE BASE CONTROL REGISTER 22!
FIGURE 5!SPACEWIRE USER SWITCH PORT 24!
FIGURE 6!SPACEWIRE TIME CONTROL REGISTER 26!
FIGURE 7!SPACEWIRE TIME COUNT REGISTER 27!
FIGURE 8!SPACEWIRE PLL DATA FIFO 28!
FIGURE 9!SPACEWIRE PLL STATUS REGISTER 28!
FIGURE 10!SPACEWIRE CHANNEL CONTROL REGISTER 30!
FIGURE 11!SPACEWIRE CHANNEL STATUS REGISTER 34!
FIGURE 12!SPACEWIRE CHANNEL RX/TX FIFO PORTS 38!
FIGURE 13!SPACEWIRE CHANNEL WRITE DMA POINTER PORT 38!
FIGURE 14!SPACEWIRE CHANNEL TX FIFO DATA COUNT PORT 40!
FIGURE 15!SPACEWIRE CHANNEL READ DMA POINTER PORT 41!
FIGURE 16!SPACEWIRE CHANNEL RX FIFO DATA COUNT PORT 42!
FIGURE 17!SPACEWIRE TX PACKET LENGTH FIFO PORTS 43!
FIGURE 18!SPACEWIRE RX PACKET LENGTH FIFO PORTS 43!
FIGURE 19!SPACEWIRE CHANNEL TX ALMOST EMPTY LEVEL REGISTER 44!
FIGURE 20!SPACEWIRE CHANNEL RX ALMOST FULL LEVEL REGISTER 44!
FIGURE 21! SPACEWIRE CHANNEL TIMECODE AND CREDIT STATUS REGISTER 45!
FIGURE 22 SPACEWIRE CHANNEL RX PACKET FIFO FULL CONTROL REGISTER 46!
FIGURE 23!MDM I/O CONNECTOR PINOUTS 47!
FIGURE 24!(CC)PMC-SPACEWIRE PN1 INTERFACE 48!
FIGURE 25!(CC)PMC-SPACEWIRE PN2 INTERFACE 49!
FIGURE 26!(CC)PMC-SPACEWIRE PN4 INTERFACE 50!
List of Figures

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Product Description
SpaceWire is part of the Dynamic Engineering family of modular I/O. This manual
describes the “BK” family of SpaceWire. Currently the PCIe, PCI, PC104p, and PMC
versions are available. Please refer to the K family manual for information about the
original memory map models.
Each has identical functionality with some variation in the IO connectors. Four ports are
supported per card, each with internal FIFO and separate DMA engines to support high
speed operation.
To receive the newer version covered in this manual add “-BK” to the part number.
K refers to the last planned updated to the original SpaceWire design. Beyond K “BK” is
the new version. Since the original PN is called out in client documentation and since
the BK version has an updated memory map Dynamic Engineering decided to require
the –BK addition to the PN to avoid mistakes in ordering.
External FIFO’s can be installed for additional storage capability. Options are available
to have the external FIFO attached to channel 0 RX and TX or channels 0 and 1 RX
only.
Revision 04 and later PCI-SpaceWire fab required for BK
Revision 08 and later PMC-SpaceWire fab required for BK
Revision 01 and later PCIe-SpaceWire fab required for BK
Additional features of BK models:
1. Larger - 16Kx32 FIFO’s for Rx and Tx data storage per channel
2. Updated PLL programming interface
3. Updated memory map to allow for additional features
4. Expanded Time Code time base - 32 bits instead of 20
5. Larger possible segment size for DMA.
6. 200 MHz operation 70C [PLL output is limited to 166 MHz for 85C]
7. Industrial Temperature components
8. Big Endian lane swapping for DMA transfers – selectable option in SW.

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The following diagram shows the “BK” SpaceWire configuration:
FIGURE 1 SPACEWIRE BLOCK DIAGRAM
Note: Not shown in diagram are the Packet FIFO’s which are 1K x 32 per channel per
direction [8] to store packet sizes for transmission or definitions from reception and the
PLL support FIFO’s and/programming engine.
PCI IF
FIFO A
16K x 32
FIFO B
16K x 32
SpaceWire
0
SpaceWire
1
Data Flow
Control
LVDS
buffers
MDM
LVDS
buffers
MDM
RX TX RX TX
FIFO C
16K x 32
SpaceWire
2
LVDS
buffers
MDM
RX TX
FPGA
Optional
FIFO
128Kx32
x2
x2
FIFO D
16K x 32
RX TX
SpaceWire
3
x2
x2
x2
2 2
4 4 44
22
4 4
22
LVDS
buffers
2 2
PN4
4 4

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The port 3 connector implementation varies depending on the format. The PMC version
can be configured with 3 MDM connectors, and have 1 channel on Pn4 or all 4 channels
routed to Pn4. In all cases, high speed, differential routing with controlled impedance
and matched lengths are used for the SpaceWire signaling. It is recommended to use a
SpaceWire compatible cable to interconnect your hardware. Dynamic Engineering has
several standard lengths of cable and offers custom lengths as well.
http://www.dyneng.com/SpaceWireCable.html
If you can use the SpaceWire hardware set but need an alternate protocol please
contact Dynamic Engineering. We will redesign the state machines and create a
custom interface protocol. See our web page for current protocols offered. Please
contact Dynamic Engineering with your custom application.
The SpaceWire protocol implemented provides Low Voltage Differential Signaling
(LVDS) data inputs and outputs. The transmit data rate is selected by a combination of
the programmed output frequencies of the PLL and the divisor values in the channel
control registers. The PLL is programmed via software over a serial I2C interface.
Transmit data rates are selectable from 2 Mbps to 200 Mbps. The receiver will
automatically adjust to the data rate seen.
The SpaceWire specification requires that the transmit frequency be 10 Mbps during the
link connection process. In order to accommodate this, the PLL frequency should be at
least close to a multiple of 10 MHz. Once the link protocol has established a
connection, the transmit speed will convert to the desired transmit rate specified in the
channel control registers.
Four independent SpaceWire channels are provided per card. Each SpaceWire
channel has two LVDS signal pairs for input and two LVDS signal pairs for output. The
electrical interface for SpaceWire is as specified in document ECSS-E-50-12C,
published by the European Cooperation for Space Standardization dated 31 July 2008.
Connections for the first three SpaceWire channels on the card are with MDM style
connectors as required by the specification. The fourth PMC channel is only available
on the PN4 connector. Any or all of the four channels can be routed to the PN4
connector (PMC only) rather than the MDM connectors by selecting which 0W resistors
are installed on the board.

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PMC-SpaceWire uses a 10 mm inter-board spacing for the front panel, standoffs, and
PMC connectors. The 10 mm height is the "standard" height and will work in most
systems with most carriers. If your carrier has non-standard connectors (height) to
mate with the PMC-SpaceWire, please let us know. We may be able to do a special
build with a different height connector to compensate.
All formats available and planned will have a common software interface allowing for
porting between systems. Dynamic Engineering offers drivers and reference software
for Windows®, Linux, and VxWorks.
Each SpaceWire channel is supported by two 16K by 32-bit FIFO’s. The TX FIFO’s
support long-word writes and the RX FIFO’s support long-word reads. For testing a
FIFO test bit in each channel control register enables the data to be routed from the TX
to the RX FIFO for a full 32-bit path. DMA operation is supported in both test and
operational modes.
Each SpaceWire receive channel can receive SpaceWire packets and store them in the
associated input FIFO’s. Each SpaceWire packet will be zero extended to align with 32-
bit long words. The actual number of bytes in the packet will be stored in the RX
packet-length FIFO [1Kx32] and the Data is stored in the 16K by 32-bit FIFO. Optional
external memory can be added to expand the receive data FIFO by an additional 512K
bytes on channel 0 and 1. The host can poll the FIFO flags or wait for the packet
received or RX almost full interrupts. The packet can be read over the PCI bus directly
from the RX data FIFO. Hardware implemented flow control uses the SpaceWire FCT
count to prevent overflow into either the Data or Packet FIFO’s automatically.
Each SpaceWire transmit channel has a separate 16K x 32-bit FIFO. The FIFO is
written as long words. The number of bytes to be transmitted is specified by writing a
byte count to the TX packet-length FIFO [1Kx32]. Provided the connection is
established, and the flow control from the destination side has authorized data transfer;
whenever TX data and packet-length values are written, the transmitter will send data.
A packet disable bit in the channel control register allows the interface to function
without packetizing the data. When in this mode the transmitter will send data as soon
as it is written to the TX FIFO. This essentially treats the data as one infinite length
packet. Optional external memory can be added to expand the transmit data FIFO by
an additional 512K bytes on port 0.
More on byte alignment: Transmit bytes are read from byte positions 0->3 byte lane
wise [7-0] first, [15-8] second, [23-16] third and [31-24] last and the bytes are
transmitted in this order. For message byte-counts not divisible by four, the last long-
word is read as described. Any unused bytes are considered padding with the next
message starting with the next FIFO long-word. For example, with 7 bytes to send, a

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word of 4 bytes will be read, then the lower 3 bytes will be read and sent and the 8th
byte will be dropped.
In the receive direction the action is similar. Bytes are written as long-words to the RX
FIFO. The first byte received is loaded into long-word byte 0 [7-0], then byte 1 [15-8],
byte 2 [23-16] and byte 3 [31-24]. Whenever a message does not have a complete
long-word to load and the end-of-packet character is received, zero-padding of the
unused upper-bytes will occur before the long-word is written to the FIFO.
The SpaceWire board supports various interrupts. An interrupt can be configured to
occur when the TX FIFO is almost empty, the RX FIFO is almost full, when a
SpaceWire packet has been transmitted or received, when a time-code character is
received or when an error has occurred. All interrupts are individually maskable, and a
channel master interrupt enable is provided to disable all interrupts on a channel
simultaneously. The current real-time status is also available from the FIFO’s making it
possible to operate in a polled mode.
For Command & Control situations direct read-write access to the FIFO’s makes sense.
The messages tend to be short and the added overhead of setting up DMA is not
justified. For data transfer DMA is recommended. Each channel has a separate
transmit and receive DMA engine for a total of 8 programmable units. The DMA
engines can be programmed for long transfers and handle scatter-gather requirements
automatically. With only 1 interrupt to deal with at the end of the transfer it is the lowest
overhead transfer method for medium and large transfers. Internal to the design is an
8-channel DMA arbiter which controls which port can access the PCI bus for DMA
operation. The arbiter operation is completely automatic.

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Theory of Operation
SpaceWire designs are for transferring data from one point to another using the
SpaceWire protocol as specified in document ECSS-E-50-12C, published by the
European Cooperation for Space Standardization dated 31 July 2008.
Continuous development in the SpaceWire community means fairly frequent updates for
new features. Generally new features can be added to a released card with a FLASH
update. New features are designed to allow for non-updated software to still function –
please set undefined bits to zero when programming to facilitate the migration path.
The BK series SpaceWire board(s) feature a Xilinx FPGA. The FPGA contains the PCI
interface, all of the registers, FIFO’s and protocol controlling elements of the SpaceWire
design. Only the transceivers and clock circuitry are external to the Xilinx device.
A logic block within the Xilinx controls the PCI interface to the host CPU. The
SpaceWire design requires one wait state for read or writes cycles to any address. The
wait states refer to the number of clocks after the PCI-core decode before the “terminate
with data” state is reached. Two additional clock periods account for the 1 clock delay
to decode the signals from the PCI bus and to convert the terminate-with-data state into
the TRDY signal.
Scatter-gather DMA is provided in this design. Once the physical address of the first
chaining descriptor is written to the DMA pointer register, the interface will read a 12-
byte block from this location. The first four bytes comprise a long-word indicating the
physical address of the first block of the IO buffer passed to the read or write call. The
next four bytes represent a long-word indicating the length of that block. The final four
bytes are a long-word indicating the physical address of the next chaining descriptor
along with two flag bits, in bit position 0 and 1. Bit zero is set to one if this descriptor is
the last in the chain. Bit one is set to one if the IO transfer is from the SpaceWire board
to host memory, and zero if the transfer is from memory to the board. These bits are
then replaced with zeros to determine the address of the next descriptor, if there is one.
NOTE: The direction bit (bit 1) must be set when the physical address of the first
chaining descriptor is written to the DMA pointer register (read DMAs only) or a
DMA error will result.
The eight DMA controllers obtain access to the PCI bus by asserting a request to the
DMA arbiter. Once a controller is granted PCI access, it keeps the bus until it drops its
request. At this point if another controller is requesting the bus, it will be granted
access. If multiple DMA controllers are asserting requests, the arbiter grants access in
a round-robin pattern, but no controller loses its grant until it drops its request.

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A controller will drop request when it reaches the end of a scatter-gather list entry or the
end of a DMA descriptor acquisition. It will also drop request when a transfer from the
device to memory is almost out of data, or when a transfer from memory to the device is
almost out of room to store the data, or if it has held the PCI bus for 1024 PCI clocks.
A DMA controller can be forced to drop request if it is preempted by another controller
that has an urgent need to transfer data. The ability to preempt other controllers is
enabled by the write/read DMA priority enable bits in the channel control registers and is
triggered by the transmit almost empty and receive almost full programmable FIFO
levels.
A retry counter is included in the DMA controllers. This six-bit counter is incremented
whenever the DMA controller initiates a PCI bus-cycle and is cleared whenever the
controller drops bus request or a data-word is successfully transferred. If the count
reaches the count stored in the base control register, the controller is forced to drop bus
request, which allows another controller to gain access. A stored count value of zero
disables this mechanism. The purpose of the retry counter is to prevent a DMA
controller from hanging-up the PCI bus when it is unable to move any data because of
some PCI bus or memory access problem.
Several state-machines within the FPGA control the link, FIFO’s, data transceivers, and
flow-control for each channel. The transmitter and receiver for each channel are
interdependent. The transmitter requires flow-control information from the receiver to
function and the receiver requires the transmitter to send flow-control tokens to regulate
the flow of received data.
In a typical transmit sequence the local receiver receives flow control tokens (FCT’s)
from the remote node. Each FCT authorizes the local transmitter to send eight
N(ormal)-Chars (a data-byte, End-Of-Packet token (EOP) or Error End-of-Packet (EEP))
back to the remote node. An up-down counter is used to keep track of the number of N-
Chars authorized, and the number of N-Chars that have been sent. Likewise, the local
transmitter sends FCT’s to the remote receiver node to enable that node’s transmitter to
send N-Chars to the local receiver. The number of outstanding FCT’s is based on the
amount of room available in the receive FIFO with an upper limit of 7 FCT’s (56 bytes).

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The transmitters will multiplex Time-Code characters, FCT characters, N-characters and
NULL characters (in that order of priority) onto the data stream to regulate the flow of
data in both directions. At the end of a transmitted packet, the transmitter will append
an EOP (or possibly an EEP if relaying a packet with an error) character to the message
stream to alert the receiver to the completion of the current packet.
The SpaceWire board uses Data-Strobe encoding where clock and data information are
sent on two paired serial links. Exactly one transition occurs in either the data line or
the strobe line at the end of each bit period allowing the clock to be recovered from the
data strobe pair. The timing is shown in figure 2.
FIGURE 2 SPACEWIRE DATA STROBE ENCODING
Before the transmitter can start operation, it must establish a link with the connected
node. When the link enable control bit is set, the connection state-machine resets the
NULL-detected latch and waits 6.4 microseconds before enabling the receiver. The
receiver then monitors SpaceWire link activity for 12.8 microseconds. If any link errors
or tokens other than NULL’s are seen during this period, the receiver is disabled and the
process starts over.
At this point the state-machine is in the ready state waiting for a start or auto-start
control bit to be set to move to the starting state. The start control bit causes the
transmitter to immediately begin sending NULL’s and the receiver to look for a NULL in
response, whereas the auto-start control bit causes the state-machine to wait for a
NULL to be received before transitioning to the starting state and sending NULL’s. If a
NULL is not seen within 12.8 microseconds while in the starting state, or if errors or
tokens other than NULL’s are seen, the transmitter and receiver are disabled and the
process starts over.

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When the transmitter has sent a NULL and the receiver has received a NULL character,
the transmitter sends an FCT character and the receiver looks for an FCT in return. If
this occurs, it means that the remote node has recognized the NULL and is ready to
connect. Once an FCT has been sent and received the link proceeds to the run state.
The transmit frequency then switches to the requested operational frequency from the
10 MHz connection frequency and Time-codes, FCT’s and N-chars (data or end-of-
packet tokens) can be sent to and from the node. (See figure 8-2: State diagram for
SpaceWire link interface on page 64 of the SpaceWire spec. ECSS-E-ST-50-12C)
The SpaceWire specification allows for a maximum of 56 bytes of credit (seven FCT’s)
to be outstanding at any time. For each eight bytes that are received, the receiver will
request the transmitter to send another FCT as long as sufficient buffer space exists to
accommodate the additional data. If the receiver receives a data byte when the
outstanding credit is zero, or if an FCT is received that causes the transmit credit to
exceed 56 bytes, a credit error has occurred.
The credit error is one of several error conditions that can disrupt the link connection.
The others include parity error, disconnect error and escape error. If any of these occur
a receive error and the offending error condition status will be latched, the link will
disconnect and after a delay, attempt to re-establish the connection.
The parity error occurs when the relevant bits of two successive characters do not
constitute odd parity (an odd number of ones). Parity coverage for SpaceWire is offset
from the character boundaries by two bits. Although each character begins with a parity
bit followed by a data control flag, these two bits are combined with the payload bits
from the previous character to determine the parity. The disconnect error occurs when
there is no activity on the strobe or data lines to the receiver for a period of 850
nanoseconds. The escape error occurs when an escape character is followed by
anything other than an FCT or a data character.
Beginning with Flash Rev 02 STD minor rev 8, 128 & 128RX minor rev5, a Receive
Packet FIFO control register was added to select when to back pressure the link to
prevent receive packet FIFO overflows from occurring. This improvement effectively
removes a SW race condition for small packets
1
. The register can be set to 0x3FF or
1
If the controlling processor does not keep up with the Packet received interrupts the Packet
FIFO would overflow and descriptors lost. The HW update adds the Packet FIFO status to
the FCT calculations to prevent overflow.

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0x000 to operate in legacy mode. A receive FIFO overflow will also cause a receive
error to be latched, but will not in itself cause a link disconnect.
If a receive data-packet is in progress when an error occurs, the receiver ceases writing
data to the receive data FIFO and writes the receive packet-length FIFO with the current
byte-count with the packet error bit set. If this packet fragment is to be relayed to a
remote node, it should be terminated with an EEP rather than an EOP.
If a transmit packet was in progress when the error occurred, the transmitter stops
sending data and attempts to purge the remainder of the current packet from the
transmit FIFO. Data must be read from the FIFO at the rate of 132 bytes per
microsecond, rather than using the FIFO reset, to avoid deleting data belonging to
subsequent packets.
A 30 microsecond delay is provided for this purpose, however, if the packet-length is
large or if all the packet data is not currently present in the transmit FIFO, the
transmitter will be unable to complete the data purge within the 30 microsecond period
and the link state-machine will go ahead and disable the receiver and transmitter in
preparation for reestablishing the link. The remote receiver that is receiving the data will
detect an error when the link is disabled, if it has not already, and will be aware that the
packet has been prematurely terminated.
This will clear the transmitter and receiver error state, but a transmitter purge error
status bit will be latched to alert the user of this error condition. The user can then read
the transmit packet-length FIFO count to determine how many packets are pending,
reset the transmit FIFO (which also clears the transmit packet-length FIFO) and perform
whatever error recovery is indicated.
See the SpaceWire specification for clarification or elaboration on any of these features.

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Programming
Programming the SpaceWire board requires only the ability to read and write data from
the host. The base address is determined during system configuration of the PCI bus.
The base address refers to the first user address for the slot in which the board is
installed. The VendorId = 0xDCBA. The CardId = 0x0055.
Depending on the software environment it may be necessary to set-up the system
software with the SpaceWire "registration" data. For example in WindowsNT there is a
system registry, which is used to identify the resident hardware.
If DMA is to be used it may be necessary to acquire a block of non-paged memory that
is accessible from the PCI bus in which to store chaining descriptor list entries. If the
Dynamic Engineering device drivers are used, the I/O channel driver will handle all the
DMA internal mechanics automatically.
In order to transfer data to another SpaceWire node, several steps must be performed.
First a physical connection must be established with the appropriate interface cable.
Then the PLL must be programmed to the desired clock configuration. The PLL is
connected to the Xilinx by an I2C serial bus. The PLL internal registers are loaded with
40 bytes of data that are derived from a .jed file that can be generated by the
CyberClock utility from Cypress semiconductor.
Reference: https://www.dyneng.com/_Download/Utilities/CyberClocks.zip . Select
CyClocksRT; the specific PLL part number is CY22393; and the external reference
clock frequency is 40 MHz. You can then specify frequencies for CLKA – CLKD which
supply the I/O reference clocks for channels 0 – 3 respectively. Click the Calculate
button and save the file. Newer versions of this utility may be available from
Infineon/Cypress.
The SpaceWire card is populated with industrial temperature components. If operating
in the Industrial temperature range be sure to set the proper temperature in the
CyberClocks software. The upper frequency of the PLL is somewhat limited in
Industrial temperature mode. If using for commercial temperature applications, select
the commercial temperature range setting to allow for higher operating frequencies.
A four-bit count field in each channel’s control register allows the I/O reference clock to
be divided by any integer value from 1 to 16 (count values 0 – 0xF) to yield the final
operational bit-rate. There is also a 5-bit initial count field for each channel in the base
control register that is used to divide the I/O reference clock in order to generate the ~10
Mbit per second connection rate. To allow the channels to achieve this connection rate,
the PLL should not be programmed to frequencies below 10 MHz and should be at least

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close to a multiple of 10 MHz.
Routines to program the PLL are included in the driver and UserApp code provided in
the engineering kit for the board. The driver will analyze the 40-byte PLL register field
to determine the requested frequencies and set the initial count values automatically
whenever the PLL is reprogrammed. If you are writing your own driver, contact
Dynamic Engineering and we can send you a file with code excerpts from our driver and
test software that cover each step of the process from parsing the .jed file to the low-
level bit manipulation of the I2C bus.
Next the link Enable bit and either the Start or Auto-start bit must be set in the channel
control register along with the desired operational clock divisor and any interrupt
enables that are to be monitored. When the link has been established as reported in
the channel status register, data may be written to the transmit FIFO using either single-
word writes or DMA. If the packet disable bit has been set, data will be sent as soon as
it is written, provided that the receiving node has authorized the transfer. In this mode
the data is treated as a single infinite-length packet.
If packetizing is not disabled, the data will not be sent until a packet-length has been
written to the SPWR_CHAN_TX_PKT_LEN FIFO. If the packet-length is not divisible by
four, the remainder of the last 32-bit FIFO word will be ignored and the next packet’s
data will begin with the next FIFO word. A packet-length must be written for each
packet to be sent, unless the constant packet-length control bit is set. If this bit is set,
the first packet-length read will be used continuously until either the data in the transmit
data FIFO is exhausted or the constant packet-length control bit is cleared.
Once the link has been established, the receiver will automatically adapt to the
frequency of the remote node’s transmitter. As data is received, a 32-bit data word will
be written to the receive FIFO for every four bytes that are received. When an end-of-
packet character is received, the remainder of the received data will be written to the
FIFO regardless of whether four bytes have been received (the unused bytes are
written as zeros) and the received packet-length (byte count) will be written to the
SPWR_CHAN_RX_PKT_LEN FIFO. The packet done bit will also be set and an
interrupt generated, if it has been enabled.

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Firmware Updates
Revision A: First release of BK. See feature table for new features. 8/14
Revision B1: Second release of BK. Updated for new FPGA pinout, external clock
recovery, PMC rear IO connector redefined to match ccPMC version. Add lane steering
for DMA in Big Endian systems. 3/16/15
Revision B2: minor update for better internal timing 12/15
Revision B2 : -128 original release based on B2 version standard product.
Revision B3-5: 9/2016 Fine tuning of FPGA terminations and timing based on new
layout with built in clock offset for improved hold time. Added minor revision field to
status.
ó Switch to numerical revisions
Revision 02p8 STD, 02p5 128 & 128RX: Implemented Receive Packet FIFO control
register and logic to each channel. Changed PCI bus access logic, FIFO Full logic, and
added timer to prevent bus lockups. Drivers changed TSI 384 bridge settings to prevent
cache coherency issue in certain system configurations. Added Channel Credit & Time
Code Status register to each channel.