Qei Epaq-9410 User manual

EPAQ-9410 Hardware Programming Reference 0.16

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ePAQ-9410

Hardware Programming

Reference 0.16

User’s Manual

October 2019

EPAQ-9410 Hardware Programming Reference 0.16

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ePAQ-9410 Hardware Programming Reference

NOTICE

The information in this document has been carefully checked and is believed to be

accurate. However, no responsibility is assumed or implied for inaccuracies. Further

more, QEI reserves the right to make changes to any products herein described to

improve reliability, function or design. QEI does not assume liability arising out of the

application or use of any product or circuit described herein; neither does it convey any

license under its patent rights nor the rights of others.

This manual and all data contained constitute proprietary information of QEI and shall

not be reproduced, copied or disclosed to others, or used as the basis for manufacture

without written consent of QEI.

45 Fadem Road

Springfield, NJ 07081

Phone: (973) 379-7400

Fax: (973) 379-2138

Web Site: www.qeiinc.com

EPAQ-9410 Hardware Programming Reference 0.16

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Revisions

Revision

Description

Date

A

Release to Production

October 2019

EPAQ-9410 Hardware Programming Reference 0.16

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Table of Contents

1Introduction................................................................................................................. 7

2References................................................................................................................... 7

3Blocks ......................................................................................................................... 7

3.1 Processor .............................................................................................................. 7

3.1.1 Memory Map ................................................................................................ 7

3.1.2 CPU GPIO Signal Usage.............................................................................. 7

3.1.3 Boot modes ................................................................................................... 9

3.2 Boot Modes .......................................................................................................... 9

3.2.1 CAPTURE and COMPARE....................................................................... 10

3.2.2 GPIO_BIT_BANG_OUT_CH[0,1]............................................................ 10

3.3 SDRAM.............................................................................................................. 11

3.4 NOR Flash.......................................................................................................... 11

3.5 NAND flash........................................................................................................ 11

3.6 SPI Flash ............................................................................................................ 12

3.7 Address Decoder CPLD..................................................................................... 12

3.7.1 Heartbeat Register....................................................................................... 13

3.7.2 L1 LED Register......................................................................................... 13

3.7.3 L2 LED Register......................................................................................... 14

3.7.4 L3 LED Register......................................................................................... 14

3.7.5 L4 LED Register......................................................................................... 14

3.7.6 SW10 High IP Address Register................................................................. 15

3.7.7 SW11 Low IP Address Register................................................................. 15

3.7.8 Option DIP Switch Register........................................................................ 15

3.7.9 AD CPLD Revision Register...................................................................... 16

3.8 QUAD UARTS.................................................................................................. 16

3.9 DUART.............................................................................................................. 17

3.10 Serial Routing CPLD...................................................................................... 17

3.10.1 IRIG-B Bus Register................................................................................... 18

3.10.2 IRIG_FIBER_TX Register ......................................................................... 18

3.10.3 IRIG-B_RS485_TXD Register................................................................... 19

3.10.4 IRIG-B_OUTPUT_TO_MICRO Register.................................................. 20

3.10.5 IRIG-B_MOD_OUT_EN_H Register........................................................ 20

3.10.6 CH8_RXD Register .................................................................................... 20

3.10.7 COM_EXP_IRIG-B Register .................................................................... 21

3.10.8 Telco [1,2] Mode Register.......................................................................... 21

3.10.9 Telco [1,2] Control Register....................................................................... 22

3.10.10 RS232 Port [1,2] Mode Register............................................................. 22

3.10.11 Bit-Bang CH [0,1] Register..................................................................... 23

3.10.12 Bit-Bang [0,1] RTS# Control Register.................................................... 23

3.10.13 DUART [A,B] Register........................................................................... 24

3.10.14 SR CPLD Revision 0 Register................................................................ 25

3.10.15 SR CPLD Revision 1 Register................................................................ 25

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3.11 LED Monitor CPLD....................................................................................... 25

3.11.1 CH_RXD Status Register ........................................................................... 27

3.11.2 CH_RXD2 Status Register ......................................................................... 27

3.11.3 CH_TXD Status Register............................................................................ 27

3.11.4 CH_TXD2 Status Register.......................................................................... 27

3.11.5 CH_RTS Status Register............................................................................. 28

3.12 System Reset & Watchdog Timer .................................................................. 28

3.12.1 Watchdog Normal Mode............................................................................. 28

3.12.2 Bypass Mode............................................................................................... 29

3.12.3 Power-On Restart........................................................................................ 29

3.13 I2C Busses and Devices ................................................................................. 30

4Manufacturing Software ........................................................................................... 30

4.1 Initial Programming via Serial Port ................................................................... 30

4.1.1 NOR Flash programming via TFTP Server................................................ 31

4.2 Install additional files......................................................................................... 32

5Bring-up procedure................................................................................................... 32

5.1 Equipment list .................................................................................................... 32

5.2 Visual inspection................................................................................................ 33

5.3 ePAQ-9410 Motherboard Initial Power Up....................................................... 34

5.4 ePAQ-9410 ProcFull Initial Power Up .............................................................. 35

5.5 Initial programming............................................................................................ 35

5.6 CPLD programming........................................................................................... 35

5.7 Modem ports ...................................................................................................... 36

5.7.1 CH 1 TX/CH 2 RX configuration............................................................... 36

5.7.2 CH 2 TX/CH 1 RX configuration............................................................... 36

5.7.3 LED’s test ................................................................................................... 37

5.8 RS232/RS485 Ports............................................................................................ 37

5.8.1 RS-232 test.................................................................................................. 37

5.8.2 RS-485 test.................................................................................................. 38

5.9 OPTIONS S1 DIP switches................................................................................ 39

5.10 Status LED’s................................................................................................... 39

5.11 IRIG/SERIAL................................................................................................. 40

5.12 SD CARD....................................................................................................... 41

5.13 USB MAINT .................................................................................................. 41

5.14 USB HOST..................................................................................................... 41

5.15 IRIG (RS-485)................................................................................................ 41

5.15.1 IRIG TX test ............................................................................................... 41

5.15.2 IRIG RX test ............................................................................................... 42

5.16 RS-422............................................................................................................ 42

5.16.1 PORT 9 (J7A) external loopback test......................................................... 42

5.16.2 PORT 10 (J7D) external loopback test....................................................... 43

5.16.3 PORT 11 J7C external loopback test.......................................................... 44

5.17 RS-232............................................................................................................ 44

5.18 IRIG COAX.................................................................................................... 46

5.19 100BaseFX Ports............................................................................................ 46

5.20 10/100BaseTX Ethernet Ports........................................................................ 46

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5.21 RTC ................................................................................................................ 47

5.22 Supercap ......................................................................................................... 47

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Revision History

Revision

Date

Author

Description

0.01

1/7/2012

KE

Initial revision

0.02

1/19/2012

KE

Updated CPLD sections

0.03

1/24/2012

KS

Added CPU GPIO Signal Usage section

0.04

1/24/12

KE

Updated CPLD sections, added REVISION registers

0.05

2/9/12

KE

Added descriptions for boot modes, watch-dog and

initial programming via serial port

0.07

2/27/12

KE

Updated CPLD registers and versions

added I2C section

0.08

3/1/12

KE

updated SR CPLD section

0.09

3/1/12

KE

updated AD and LM CPLD sections

0.10

3/7/12

KE

updated SR CPLD section

0.11

3/20/12

KE

added “boot modes”, “CAPTURE and COMPARE”,

GPIO_BIT_BANG_OUT_CH[0,1]

0.12

10/18/12

KE

updated NAND flash section

0.13

10/19/12

KE

bring-up procedure WIP

0.16

10/3/19

UL

CPLD/USB/Ethernet enables

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1 Introduction

This document describes hardware functionality of ePAQ-9410 ProcFull board Rev B

and ePAQ-9410 Mother Board Rev B.

2 References

1. ePAQ-9410/9420 Multifunction Gateway Functional Specification, 05-055104-

001 ePAQ-94XX MultiFunction Gateway Spec Rev H13.pdf, REV.H13,

6/27/2011

2. eXP-9430 Comm Port Expander Functional Specification, 05-055111-001 eXP-

9430 Comm Port Expander Rev. E.pdf, Rev.E

3 Blocks

3.1 Processor

3.1.1 Memory Map

Start

End

Size

Description

0xA000_0000

0xA3FF_FFFF

64Mbytes

NOR Flash 1 on

CS0

0xA400_0000

0xA7FF_FFFF

64Mbytes

CS0, (aliased to

NOR Flash 1?)

0xA800_0000

0xABFF_FFFF

64Mbytes

NOR Flash 2

0xAC00_0000

0xAFFF_FFFF

64Mbytes

CS1, (aliased to

NOR Flash 2?)

0xB400_0000

0xB5FF_FFFF

32 MBytes

WEIM CS4,

Address Decode

CPLD

3.1.2 CPU GPIO Signal Usage

Pin #

Signal Name

Used On

I/O

Comment

L20

GPIO_1_0

ProcFull

Drives Diag LED 0, high active

L16

GPIO_1_1

MotherBoard

Not used

M19

GPIO_1_2

MotherBoard

Drives Diag LED 2, high active

M17

GPIO_1_3

MotherBoard

Drives Diag LED 3, high active

V12

CAPTURE_GPIO1-4

MotherBoard

Goes to Serial Routing CPLD

J4

GPIO_1_7

ProcFull

Drives Diag LED 4, high active

J1

GPIO_1_8

ProcFull

Drives Diag LED 5, high active

J5

GPIO_1_9

MotherBoard

QUART U1 INTA

H1

GPIO_1_14

ProcFull

Drives Diag LED 6, high active

G4

GPIO_1_15

ProcFull

Drives Diag LED 7, high active

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W15

GPIO_1_28

MotherBoard

Provisional for Ethernet

switch SCL

Y15

GPIO_1_31

MotherBoard

Provisional for Ethernet

switch SDA

F20

GPIO_2_0

MotherBoard

QUART U1 INTB

G18

GPIO_2_1

MotherBoard

QUART U1 INTC

FG17

GPIO_2_2

MotherBoard

QUART U1 INTD

G16

GPIO_2_3

MotherBoard

QUART U7 INTA

G19

GPIO_2_4

MotherBoard

QUART U7 INTB

H16

GPIO_2_5

MotherBoard

QUART U7 INTC

H18

GPIO_2_6

MotherBoard

QUART U7 INTD

G20

GPIO_2_7

CommExpander

UART1 IRQ

H17

GPIO_2_8

CommExpander

UART2 IRQ

H19

GPIO_2_9

CommExpander

UART3 IRQ

H20

GPIO_2_10

CommExpander

UART4 IRQ

V4

GPIO_2_19

MotherBoard

O

GPIO_MICRO_IRIG_IN, IRIG-

B source for SR CPLD

Y3

GPIO_2_20

MotherBoard

I

IRIG-B_OUTPUT_TO_MICRO,

IRIG-B input to uP

W1

GPIO_2_27

MotherBoard

Not used

T4

GPIO_2_28

MotherBoard

SD_CARD_DET#

V2

GPIO_2_29

CommExpander

COMM_EXP_RESET#

T5

GPIO_2_30

MotherBoard

GPIO_BIT_BANG_OUT_CH1

T3

GPIO_2_31

MotherBoard

GPIO_BIT_BANG_OUT_CH0

R4

GPIO_3_0

ProcFull

Not used

V1

GPIO_3_1

MotherBoard

Not used

R5

GPIO_3_2

MotherBoard

Not used

W13

MICRO_SD_CARD_DETECT

ProcFull

Goes to U21 & U24 on PF

board

Y13

GPIO_3_4

MotherBoard

Not used

T12

COMPARE_GPIO1-5

MotherBoard

Goes to Serial Routing CPLD

W12

GPIO_3_5

MotherBoard

Not used

W7

GPIO_3_14

MotherBoard

DUART IRQ#, Pulled Up

U7

GPIO_3_15

MotherBoard

Not used, pulled up

L15

GPIO_3_31

ProcFull

Drives Diag LED 1, high active

L5

GP_SPARE_0

ProcFull

Not used

K3

GP_SPARE_1

MotherBoard

Provisional for JTAG-TDO

L17

GP_SPARE_2

MotherBoard

Provisional for JTAG-TDI

K5

GP_SPARE_3

MotherBoard

Provisional for JTAG-TCLK

M18

GP_SPARE_4

MotherBoard

Provisional for JTAG-TMS

T7

GP_SPARE_5

ProcFull

Not used

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3.1.3 Boot modes

Boot related pins:

Pad

Pad Name

Boot function

W10

BOOT_MODE0

switch

[1,0] = 00 –internal ROM boot

[1,0] = 10 –Direct external NOR boot

[1,0] = 10 - BT_MEM_CTRL[1:0] = b11:

[1:0] = 11 –serial bootloader

U9

BOOT_MODE1

switch

U15

CSI_D8

BT_MEM_CTRL[0]

switch

when BOOT_MODE[1:0] = b10:

[1:0] = b00 - Direct external NOR boot

[1:0] = b11 - Startup mode/JTAG debug

when BOOT_MODE[1:0] = b00:

[1:0] = b11 - 11 Expansion device (SD, eSD,

MMC, eMMC, or serial ROM)

W17

CSI_D9

BT_MEM_CTRL[1]

switch

T15

CSI_D11

BT_MEM_TYPE[1]

100/10K

when BT_MEM_CTRL[1:0] == b11:

[1:0] = b00 SD, MMC, eMMC, or eSD

V16

CSI_D10

BT_MEM_TYPE[0]

100/10K

W16

CSI_D12

BT_PAGE_SIZE[0]

100/10K

only used when BT_MEM_CTRL[1:0] = b01

(NAND boot)

not used in our design

V15

CSI_D13

BT_PAGE_SIZE[1]

100/10K

U14

CSI_D14

BT_ECC_SEL

100/10K

If the bootable device is MMC then:

0 Don't use eMMC fast boot mode.

1 Use eMMC fast boot mode.

(not relevant?)

T14

CSI_VSYNC

BT_BUS_WIDTH

100/10K

BT_MEM_CTL[1:0] = 00

0 16 bit

1 Reserved

however this refers to functionality during

internal boot mode only which we are not

using

V14

CSI_HSYNC

BT_USB_SRC[1]

100/10K

not used, should be recycled as GPIO

Y16

CSI_D15

BT_USB_SRC[0]

100/10K

3.2 Boot Modes

The ePAQ-9410 system supports four boot modes as follows:

Boot mode

BOOT_MODE[1:0]

BT_MEM_CTRL[1:0]

BT_MEM_TYPE[1:0]

NOR FLASH

10

00

xx

Serial Download

11

xx

SD Card

00

11

00

Startup/JTAG

10

11

xx

The NOR FLASH boot mode is the normal, field mode of operation. The Serial

Download boot mode is for initial programming of the NOR FLASH. The SD Card boot

mode is for system initialization, configuration and updates. The Startup/JTAG boot

mode is intended for initial R&D development support and is not currently being used.

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These boot modes are among many possible boot modes and configurations supported by

IMX357 CPU. The ePAQ-9410 design only supports the boot modes listed above. The

supported boot modes are selected by the configuration switch U1.

NOR FLASH Boot Mode

Signal Logic Level Switch Position

BOOT_MODE0 0 U1 pole 7 = closed (on)

BOOT_MODE1 1 U1 pole 3 = closed (on)

MEM_CTL0 0 U1 pole 4 = open (off)

MEM_CTL1 0 U1 pole 5 = open (off)

Serial Download Boot Mode

Signal Logic Level Switch Position

BOOT_MODE0 1 U1 pole 7 = open (off)

BOOT_MODE1 1 U1 pole 3 = closed (on)

MEM_CTL0 0 U1 pole 4 = open (off)

MEM_CTL1 0 U1 pole 5 = open (off)

Startup/JTAG Boot Mode

Signal Logic Level Switch Position

BOOT_MODE0 1 U1 pole 7 = open (off)

BOOT_MODE1 0 U1 pole 3 = open (off)

MEM_CTL0 0 U1 pole 4 = open (off)

MEM_CTL1 0 U1 pole 5 = open (off)

This boot mode will not execute the IMX357’s internal boot ROM. A compatible JTAG

emulator may be used to load and execute application code.

3.2.1 CAPTURE and COMPARE

These signals are intended to be used for the two receive lines of the bit-bang

interface. Although one is labeled "CAPTURE" and the other "COMPARE", in fact,

both of these would potentially be used as capture inputs.

The idea is that for the Bit-Bang receiver, we have the option of using the

input capture hardware to give us an accurate time-of-transition on the

received signal (which then can be translated into bit times).

The processor pads CAPTURE and COMPARE can also be used as GPIO’s:

Pad

Pad name

Function

GPIO

V12

CAPTURE

BB0_RXD

GPIO1_4

T12

COMPARE

BB1_RXD

GPIO1_5

3.2.2 GPIO_BIT_BANG_OUT_CH[0,1]

These signals are intended to be used for the two transmit lines of the bit-bang

interface as follows:

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Pad

Pad name

Function

GPIO

T3

ATA_DMARQ

BB0_TXD

GPIO2_31

T5

ATA_BUFF_EN

BB1_RXD

GPIO2_30

3.3 SDRAM

LowPowerDDR1 SDRAM, 64Meg by 16 bits, 1.8 Volts, Micron MT46H64M16LFBF-

6 IT:B MT46H64M16LFBF-6 IT:B -40C TO 85C 10-057931-001 60-VFBGA

MT46H64M16LF –16 Meg x 16 x 4 banks (=64 Meg x 16 = 128 MBytes)

From the processor perspective, the SDRAM is arranged as two banks of 32-bit SDRAM,

256 MBytes each. 0x80000000 and 0x90000000 are the starting addresses of the memory

banks. There is no gap between the banks and the SDRAM can be viewed as a

continuous region of 512 MBytes

During normal, NOR flash boot, the SDRAM and the SDRAM memory controller is

initialized by u-boot bootloader during early stages of the boot process.

board/pcm043/lowlevel_init.S

u-boot passes SDRAM memory layout to Linux kernel via memory based arguments

(ATAG_MEM method). Observe messages during u-boot to confirm layout:

## Transferring control to Linux (at address 0x80008000) ...

Memory: 80000000[10000000]

Memory: 90000000[10000000]

Starting kernel ...

Potentially, there is an advantage for Linux to work with one continuous memory region

instead of two memory regions. Not sure if Linux is smart enough to figure out if the

memory regions are adjacent.

3.4 NOR Flash

We have 2 x S29GL512P (512 Megabit) at CS0# and CS1#

starting at 0xA0000000 and 0xA8000000, respectively

512 Megabit = 64 MBytes

3.5 NAND flash

2 x MT29F4G08ABADAWP-IT_D

2 x 4Gb for 512MBytes total

The hardware design supports a stuffing option when a more dense flash part could be

placed into U6, for example MT29F16G08AJADAWP, at the expense of second NOR

flash chip in U13. This configuration was not thoroughly reviewed or tested.

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3.6 SPI Flash

3 x SST25VF064C –64 Mbit SPI Serial Dual I/O Flash.

3 x 8MBytes

3.7 Address Decoder CPLD

0xB400_0000-0xB5FF_FFFF 32 Mbytes WEIM CS4 for AD CPLD

A0-A8, 512 byte chunks

A16-A20, 32 chunks of 64K

Start

End

Size

Description

0xB400_0000

0xB400_01FF

512 bytes

QUAD UARTs, DUART

0xB401_0000

0xB401_01FF

512 bytes

Address Decode CPLD_CS_1

0xB402_0000

0xB402_001F

32 bytes

Serial Routing CPLD

0xB403_0000

0xB403_01FF

512 bytes

Address Decode CPLD

0xB404_0000

0xB405_FFFF

128 KBytes

NVRAM_CS#, NVRAM

0xB406_0000

0xB406_FFFF

64 KBytes

reserved for future use

0xB407_0000

0xB407_FFFF

64 KBytes

reserved for future use

0xB408_0000

0xB408_00FF

256 Bytes

LED Monitor CPLD

0xB409_0000

reserved for future use

0xB40A_0000

reserved for future use

0xB40B_0000

reserved for future use

0xB40C_0000

reserved for future use

0xB40D_0000

reserved for future use

0xB40E_0000

reserved for future use

0xB40F_0000

reserved for future use

0xB410_0000

reserved for future use

…

0xB41F_0000

reserved for future use

Register summary at 0xB401_0000

Offset

Register

Name

Access

Reset

0x0B

RS232 Port 1 PTT

CH10_PTT_H

write-only

0x00

0x0C

RS232 Port 2 PTT

CH11_PTT_H

write-only

0x00

0x0D

DISABLE_COMM_EXP_H

write-only

0x0E

COM_EXP_BRD_DETECT#

read-only

0x0F

Heartbeat LED

HEARTBEAT_L

write-only

0x01

0x10

L1 LED

LED_1

write-only

0x01

0x11

L2 LED

LED_2

write-only

0x01

0x12

L3 LED

LED_3

write-only

0x01

0x13

L4 LED

LED_4

write-only

0x01

0x14

DISABLE_2_H

write-only

0x00

0x15

DISABLE_3_H

write-only

0x00

0x16

MSTR_RS422_TXEN

write-only

0x00

0x17

BIT_BANG_RS232_ENA

write-only

0x00

0x18

AD CPLD Revision

AD_REVISION

read-only

0x07

0x19

ETHER_CONFIG_MODE

write-only

0x1A

ETHERNET_CPLD_RESET#

write-only

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0x1B

reserved

0x1C

reserved

0x1D

reserved

0x1E

reserved

0x1F

ULPI_VBUS

write-only

0x20

USB_CPLD_RESET#

write-only

Register summary at 0xB403_0000

Offset

Register

Name

Access

Reset

0x00

SW10 High Byte of IP address

IP_CSR_1

read-only

-

0x01

SW11 Low Byte of IP address

IP_CSR_2

read-only

--

0x12

Option DIP Switch

OPTION_DIP_SWITCH

read-only

-

0x18

AD CPLD Revision

AD_REVISION

read-only

0x01

TP107

Ethernet Port Chip

Forced LOW always to

enable serial programming

None

0x0

3.7.1 Heartbeat Register

Register Name: HEARTBEAT_L

Address: 0xB401_000F

Access type: write-only

7

6

5

4

3

2

1

0

LED_OFF

Heartbeat LED is the top row left column LED in the 2 rows by 3 columns LED array

located on the ePAQ-9410 front panel. It is right above the Power LED which is bottom-

left.

LED_OFF: LED control

0 = LED on

1 = LED off

3.7.2 L1 LED Register

Register Name: LED_1

Address: 0xB401_0010

Access type: write-only

L1 LED is the top row middle column LED in the 2 rows by 3 columns LED array

located on the ePAQ-9410 front panel.

7

6

5

4

3

2

1

0

LED_OFF

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LED_OFF: LED control

0 = LED on

1 = LED off

3.7.3 L2 LED Register

Register Name: LED_2

Address: 0xB401_0011

Access type: write-only

L2 LED is the top row right column LED in the 2 rows by 3 columns LED array located

on the ePAQ-9410 front panel.

7

6

5

4

3

2

1

0

LED_OFF

LED_OFF: LED control

0 = LED on

1 = LED off

3.7.4 L3 LED Register

Register Name: LED_3

Address: 0xB401_0012

Access type: write-only

L3 LED is the bottom row middle column LED in the 2 rows by 3 columns LED array

located on the ePAQ-9410 front panel.

7

6

5

4

3

2

1

0

LED_OFF

LED_OFF: LED control

0 = LED on

1 = LED off

3.7.5 L4 LED Register

Register Name: LED_4

Address: 0xB401_0013

Access type: write-only

L4 LED is the bottom row right column LED in the 2 rows by 3 columns LED array

located on the ePAQ-9410 front panel.

7

6

5

4

3

2

1

0

LED_OFF

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LED_OFF: LED control

0 = LED on

1 = LED off

3.7.6 SW10 High IP Address Register

Register Name: IP_CSR_1

Address: 0xB403_0000

Access type: read-only

Refers to SW10, eight DIP switches. front-to-back: SW10-1 … SW10-8.

7

6

5

4

3

2

1

0

SW10_8

SW10_7

SW10_6

SW10_5

SW10_4

SW10_3

SW10_2

SW10_1

SW10_[1..8]: DIP switch SW10-[1..8]

0 = ON (left)

1 = OFF (right)

3.7.7 SW11 Low IP Address Register

Register Name: IP_CSR_2

Address: 0xB403_0001

Access type: read-only

Refers to SW11, eight DIP switches. SW10 is in front SW11.

7

6

5

4

3

2

1

0

SW11_8

SW11_7

SW11_6

SW11_5

SW11_4

SW11_3

SW11_2

SW11_1

SW11_[1..8]: DIP switch SW11_[1..8]

0 = ON (left)

1 = OFF (right)

3.7.8 Option DIP Switch Register

Register Name: OPTION_DIP_SWITCH

Address: 0xB403_0012

Access type: read-only

Refers to SW1, four Front Panel Option DIP switches. Left to right: SW1-1, SW1-2,

SW1-3, SW1-4. “ON” is down.

7

6

5

4

3

2

1

0

FP_DIP_SW4

FP_DIP_SW3

FP_DIP_SW2

FP_DIP_SW1

FP_DIP_SW1: DIP switch SW1-1

0 = ON (down)

1 = OFF (up)

EPAQ-9410 Hardware Programming Reference 0.16

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FP_DIP_SW2: DIP switch SW1-2

0 = ON (down)

1 = OFF (up)

FP_DIP_SW3: DIP switch SW1-3

0 = ON (down)

1 = OFF (up)

FP_DIP_SW4: DIP switch SW1-4

0 = ON (down)

1 = OFF (up)

3.7.9 AD CPLD Revision Register

Register Name: AD_REVISION

Address: 0xB403_0018

Access type: read-only

7

6

5

4

3

2

1

0

AD_REVISION

AD_REVISION: AD CPLD Revision

3.8 QUAD UARTS

Two SC16C754B QUAD UARTS.

The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with

64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s

(3.3 V and 5 V).

QUAD UART 1 (U1), controls RS-232-485_PORT1, RS-232-485_PORT2, RS-232-

485_PORT3 and RS-232-485_PORT4 ports.

QUAD UART 2 (U7), controls CH7, CH8, CH9 and COM_EXP ports.

Start

End

Size

Description

0xB400_0000

0xB400_0007

8 Bytes

QUAD UART 1, Channel A

0xB400_0008

0xB400_000F

8 Bytes

QUAD UART 1, Channel B

0xB400_0010

0xB400_0017

8 Bytes

QUAD UART 1, Channel C

0xB400_0018

0xB400_001F

8 Bytes

QUAD UART 1, Channel D

0xB400_0020

0xB400_0027

8 Bytes

QUAD UART 2, Channel A

0xB400_0028

0xB400_002F

8 Bytes

QUAD UART 2, Channel B

0xB400_0030

0xB400_0037

8 Bytes

QUAD UART 2, Channel C

0xB400_0038

0xB400_003F

8 Bytes

QUAD UART 2, Channel D

Under Linux, the individual channels of QUAD UART are mapped to devices as follows:

Channel

Linux name

QUAD UART 1, Channel A

/dev/sttyS0

GPIO_1_9

EPAQ-9410 Hardware Programming Reference 0.16

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QUAD UART 1, Channel B

/dev/sttyS1

GPIO_2_0

QUAD UART 1, Channel C

/dev/sttyS2

GPIO_2_1

QUAD UART 1, Channel D

/dev/sttyS3

GPIO_2_2

QUAD UART 2, Channel A

/dev/sttyS4

GPIO_2_3

QUAD UART 2, Channel B

/dev/sttyS5

GPIO_2_4

QUAD UART 2, Channel C

/dev/sttyS6

GPIO_2_5

QUAD UART 2, Channel D

/dev/sttyS7

GPIO_2_6

3.9 DUART

SC28L92A1B

Configured for Intel bus format

CH10_TXCLK_OUT –OP2

CH10_RXCLK_IN - IP4

CH11_TXCLK_OUT –OP3

CH11_RXCLK_IN - IP6

3.10Serial Routing CPLD

Base address is at 0xB402_0000, 4-bit wide data bus, 5 address bits.

Offset

Register

Name

Access

Reset

0x00

IRIG-B Bus

IRIG_SIGNAL_BUS_SEL

write-only

0x0

0x01

IRIG_FIBER_TX

IRIG_FIBER_TX_SEL

write-only

0x0

0x02

IRIG-B_RS485_TXD

IRIG_B_RS485_TXD_SEL

write-only

0x0

0x03

IRIG-B_OUTPUT_TO_MICRO

IRIG_B_OUTPUT_TO_MICRO_SEL

write-only

0x0

0x04

unused

0x05

IRIG-B_MOD_OUT_EN_H

IRIG_B_MOD_OUT_EN_H

write-only

0x0

0x06

CH8_RXD

CH8_RXD_SEL

write-only

0x0

0x07

COM_EXP_IRIG-B

COM_EXP_IRIG_B_SEL

write-only

0x0

0x08

Telco 1 Mode

CH14_SEL

write-only

0x0

0x09

Telco 1 Control

CH14_CTRL

read-write

0x0A

Telco 2 Mode

CH15_SEL

write-only

0x0

0x0B

Telco 2 Control

CH15_CTRL

read-write

0x0C

RS232 Port 1 Mode

CH10_SEL

write-only

0x00

0x0D

RS232 Port 2 Mode

CH11_SEL

write-only

0x00

0x0E

Bit-Bang CH 0

BB0_SEL

0x0F

Bit-Bang CH 1

BB1_SEL

0x10

Bit-Bang 0 RTS# Control

BB0_RTS_CTRL

write-only

0x00

0x11

Bit-Bang 1 RTS# Control

BB1_RTS_CTRL

write-only

0x00

0x12

DUART A

DUART_CHA_SEL

write-only

0x00

0x13

DUART B

DUART_CHB_SEL

write-only

0x00

0x14

reserved

0x15

reserved

0x16

reserved

0x17

reserved

0x18

SR CPLD Revision 0

SR_REVISION_0

read-only

0x8

0x19

SR CPLD Revision 1

SR_REVISION_1

read-only

0x0

0x1A

reserved

0x1B

reserved

0x1C

reserved

0x1D

reserved

0x1E

reserved

EPAQ-9410 Hardware Programming Reference 0.16

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0x1F

reserved

3.10.1 IRIG-B Bus Register

Register Name: IRIG_SIGNAL_BUS_SEL

Address: 0xB402_0000

Access type: write-only

3

2

1

0

IRIG_SIGNAL_BUS_SEL

The IRIG_SIGNAL_BUS_SEL register controls the configuration of the

IRIG_SIGNAL_BUS signal internal to the SR CPLD. The external IRIG_B-RS-485

signal is always driven by the internal IRIG_SIGNAL_BUS signal and can be configured

to be transmitted on RS-232-485_PORT[1..4] ports connected to QUAD UART 1. See

CH[1..4]_CFG registers of LED Monitor CPLD.

The table below summarizes supported values for IRIG_SIGNAL_BUS_SEL register.

Value

Description

0x0

0, IRIG_SIGNAL_BUS signal is driven low

0x1

IRIG_SIGNAL_BUS = IRIG_FIBER_RX_NI

0x2

IRIG_SIGNAL_BUS = ~IRIG_FIBER_RX_NI

0x3

IRIG_SIGNAL_BUS = IRIG_COAX_IN

0x4

IRIG_SIGNAL_BUS = IRIG_B_RS485_RXD

0x5

IRIG_SIGNAL_BUS = ~IRIG_B_RS485_RXD

0x6

IRIG_SIGNAL_BUS = GPIO_MICRO_IRIG_IN, IRIG_SIGNAL_BUS is

controlled by processor’s GPIO 2-19

0x7

IRIG_SIGNAL_BUS = CH8_TXD, QUAD UART 2, CH B TDX signal

0x8

IRIG_SIGNAL_BUS = 1, IRIG_SIGNAL_BUS is driven high

0x9-0xF

reserved for future use, IRIG_SIGNAL_BUS is driven low

3.10.2 IRIG_FIBER_TX Register

Register Name: IRIG_FIBER_TX_SEL

Address: 0xB402_0001

Access type: write-only

3

2

1

0

IRIG_FIBER_TX_INV

IRIG_FIBER_TX_SEL

The IRIG_FIBER_TX_SEL bits controls the configuration of the IRIG_FIBER_TX_NI

signal internal to the SR CPLD. The IRIG_FIBER_TX_NI is the Non-Inverted

counterpart of the IRIG_FIBER_TX signal. Similarly, the IRIG_FIBER_RX_NI is the

non-inverted counterpart of the IRIG_FIBER_RX signals.

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The table below summarizes supported values for IRIG_FIBER_TX_SEL register.

Value

Description

0x0

0, IRIG_FIBER_TX_NI signal is driven low

0x1

IRIG_FIBER_TX_NI = IRIG_FIBER_RX_NI

0x2

IRIG_FIBER_TX_NI = IRIG_SIGNAL_BUS

0x3

IRIG_FIBER_TX_NI = CH8_TXD

0x4

IRIG_FIBER_TX_NI = (CH8_RTS_L) ? (IRIG_FIBER_RX_NI) :

(CH8_TXD)

0x5-0x7

reserved for future use, IRIG_FIBER_TX_NI is driven low

The IRIG_FIBER_TX_INV bit allow for optional inversion of the

IRIG_FIBER_TX/IRIG_FIBER_RX signals as specified below:

IRIG_FIBER_TX_INV

0: IRIG_FIBER_TX/IRIG_FIBER_RX are not inverted

1: IRIG_FIBER_TX/IRIG_FIBER_RX are inverted

3.10.3 IRIG-B_RS485_TXD Register

Register Name: IRIG_B_RS485_TXD

Address: 0xB402_0002

Access type: write-only

3

2

1

0

IRIG_FIBER_TXD_SEL

The IRIG_B_RS485_TXD register controls the configuration of the IRIG-

B_RS485_TXD and IRIG-B_RS485_DRV_EN# signals. The RIG-B_RS485_DRV_EN#

signal is the “driver enable” signal for IRIG-B RS-485 isolated port J7-B.

The table below summarizes supported values for IRIG_B_RS485_TXD register.

Value

Description

0x0

Disabled/Irig-In:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b1};

0x1

reserved/unused

0x2

TEST0:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b0, 1'b0};

0x3

TEST1:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b0};

0x4

IrigOut:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =

{IRIG_SIGNAL_BUS, 1'b0};

0x5

~IrigOut:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =

{~IRIG_SIGNAL_BUS, 1'b0};

0x6

CH8:

{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =

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