QEI ePAQ-9410 User manual
EPAQ-9410 Hardware Programming Reference 0.16
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ePAQ-9410
Hardware Programming
Reference 0.16
User’s Manual
October 2019
EPAQ-9410 Hardware Programming Reference 0.16
________________________________________________________________________
________________________________________________________________________
Copyright © 2019 QEI Page 1
Copyright © 2019 by QEI
ePAQ-9410 Hardware Programming Reference
ALL RIGHTS RESERVED
NOTICE
The information in this document has been carefully checked and is believed to be
accurate. However, no responsibility is assumed or implied for inaccuracies. Further
more, QEI reserves the right to make changes to any products herein described to
improve reliability, function or design. QEI does not assume liability arising out of the
application or use of any product or circuit described herein; neither does it convey any
license under its patent rights nor the rights of others.
This manual and all data contained constitute proprietary information of QEI and shall
not be reproduced, copied or disclosed to others, or used as the basis for manufacture
without written consent of QEI.
45 Fadem Road
Springfield, NJ 07081
Phone: (973) 379-7400
Fax: (973) 379-2138
Web Site: www.qeiinc.com
EPAQ-9410 Hardware Programming Reference 0.16
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Copyright © 2019 QEI Page 2
Revisions
Revision
Description
Date
A
Release to Production
October 2019
EPAQ-9410 Hardware Programming Reference 0.16
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Copyright © 2019 QEI Page 3
Table of Contents
1Introduction................................................................................................................. 7
2References................................................................................................................... 7
3Blocks ......................................................................................................................... 7
3.1 Processor .............................................................................................................. 7
3.1.1 Memory Map ................................................................................................ 7
3.1.2 CPU GPIO Signal Usage.............................................................................. 7
3.1.3 Boot modes ................................................................................................... 9
3.2 Boot Modes .......................................................................................................... 9
3.2.1 CAPTURE and COMPARE....................................................................... 10
3.2.2 GPIO_BIT_BANG_OUT_CH[0,1]............................................................ 10
3.3 SDRAM.............................................................................................................. 11
3.4 NOR Flash.......................................................................................................... 11
3.5 NAND flash........................................................................................................ 11
3.6 SPI Flash ............................................................................................................ 12
3.7 Address Decoder CPLD..................................................................................... 12
3.7.1 Heartbeat Register....................................................................................... 13
3.7.2 L1 LED Register......................................................................................... 13
3.7.3 L2 LED Register......................................................................................... 14
3.7.4 L3 LED Register......................................................................................... 14
3.7.5 L4 LED Register......................................................................................... 14
3.7.6 SW10 High IP Address Register................................................................. 15
3.7.7 SW11 Low IP Address Register................................................................. 15
3.7.8 Option DIP Switch Register........................................................................ 15
3.7.9 AD CPLD Revision Register...................................................................... 16
3.8 QUAD UARTS.................................................................................................. 16
3.9 DUART.............................................................................................................. 17
3.10 Serial Routing CPLD...................................................................................... 17
3.10.1 IRIG-B Bus Register................................................................................... 18
3.10.2 IRIG_FIBER_TX Register ......................................................................... 18
3.10.3 IRIG-B_RS485_TXD Register................................................................... 19
3.10.4 IRIG-B_OUTPUT_TO_MICRO Register.................................................. 20
3.10.5 IRIG-B_MOD_OUT_EN_H Register........................................................ 20
3.10.6 CH8_RXD Register .................................................................................... 20
3.10.7 COM_EXP_IRIG-B Register .................................................................... 21
3.10.8 Telco [1,2] Mode Register.......................................................................... 21
3.10.9 Telco [1,2] Control Register....................................................................... 22
3.10.10 RS232 Port [1,2] Mode Register............................................................. 22
3.10.11 Bit-Bang CH [0,1] Register..................................................................... 23
3.10.12 Bit-Bang [0,1] RTS# Control Register.................................................... 23
3.10.13 DUART [A,B] Register........................................................................... 24
3.10.14 SR CPLD Revision 0 Register................................................................ 25
3.10.15 SR CPLD Revision 1 Register................................................................ 25
EPAQ-9410 Hardware Programming Reference 0.16
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Copyright © 2019 QEI Page 4
3.11 LED Monitor CPLD....................................................................................... 25
3.11.1 CH_RXD Status Register ........................................................................... 27
3.11.2 CH_RXD2 Status Register ......................................................................... 27
3.11.3 CH_TXD Status Register............................................................................ 27
3.11.4 CH_TXD2 Status Register.......................................................................... 27
3.11.5 CH_RTS Status Register............................................................................. 28
3.12 System Reset & Watchdog Timer .................................................................. 28
3.12.1 Watchdog Normal Mode............................................................................. 28
3.12.2 Bypass Mode............................................................................................... 29
3.12.3 Power-On Restart........................................................................................ 29
3.13 I2C Busses and Devices ................................................................................. 30
4Manufacturing Software ........................................................................................... 30
4.1 Initial Programming via Serial Port ................................................................... 30
4.1.1 NOR Flash programming via TFTP Server................................................ 31
4.2 Install additional files......................................................................................... 32
5Bring-up procedure................................................................................................... 32
5.1 Equipment list .................................................................................................... 32
5.2 Visual inspection................................................................................................ 33
5.3 ePAQ-9410 Motherboard Initial Power Up....................................................... 34
5.4 ePAQ-9410 ProcFull Initial Power Up .............................................................. 35
5.5 Initial programming............................................................................................ 35
5.6 CPLD programming........................................................................................... 35
5.7 Modem ports ...................................................................................................... 36
5.7.1 CH 1 TX/CH 2 RX configuration............................................................... 36
5.7.2 CH 2 TX/CH 1 RX configuration............................................................... 36
5.7.3 LED’s test ................................................................................................... 37
5.8 RS232/RS485 Ports............................................................................................ 37
5.8.1 RS-232 test.................................................................................................. 37
5.8.2 RS-485 test.................................................................................................. 38
5.9 OPTIONS S1 DIP switches................................................................................ 39
5.10 Status LED’s................................................................................................... 39
5.11 IRIG/SERIAL................................................................................................. 40
5.12 SD CARD....................................................................................................... 41
5.13 USB MAINT .................................................................................................. 41
5.14 USB HOST..................................................................................................... 41
5.15 IRIG (RS-485)................................................................................................ 41
5.15.1 IRIG TX test ............................................................................................... 41
5.15.2 IRIG RX test ............................................................................................... 42
5.16 RS-422............................................................................................................ 42
5.16.1 PORT 9 (J7A) external loopback test......................................................... 42
5.16.2 PORT 10 (J7D) external loopback test....................................................... 43
5.16.3 PORT 11 J7C external loopback test.......................................................... 44
5.17 RS-232............................................................................................................ 44
5.18 IRIG COAX.................................................................................................... 46
5.19 100BaseFX Ports............................................................................................ 46
5.20 10/100BaseTX Ethernet Ports........................................................................ 46
Table of contents
