Radio Shack TRS-8O User manual

!ladleIhaeK
•
ervlce
TRS-BO®
DISK/VIDEO INTERFACE
[AND EXPANSION FLOPPY DISK DRIVE UNIT)
•
l'•
1
,
Catalog Numbers: 26-3806/3807
.. .;-: '"
CUSTOM MANUFACTURED FOR RADIO SHACK. ADIVISION OF TANDY CORPORATION

"ill
Contents
1IINTRODUCTION 1-1
GENERAL. ........•..........................................••..1-1
SYSTEM OVERVIEW ..•.....................••........•••........•...
1-2
SPECIFICATIONS ........................••..........•..............1-4
2/DISASSEMBLY INSTRUCTIONS. ................................ .. 2-1
TOP CASE .................................•••........••......... 2-1
MAIN P.C. BOARD
...........................•.........•.•........... 2-1
POWER SUPPLY P.C. BOARD
......•..................•.•.........•...... 2-1
DISK DRIVE UNIT
..................•••.........••.................•. 2-2
FRONT PANEL ASSEMBLY ...........•.................................. 2-2
3/PREVENTIVE MAINTENANCE .................................. .. 3-1
ADJUSTMENT ....•..............................•.•.......•....... 3-1
SYSTEM CLOCK
........••...................................... 3-1
POWER SUPPLY
3-2
4/THEORY OF OPERATION. ..................................... .. 4-1
CPU ...........................•.........••........•.........•.. 4-2
ADDRESS DECODING AND BANK SELECTION CIRCUIT 4-3
MEMORY MAP ....•...............................•................ 4-3
I/O MAP .....•.........•..........••.........•........••......... 4-4
CLOCK GENERATOR CIRCUIT 4-5
SYSTEM BUS INTERFACE CIRCUIT
...........•••........••.........•...... 4-6
CRT INTERFACE AND CONTROL CIRCUIT 4-8
FLICKER SUPPRESSING CIRCUIT .................•••.................••.4-11
FDD INTERFACE SIGNALS ........•............•..................••.. 4-11
FDD CONTROL CIRCUIT. .........•................................... 4-13
POWER SUPPLY AND RESET CIRCUIT ............................••....... 4-16
5/TROUBLESHOOTING .......................................... .. 5-1
TROUBLESHOOTING FLOWCHART .....•.................................. 5-1
CHECKING PROCEDURE
....................•..........•........•...... 5-2
6/EXPLODED VIEW AND PARTS LIST. 6-1
EXPLODED VIEW •.................................................. 6-1
ELECTRICAL PARTS LIST
6-2
MECHANICAL/ASSEMBLY PARTS. ...............••...................... 6-13
7/P.C. BOARD VIEWS AND SCHEMATIC DIAGRAM 7-1
MAIN P.C. BOARD , ......•...... 7-1
MAIN P.C. BOARD -- REVISED
.••..........•........••................... 7-3
POWER SUPPLY P.C. BOARD ...............................••........... 7-5
SCHEMATIC DIAGRAM ....................••.........•..........•..... 7-6
APPENDIX AI INSTALLATION OF ADDITIONAL DISK DRIVE UNIT. A-1
APPENDIX B/CONNECTOR PIN ASSIGNMENTS. ................... .. B-1
SYSTEM BUS CONNECTOR B-1
RF MODULATOR ..............................••...................• B-2

APPENDIX C/SERVICING THE FDD UNIT" """"""""""""""""""""""""""" C-1
PART 1" MECHANICAL SECTION" """""""""""""""""""""""""""""""""""""""" C-1
1-1 INSTALLATION/REMOVAL OF COMPONENTS" """""_"""""""""""""""""""" C-1
1-2 ADJUSTMENT" """"""""""""""""""""""""""""""""""""""""""""""C-7
1-3 SPECIAL MAINTENANCE TOOLS" """"""" __ """_"""""""""""""""""""" C-15
1-4 MAINTENANCE" """""""""""""""""""""""""""""""""""""""""""" C-15
PART 2" ELECTRICAL SECTION" """""""""""""""_"""""""""""""""""""""""" C-1"7
2-1 GENERAL DESCRIPTION" """""" """"" """""" __ """"""" """""" """"""C-17
2-2 BLOCK DIAGRAM" """""""" __ """""""""""""""""" __ """"""""""""C-17
2-3 ELECTRICAL DIAGRAM" " __ """""""""""""""""""" __ """"""""""_""_ C-1 B
2-4 INDEPENDENT LSI CONRGURATION """"""""""""_""_•"""""""_""""."C-19
2-5 INPUT SIGNAL LINES (CPU TO FDD) " ..... " " " " " " " " " " " .. " " . " " " _" " _" " C-23
2-6 OUTPUT SIGNAL LINES (FDD TO CPU) """"""""""""""""""""""" •. " ... C-29
PART 3" CIRCUIT DlAGRAM_ """""".""""" """""" .. " .. """"""""""""""" C-33
PART 4" TROUBLESHOOTING" """"""""" .• __ """ __ """""""""""•""•" .. """"" C-35
4-1 PROCESSING SOFT ERRORS" " " " .. """_""""""""""_""""" .. " .. " " " " " C-35
4-2 FLOPPY DISK DRIVE FOR REPAIR" """"."""""""" __ "_""""""""""""""" C-36
4-3 TROUBLESHOOTING PROCEDURES" """""" .. " _" _" __ """""" .. """"" •• "C-37
PART 5" EXPLODED VIEW AND PARTS LIST. " . " " " . " " " . " " .. """"""" ... """"""""C-47
PART 6. SPECIAL MAINTENANCE TOOLS """"""""""."""""""""""""."""""""".C-57
Note: The expansion drive unit (Radio Shack Catalog Number 26-3807) is exactly the sameas the built-in drive unit
of the DiskNideo Interface. When servicing the 26-3807, refer to the drive unit portion of this service manual.
j,

List of Illustrations
FIGURE
NUMBER DESCRIPTiON PAGE
NUMBER
Disk Drive Removal .
Cable Connections .
Disk/Video Interface (Front View} . . . . . . . . . .
Disk/Video Interface (Rear View) . . . . . . . . . . . . . . . . . .
Top Case Removal .
Removal
of P.C. Board < ••••••••••••••••••••••••••••••••••••••••••••••••••
System BUS Connector .
RF
Modulator . . . . . . . . .
P.C. Board Removal .. . . . . . .
Clamp
Base BK and Clamp Arm KRemovals . . . . . . . . . . . . . . . . . .
Carrier
BK Removal .. . . . . . . .. . .
1- 2
1- 3
2- 1
2- 1
2- 2
3- 1
3- 2
4- 1
4- 2
4- 3
4- 4
4- 5
4- 6
4- 7
4- 9
4- 9
4-10
4-10
4-11
4-12
4-14
4-15
4-15
6- 1
7- 1
7- 2
7- 3
7- 4
7- 5
7- 5
7- 6
A- 1
A- 1
A- 2
8- 1
8- 2
C- 1
C- 2
C- 3
C- 4
C- 5
C- 6
C- 7
C- 8
C- 8
.............................................
Pulse Motor BK Removal
System
Clock Adjustment . .
+5V Adjustment. . . .. .< • • ••••••••••••••••••••••••••••••••••••••
Block Diagram .
CPU Control Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Decoding and
BANK Selector Circuit .
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator
Circuit. ........................................ . .
System
BUS Interface Block Diagram (Receive Mode). ..................... . .
System BUS Interface Block Diagram
{Transmit Mode} .
CRT Interface Block Diagram .
Display
Timing Chart (40 Characters Mode) . .
Display
Timing Chart (80 Characters Mode) . . . . . . . . . .
Waveform
of Video Signal . .
Flicker Suppression Circuit. . . . . . . . . . . . . . . . . . . . .
FDD Interface Block Diagram. . . . . . . . . . . . . . . . . . . .
Data
Separator. .................... . .
Pre-Compensation
Circuit. ........... . .
Wait
Control Circuit .
Exploded View . . . . . . . . . . . . . . . . . . .
Main
P.C. Board (Top View) . . . . . . . . . . . . .. . .
Main
P.C. Board (Bottom View) . . . . . . . . . . . . . . . . . . . . . . .
Main P.C. Board-Revised
(Top View) . . . . . . . . . . . . . . . . . . . . . .
Main P.C. Board-Revised
(Bottom View) .
Power
Supply P.C. Board (Top View) .
Power
Supply P.C. Board (Bottom View) . . . . . . . . . . . . . . . .. . . . . . . . . .
Schematic Diagram < • • • •
•••••••••••••••••••
Preparation on P.C.B. of FDD . . . . . . . . .
Installation of FDD .............. .... .. . .
Spindle
Motor KRemoval . .
Track Sensor Removal .
Index Sensor
Adjustment .
Winding
the Steel Belt .
Mounting the Belt Supporter .
H
1-2
2-1
2-2
2-3
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
6-1
7-1
7-2
7-3
7-4
7-5
7-6
7-7
A-l
A-2
A-3
8-1
8-2
C-l
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
•

FIGURE
NUMBER DESCRIPTION PAGE
NUMBER
C-lO
C-1l
C-12
C-13
C-14
C-15
C-16
c-n
C-18
C- 19
C-20
C-2l
C-22
C·23
C-24
C-25
C-26
C-27
C-28
C-29
C-30
C-31
C-32
C·33
C-34
C-35
C-36
C-37
C·38
C-39
CAD
C-41
C-42
C-43
C-44
CA5
CA6
C-47
Mounting the Pulse Motor K . 0 0 ••••••••••• 0 •••• 0
Tensioning the Belt. _0 ••••••• 0 •• 0 •• 0 •• 0 •••••
Confirmation of the Belt Gaps ... 0 0 ••••••••••• 0 •••••••••••••
Fixing the Track 00 Stopper .. 0 0 • • • • • • • 0 •••••• 0 0 ••••••••• 0 •• 0 ••••
Waveform of Index Pulse .. _0 ••••••••• 0 0 •••• 0 0 0 •••••
Waveform of Head Output . . . . ... 0 0 • • 0 •••• 0
Motor Speed Adjustment. 0 ••• 0 ••••• 0 0 •• 0 ••
Track 00 Adjustment .0 ••••••• 0 0 ••••••••••••
Interrupter Timing Chart ..... 0 0 •• 0 ••
Block Diagram 0..... 0 ••••• 0 •• 0 •••• 0 •••••••••• 0
Electrical Diagram ... 0 0 • • • • • 0 •••••••••••••••• 0 •• 0
Pin Configuration of Control LSI. 0 •••• 0 0 ••••••• 0
Block Diagram of Control LSI. 0 •••••
Pin Configuration of Read LSI 0 0 • • •••• 0 0 •••• 0 •••••••
Block Diagram of Read LSI 0 0 •• 0 • • 0 •••• 0 ••••••••• 0
Block Diagram of Drive"Select Circuit. . . . 0 •• 0 • • • • • 0 •••••
Side Select Circuit ... 0 0 •••••••••••• 0 ••• 0 • • • • • • • • • • • • • • • • 0 •• 0 •••
Head Positioning Circuit 0 0 ••••••• 0 •• 0 • 0 • • • • • 0 •••••••
Timing Chart for the Direction and Step Signal ... 0 0 •• 0 ••• 0 0 •••••
Write Circuit and Erase Circuit ..... 0 0 ••••••• 0 0 • • • • • • • ••••• 0
Timing Chart for Write Circuit
Timing Chart for Erase Circuit 0 _ • 0 • 0 ••
Data Recording Procedure 0 •••••
Motor ON Circuit 0 ••• 0 ••
Index Circuit
Waveform
of TP2-4 Pin .0
Track 00 Detection Circuit 0
Waveform of TP2-2Pin .
Write
Protect Circuit .... 0
Read Amplifier Circuit .. 0 ••••••• 0 ••••••• 0 0 • 0 •••• 0
Timing Chart for Read Amplifier Circuit _ .
Circuit Diagram
0..... • • 0 •••• 0 ••••••• 0
Test System Hook-up .0 ••••• 0 •••• 0 •••••
Exploded View of Main Unit ... 0 •••• 0 • 0 ••• 0
Exploded View of Clamp Base BK and Carrier A .. 0 • 0 ••••• 0 0 •••••••
Exploded View of Pulse Motor BK. .0 • • • • • 0 • • • • •• o. 0 ••••••
PoCo Board. . . . . 0 • 0 •• 0 0 _ • 0 ••• 0 0 •••• 0
Special Meintenance Tool. 0
c· 9
C· 9
C·10
C-l0
C-"
C-ll
C- 12
C- 13
C-14
c·n
C-18
C-19
C-20
C-22
C-22
C-23
C-23
C-24
C-25
C-26
C-26
C-27
C-27
C-28
C-29
C-29
C-29
C-30
C-3l
C·31
C-32
C-33
C-36
CA7
C-48
C·49
C-50
C-57

TABLE
NUMBER
List of Tables
DESCRIPTION PAGE
NUMBER
4-1 I/O Port Description 4· 4
4,2 Signals from the Portable Computer 4- 6
4-3 PPI Function Table 4- 7
4-4
Function of the Principal Signals _4- 8
4-5 FDG Function Table '4-13
4-6 Description of the Principal Terminals . . . . . . . . . . . . . . . . 4-13
B-1 System Bus Connector Pin Assignments .. ............ . S- 1
Col Pin Assignments of Control LSI. . . . . . . . . . . . . . . . . . . . . . . . . C-21

•
1/lntroduction
This manual is prepared for the TRS-80 Disk/Video Interface technicians working in the field or repair centers. The user
of this manual should be acquainted with Z-80 CPU, 8255 PPI (Programmable Peripheral Interface), HD6845S CRTe {CRT
Controller) and M5W1793·02P FDG (Floppy Disk Controller).
This manual consists of seven sections and three appendices:
•The Introduction gives general information on
the TRS"80 Disk/Video Interface such as specifications, s~itch functions,
etc.
•Section 1describes disassembly procedures.
•Section 2describes preventive maintenance and adjustment.
•Section 3describes general theory
of the TRS-80 Disk/Video Interface operation.
•Section 4describes how to troubleshoot
the TRS-80 DisklVideo Interface.
•Section 5provides aparts list and an exploded view
of the TRS·80 Disk/Video Interface.
•Section 6provides schematics,
P.C. board diagrams and silk screen view of the P,C. boards of the TRS-80 DisklVideo
Interface.
•Appendix Aprovides instructions for installing an additional disk drive unit.
•Appendix Bprovides technical information for connector signals.
•Appendix Cprovides service information on
the built-in FDD unit.
General
By utilizing the TRS-80 DisklVideo Interface with the TAS·80 Portable Computer, the user can fully realize the capabilities
of the TRS-80 Portable Computer.
The TRS-80 DisklVideo Interface consists of:
•Interface circuit; Transfers data and commands to the TAS-80 Portable Computer.
•Floppy disk drive unit: Drives 5-1/4 inch single-sided, double density floppy disk.
•Floppy disk controller (FDC): Controls driving
of the floppy disk drive unit.
eCentral processing unit (CPU) and memory; Controls interface circuit, floppy disk controller and CRT controller.
To connect
the TRS-80 Disk/Video Interface to the Portable Computer, use the connector cable supplied as an accessory.
Install
the adapter socket provided with the Disk/Video Interface on the System Bus Connector located on the bottom
side of the TRS-80 Portable Computer. Connect one side
of the cable to the adapter socket and the other side to the same
connector located on
the bottom side of the Disk/Video Interface.
1-1

System Overview
Figure 1-1. Disk/Video Interface (Front view)
CD LED Power Indicator: Lights up when the Power Switch is on.
mDrive 0: This is the disk drive unit used for the BASIC SYSTEM diskette.
(}) Drive Select LED: LED lights during access of the diskette.
CD Optional Disk Cover: Remove this cover to install the expansion drive unit. See Appendix A.
oClamp Lever: Turning this lever downward locks the disk drive unit into the operating position.
1-2
•

456
32
7
Figure 1-2. DiskiVideo Interface (Rear view)
CD AC Power Cord: Supplies AC power source to the Disk/Video Interface.
G) PowerSwitch: Turn this switch on to supply AC power to the Disk/Video Interface.
CD Fuse Holder: Contains afuse. Remove the AC cord from the AC receptacle while inspecting/replacing the fuse.
(±) Video Monitor Terminal: Connect your video monitor for a 80 x 25 or 40 x 25 line display.
G) Home TV Terminal: Provides RF output modulated to Channel 3 or Channel 4* of the TV frequency. Connect your
home
TV set to this terminal using the TV cable and switch box supplied.
@) Channel 3/Channel 4Exchange Switch*"': Select either Channel 3or Channel 4RF output (Channell or Channel 2
for Australia), whichever is not used in your area.
(j) System Bus Connector: Connect the system bus connector of the Portable Computer using the attached cable.
~ Channel 1 or Channel 2'for Australia version.
Channel 36 UHF signal for UK/Belgium version.
""_. Deleted for UK/Belgium version.
1-3

Specifications
Operating Voltage:
Power Consumption:
Operating Temperature Range:
Operating Humidity Range:
Dimensions (W x H x O):
Weight:
Disk Drive:
Spindle Rotation Speed
Seek Time
Average Access Time
Motor Starting Time
Data Density
Track Density
Number
of Tracks
Number of Sectors
Bytes/Sector
CRT jnterface;
Display Mode
Display attribution
RF Output Channel
Modulation Ratio
Output Impedance
RF Output Level
Horizontal Scanning Frequency
Vertical Scanning Frequency
120 Volts AC for USA and Canada
220 Volts AC for Belgium
240 Volts AC for UK and Australia
66 Watts
S"C
~ 40°C
20 to 80%
430 x 125 x 300 mm (16-15/16" x 4-15/16" x 11-10/12")
8kg (17.7lbs)
Single,sided, double density
300 R.P.M.
6msec.
88 msec.
500 msec.
5536 B.P.I.
48 T.P.1.
40
18
256 Bytes
40 columns x25 lines or 80 column x 25 lines
Normal,
Blink, Reverse or Reverse and Blink
VHF 3 or 4channel for USA/Canada
VHF 1 or 2channel for Australia
UHF 36 channel for UK/Belgium
75% Typ.
75 ohms
62.5
dBti (67.3 dBf) Typ.
15.625 kHz
60.1 Hz
1-4

2/Disassembly Instructions
Top Case
1. 0isconnect the cables from the unit.
2. Remove the four screws (A) on the left and right of the unit.
3. Remove
the top case by sliding it toward the rear of the unit.
Main P .C. Board
Figure 2 -1. Top Case Removal
1. Disconnect the two connectors marked eN1 and CN4 on the main P.C. Board.
2. Remove the four screws (B).
3. Take out the main P,C. Board. Be careful not to damage the connectors and switch inside on the rear panel.
4. Disconnect the connector marked CN2 and ground lead.
Power Supply P.C. Board
1. Disconnect all the connectors from the power supply P.C. Board.
2. Remove
the two screws {C) and take out the power supply P.C. Board.
Figure 2-2. Removal of P.C. Boards
2-1

Disk Drive Unit
1. Disconnect the two connectors marked eN-2 and CNA on the floppy disk control P.C. Board.
2. Remove
the four screws (0) tightening the floppy disk supporting bracket.
3. Remove
the floppy disk drive unit together with the floppy disk supporting bracket by sliding them toward the rear of
the unit.
4. Remove the screws (E), two each on the left and right supporting brackets securing the floppy disk drive unit.
tr
{D{
Figure 2-3. Disk Drive Removal
Front Panel Assembly
1. Remove the two screws securing the front panel assembly to the chassis.
2. Take
out the front panel assembly by moving it toward the front of the unit. Be careful not to damage the three snaps
securing
the front panel assembly to the chassis.
2-2

3/Preventive Maintenance
To ensure the proper operation of the Disk/Video Interface, the only scheduled preventive maintenance required is periodic
cleaning
of the magnetic recording head.
Radio Shack's Universal Disk Drive head cleaning kit for S-1/4-lnch disks works well for this purpose. The kit includes two
special cleaning disks and one bottle of cleaning solution.
Cleaning the Head
To clean the magnetic head, use alint-free cloth or cotton swab moistened with 91% Isopropyl alcohol. Wipe the head
carefully to remove all accumulated oxide and dirt.
CAUTION: Rough or abrasive cloth should not be used to clean the magnetic recording head. Use of cleaning solvents
other than 91% Isopropyl alcohol may damage the head.
Extreme care must be exercised to prevent the head from being damaged (do not scratch or strike the head).
Adjustment
This section describes adjustment of the System Clock and Power Supply. When you are going to adjust the floppy disk
drive, refer
to Appendix C. Before adjustment, turn the power switch of the Disk/V.ideo Interface on and load the DOS
from the system diskette.
System Clock Adjustment
1. Connect the frequency counter to pin 3 of Mll on the Main PCB.
2. Adjust the C44 trimmer capacitor to read 16 MHz +0%, -0.3% (16 MHz to 15,952 MHz) on the frequency counter.
Frequency counter
16MHz
INPUT
•
?
to GND --ll
adjust
MO<
o
3pin
-
iI
J
•
Figure 3·1. System Clock Adjustment
3-1

+5V Adjustment
1. Connect aDC voltmeter across pin 2 of CN4 (Ground~ and pin 3 of CN4 (+5V) on the Main PCB.
2. Adjust VR 101 on the Power Supply PCB to read +5V +0.1 V, -0.1 Von the DC voltmeter.
DC voltmeter
OJ
• 0
INPUT
" '" '"
~4
5J4U3!
'! '
/ad)US!
Figure 3-2. +5V Adjustment
3-2

4/Theory of Operation
The TRS-80 DisklVideo Interface uses apPD780C (compatible with Z-80A) as the CPU.
The CPU controls the transaction of data or commands between the Portable Computer and the Disk/Video Interface by
the PPI (8255), control afthe CRT by the CRTe (HD46505) and control of the FDD by the FOG (M5W1793-C2).
The memory consists of four sections:
• 4K bytes of P-ROM which store aprogram that reads the control program from track 1of the system diskette (actual
memory size used is 1K bytes).
•4K bytes of RAM to store the control program read.
e 4K bytes of VRAM (Video RAM) to display characters on the CRT.
e 4K bytes of P-ROM to store the dot pattern of the characters (actual memory size used is 2 K bytes),
Isk D.lve
Unit.
--,
,
,
,
,
,
,
,
,
,
,
,
--"
Systgm Bus
TRS~60
,
'"
""
Portable
8255
ROM
,,"
Computer
,
,
r--"
."
<,
n-
,Z80A
(CPUl KDoto BUS, Add.ess 8us Cont.ol Bus
11 11
CRTCI==:>f 4 K RAM
I
HD 46505$ 1I,'-RAMI
eo'
"'-J.
8
Chorocter
Gene.g!o.
"
~-------,
,,
"'-J.
,0
,Shift
I CRT
Re~l",e.
lP-S)
0
Monito' I,
, --
,j
,
fr
,
fr
,I,,
IHome ,",
"I
ModulO-lor
,
,,
I
~
,-
,
OpTion
,,
OpTion
,,
________ JL ____
Figure 4-1. Block Diagram
•
4-1

This section provides circuit descriptions of the 0isk/Video Iriterface,dividing it into the following eleven parts:
• CPU
•Address Decoding and Bank Selection Circuit
•Memory Map
•I/O Map
•Clock Generator Circuit
•System Bus Interface Circuit
•CRT Interface and Control Circuit
•Flicker Suppressing Circuit
•FDD Interface Signals
•FDD Control Circuit
•Power Supply and Reset Circuit
CPU
•
The CPU is aj1PD780C compatible with the Z-80A.
System Clock: Uses 4-MHz clock,
The clock generator circuit generates a16-MHz dock and it is divided by four by M27
(SED9421C).
Data BUS and Address BUS: Connected
to each memory and also used as the select signal and data BUS for the PPI, CRTC
and FDC.
Interrupt:
Two terminals, INT (I nterrupt Request) and i\fMl (Non Maskable Interrupt), accept interrupts. By writing data
into the
PPI via the Portable Computer, (NT is generated. The CPU receives the data from PPI by jumping to the Interrupt
Handling Routine.
NMI is used for accepting the completion of disk commands.
BUSRQ:
SUSRQ is input from the Flicker Suppressing circuit. EfUSRO prohibits the CPU from accessing VRAM while the •
CRT
is displaying characters and prevents flicker of the CRT.
RESET: RESET
is generated in the power supply circuit and is used as a RESET signal for the CPU, ICs and LSls.
M27 Clock
Generator
System
Bus
q,
Interface INT
Flicker Suppressing ~
'BUSRQ
Circuit
'2" L'L'
CPU
<
--
NMI ,
FDD
Control Circuit
--
WAIT
RESET
Power Supply •
Figure 4-2. CPU Control Diagram

---------------------------------,--------
•Address Decoding and Bank Selection Circuit
M31 and M38 determine memory address decoding. M31 decodes A15, A14 and A13, and selects ROM (M40), RAM (M28
and M36l, ARAM (M23) and CRAM (M9).
The output of 20 in M16 selects BANK switching. At power-on, M16 receives the RESET signal and BANKO is assigned
so
that the program starts from address COOOH in the ROM. After that, the CPU assigns STS as the 110 Port and sets bit
01 of the data bus to "H", a nd the BAN K1 is selected.
2) CE
AM 1) CE
ROM) cl~
Vc
01 3 2
BA'N'k6
13
11
2D 20
...d M34;
M40 (p.
M16
12 _.-
STSWR elK
9
M7
BANK"" 9
1J elK
8
12
...;,j M34 ,r
RESET M36(R
vr
10
v"
RFS'i-l 6
YO
15 15 G
YO
12
1G
MREQ 4
--
Y1
14 NC
'11
11
M28 (RAM
2GA
5
2GE!
-13
NC
All 13 -10
NC
Y2
A
M38 Y2
m'13 12
NC
A12 14
8
Y3
9 NC
M31 Y4
11 NC
GNO
Y5
10 NC J,-
A15 3-9
ARAM
CY6
A14 28
Y7
7 CRAM
A13 1
AGND
V"
~
)'6
c
•
Figure 4-3. Address Decoding and BANK Selection Circuit
Memory Map
The DisklVideo Interface uses two 4K-byte P-ROMs and four 2K-byte Static RAMs.
At power-on, the P·ROM program is used to load the control program from the system diskette, but as the address codes
A10 and
Ali are connected to ground through A25 and A28, memory is 1024 bytes.
Another
P-ROM is used as acharacter generator and accessed by the CRTC. Two 2K-byte RAMs, RAMi and RAM2, are
assigned for
the control program.
Two other
AAMs are CRAM (Character RAM), which stores data to display on the CRT, and ARAM (Attribute RAM).
which stores data to reverse and blink characters.
• A P·ROM for
the program and RAM1 are switched by the BANK selection circuit. At power-on and while track 1of the
system diskette is being read, the combination of RAM2 and BANKO P-ROM is selected. After the system has been read,
the combination is switched to RAM2 and BANK1 RAM1.
4-3

.----------------------~ -
BANKl
~
~
I/O Map
0000
0400
0800
1000
CODO
C7FF
EDOO
E7FF
BANKO
P-ROM 1K
~
L..:..:.-J
I I
~
~
I I
VRAM
(ARAM)
2K
VRAM
(CRAM)
2K
Figure 4-4. Memory Map
•
•
Selection of an I/O Port is determined by M38 by decoding the address of A5, A6 and A7. There are four 1(0 ports:
Address
Signal Description
---------- ---------'''-
DOH eRTC DOH: Address Register of eRTC
j02H: Command Register of CRTC (for Write)
1FH
03H:
Status Register of CRTe (for Read)
----
20H S1'S
20H
I
Bit
Read Write
""'-'-
0 PPI PBO
Select 80 characters mode
1 PB1 Select Bank 1
2PB2 Not Used
3PB3 Not Used
4PB4 Select Drive 0
5 VSRET Select Drive 1
6 IBF
Half CPU if VSRET is High
3FH 7 MOTOR ON Enable head
40H
FO'C
50H:
Status Register of FOG
(for Read)
50H: Command Register of FOG (for Write)
51H: Track Register of FDG
52H: Select Register of FOC
5FH
...... 53H: Data Register
of FOe
,~""
GOH
8255 60H:
Input from 8255
j
7FH
70H:
Output to 8255
•
lTable 4-1. I/O
Port Description
4-4
-----

•Clock Generator Circuit
The clock generator circuit generates al6-MHz clock and is used as the fundamental element for the system clock in the
CPU, the timing clock for the FDD to read/write data and the timing clock for the CRT.
The l6-MHz clock, generated by
M37 (NAND gate) and the l6-MHz crystal oscillator, is transferred to the FOD interface
circuit and also transferred to M27 (SED9421C). This l6-MHz clock is divided by four by M27 and, passing through M14,
it is transferred to the CPU as a4-MHz clock. The CPU uses this clock as the system clock.
Also
in M27, the l6-MHz clock is used as the timing clock to read/write data between the FDD. This l6-MHz clock is divided
by
two by M47 and the divided 8-MHz clock is supplied to the pre-compensation circuit in the FDD interface. The timing
clock of
the CRT isalso generated by this circuit.
The fundamental factor of character display
is DCLK. DCLK is atiming signal which shows 1 dot on the CRT. Every eight
DCLK
outputs one lOAD signal. lOAD is atiming signal which displays one character on the CRT.
There are
two modes of character display; one is 40 characters per one line and the other is 80 characters per one line.
For
the 80 characters mode, 1Q in M16 is set by the CPU and BOC becomes "l". Then Mll becomes preset so that the
16-MHz ciock passes through M34and M37, and is input into the elK terminal of M33 dIrectly.
For
the 40 characters mode, at the gate of M34, BOC becomes "H" so that the 16-MHz clock is inhibited and divided by two
in Ml1, and input into the ClK terminal of M33.
Because of this logic, display
time of one character in 80 characters mode becomes half of that in 40 characters mode.
DClK
2
M32 ClI<
•G514
0A
13
08
M33
212
0C
to CRCT ClK
NC
11
00
M37 nVee
,
""5a
ClR
D 2
C83
Jr
56P
Mn
6 b
PR
,
3 C:l<>----''---+_
M34
2
R24 1K
C44
25P
I f-'~ r-+ 046
33'
e51
r+r
220P
8M
>OM
5Q
6Q
D'
3
elK
M7 15
10
1D 14
DD
8
'DC
M>O
f6 CCK
STSWR
9
•Figure
4-5. Clock Generator Circuit
4-5

System Bus Interface Circuit •
Transaction of data or commands between the Portable Computer and the Disk/Video Interface is executed by M45, M41
and M44 under the control of the CPU,
The signa Is from the Portable Computer are as tollows:
-
Signal name 1
__________ lnput or Output
Description
------------ -----
YO
Input Chip select signal for PPI
AD
I
Input Port select signal for PPI
-------------
Al
I
Input
I
Port select signal for PPJ
-Allows
the Portable Computer to read
RD Input
data from the PPI
-
-
Input
Allows the Portable Computer to write
WR
data and commands in the PPI ds in the ppj
I
00- D7 i Input/Output
Data lines
Table 4-2. Signals from the Portable Computer
As soon as the DC voltage of the Disk/Video Interface reaches a proper level, RES signal becomes "L" and PCO, PC1 and
PC2 terminals in the PPI also become low level, By checking the level of these 3bits (whether they are "L" or not), the
Portable Computer decides if the Disk/Video Interface is in an operable or inoperable mode.
1. Transmission of signals from the TRS-SO Portable Computer to the Disk/Video Interlace
If you are going to transmit data from TRS·8D Portable Computer to the Disk/Video Interface, the Portable Computer
checks O'i3F (Output Buffer Full) first. If this signal is "L", the Portable Computer waits until it becomes "H". As soon
as
the output buffer becomes empty (OBF '" "H"), the Portable Computer writes data mode on the least significant
4bits of Port B in the PPI.
This data mode is the data which define the going data whether they are commands or data, and to be transferred to the
CRT or FDD and then, the data are written on the Port A in the PPI. Then, OBF becomes "L".
The OSF signal generates interruption in the CPU o'f the Disk/Video Interface, Through this interruption, the CPU
acknowledges that the data is ready to be transmitted in the PPI, and then receives the data through PAD -PA7 ter-
minals
in the PPI by switching the ACK (Acknowledge input) signal to "L",
Receiving the A'CK signal from the CPU, the PPI switches OSF to "H", and reading OSF from Port C, the Portable
Computer transfers the next data to Port A in the PPI.
•
•
CPU PPI
- - ---,
-"
Data ~':,
'eo",,,,
[Data
'-'-;J-@
,fORD·8is'5
rY
IOBF ACK
T
INT
•OBF [
'PCin;g;:' [,
-"
t?
ala Mode X' ?0,\50
IData Mode
,
- -
--
i
Portable
Computer
f--+--,
~
lORD· STS
Figure 4-6. System BUS Interface Block Diagram
(Receive Mode)
4-6