Shugart SA455 User manual

SECTION I
INTRODUCTION
1.1 GENERi\L DESCRIPTION
The SA455/465 Minifloppy Disk DrlvE!s are enhanced double~headed, half~helght versions of the ShuBarl SAIJOO
minifloppy drives. The SA455/46f> provides up to four Umes the on-line storage capacity, faster access time, nnd
improved reliability and maintainability'.
51\455/465 drives read and write in single and double density on standard 5.25 inch diskettes on both :sides of the
diskettes. The
new drives are: half the height of the Shugart SA400 and are plug compatible.
The compact
SA455/465 offers areliable, low cost, high performance alternative to OEM data storage applica-
tions where tape cassette units
wOUild bave been previously considered.
SA455/465 drives have these standard features: compact size' ~ 1.62 Inches high x 5.75 inches wiele x 7.96
inches deep, and aweight of 3.3 pounds; low heat dissipation; de drive motor with precision servo speed control
(lnd integral tachometer; band positioner; same proprietary glass bonded ferrite/ceramic read/write head as used
in SIIllUml\ Imge floppy drives; Int,ernal write protect circuitry; activity light. and solid die eust chassis.
Typical applications for the SA455/465 are word processing systems, entry level micro-processor systems, in-
telligent calculators, program storagl:!,hobby computer systems, and other applications where low cost rilndoTl\ ac-
cess data storage is arequirement.
This manual prOVides depot level maintenance Informatk:m necessary to maintain, trouble-shoot, and repair the
SA455/465. Aseparate OEM manual (PIN 39238) Is available which describes installation. interface. ,mel power
requirements useful for the applications of the drive.
Key Features
a. 0.5 Mbytes (SA455) or 1.0 Mbyte (SA465) storage capacity (unformatted)
b. Low power (12.5 wallts)
c. 125/250 kbits/second transfer rate
d. DC drive motor (eliminates ac requirements)
1.2 SPECIFICATION SUMM~lRY
1.2.1 Perfonnance Specifications
SA455 (40 Track)
Single Densit~1 Double Density
(PM) (MFM)
SA465 (80 Trad')
Single Denstiy Double Density
(FM) (MFM)
Capacity
(in bytes)
Unformatted
Per Disk
Per Surface
Per Track
250,000
125,000
3,125
1·1
500,000
250,000
6,250
500,000
250,000
3,125
1,000,000
500,000
6,250

Formatted (16 Records/Track)
Per Disk
Per Track
Per Sector
Formatted (10 Records/Track)
Per Disk
Per Track
Per Sector
Transfer
Rate
Latency (avg.)
Access Time
-rrack to Track
Average
Settling Time
SA455 (40 Track)
SA465 (80 Track)
Single Density Double Density Single Density Double Density
163,840 327,680 327,680 655,360
2,048 4,096 2,048 4,096
128 256 128 256
204,800 409,600 409,600 819,200
2560 5120 2560 5120
256 512 256 512
125 kbits/sec 250 kbits/sec 125 kblts/sec 250 kblts/
sec
100 ms 100 ms 100 ms
100 ms
6 ms 6 ms 3 ms
3 ms
93 ms 93 ms 94 ms
94 ms
15 ms 15 ms 15 ms
15 ms
1.2.2 Functional Specifications
Motor Start Til11('
Hotatlotlal Speed
Recording Density
Flux Density
Track Density
Media Requirements
Soft sectored
16 sectors hard sectored
10
sectors hmd sectored
Industry standard flexible diskette
Oxide on O.OO~ in. (0.08 mm) Mylar
5.25 In. (133.4 111m) square jacket
1.2.3 Physical Specifications
500 ms
500 ms
500 ms
500 ms
300 rpm 300 rpm 300 rpm 300 rpm
2938 bpi 5876 bpi 2961 bpi 5922 bpi
5876
fcl
5876 fci 5922 fcl 5922 fcl
48 tpi 48 tpi 96 tpl 96 tpl
SA154 SA154 SA164 SA164
SA155 SA155 SA165 SA165
SA157 SA157 SA167 SA167
Environmental Limits
Ambient Temperature
Relative Humiditv
Maximum Wet Bulb
Shock
Vibration
Operating
.50° to 11soF
(10.0° to 46.1°C)
20 to 80%
78°F (25.6°C)
0.5G 10
rns
0.5G 5-600 Hz
Shipping
-400 to 144°F
(.40° to 62.
2°C)
1to 95%
No Condensation
15G 10
ms
3G 5-600 Hz
Storage'
_8° to 117°F
(-22.2° to 47.2°C)
1to 95%
No Condensation
35G 10
ms
3G 5-600 Hz
.DC Voltage Requirements
+·12 V±10% @1.2 A(max), 0.6 A(typ), 100 mV ripple
+5 V ±5% @ 0.9 A (max:), 0.6 A(typ), 50 mV ripple
Mechanical Dimensions (exclusive of front panel)
Width :5.75 Inches (146.1 mm)
Height: 1.62 Inches (41.1 mm)
Depth :::::. 7.96 inches (202 mm)
Weight =:t:3Ibs (1.5
kg)
Power Dissipation =9.6 Watts (34.0 BTU) continuous typical
3.6 Watts
(13;.5 BTU) standby
NOTE
Standby: Drive motor off. dr.lve select off, and stepper at reduced current.
1·2

1.2.4 Reliability Specifieatianli
MTBF: 10,000 POH under typical usage.
PM: Not required.
MTTR:
:30 minutes.
Error Rates:
Soft Head Errors: 1per
10" bits Hmd.
I--Iard Head Errors: 1per 101 :.1 bits read.
Seel~ Errors: 1per 10
6seeks.
Media Lif('.:
Passes per Trac!(: 3.0 x 10('
Insertions: 30,000 +
j\.3 FUNCTIONAL CHARACTERiSTICS
The SA455/465 consists of read/write and control electronics. drive mechanism, read/write head, and precision
track positioning mechanism. These components perform the following functions:
a. Interpret and generate control signals.
b. Move read/write heads to the desired track.
c. Read and write data.
The interface signals and their relationship to the internal functions are shown
In figure 1-2.
1.3.1 Read/Write and Control EIE~ctronics
The electronics package contains:
a, Index detector circuits
b. I-lead position actuator driver
c, Read/write amplifier and liransition detector
d. Writeprotect detector
e. Drive select circuit
f. Drive motor control
1.3.2 Drive Mechanism
The dc drive motor under servo . spE~ed control (using an integral tachometer) rotates the spindle at 300 rpm
through adirect drive system.
An expandable collet/spindllB assembly provides precision media positioning to en-
sure data interchange.
1.3.3 Positioning Mechanics
The read/write head assembly is accul'atelypositioned through the use of aband positioner which is attached to the
head carriage assembly. Precise track location is accomplished as this positioner is rotated in discrete increments by
astepping motor.
1.3.4 Read/Write Heads
The proprietary heads are asingle elementceramic read/write head with tunnel erase elements to provide erased
areas between data tracks. Thus normal interchange tolerances between media and drives will
not degrade the
signal·to-noise ratio and diskette interchangeability
is ensur,ed.
The
read/ write heads are mounted on acarriage which is located on precision carriage ways. The diskette is held
in aplane perpendicular to the
read/write heads by aplaten located on the base casting. This precise registration
assures perfect compliance with the re,ad/write heads. The
read/write heads are in direct contact with the diskette.
The
h(~ad surface has been designed to obtain maximum signal transfer to and from the magnetic surface of the
diskette with minimum head/diskette wear.
1·3

1.3.5 Recording Formats
The formats of the data recorded on the diskette are totally afunction of the host system. These formats can be
designed around the user's application to take maximum advantage of the total available bits that can be written
on
anyone track.
-
ACTIVITV
LIGHT
1-1-'-,-------.-----1
STEP
DIRECTION SELECT
INDEx/SECTOR 1-1-'-.- ... ------,------1
I.ED
STEPPER A
DRIVE SELECT (4 LINES)
...
CONTROL TRACK 00
LOGIC
INOEx/SECTOR
STepPER
MOTOR
TRACK 00
SWITCH·
STEPPER B
-
STEPPER C
STEPPER 0
-
1-t-1'RACK 00 (COM)
TRACK 00 (N/C) _
...
MOTOR ON
SIDE SELECT
READY
-
INDEx/SECTOR
DETECTOR
DRIVE
SELECT
SIDE
SELECT
DRIVE
MOTOR
REAO/WRITE
HEAD
ASSEMBL''(
I
WRITE WRll'E PROTECT (N/2)
PROTECT -'--1.. ..
SWITCH !-+w'RITE PROTECT
.... -----' (COM)
WRITE HEAD 0
WRITE HEAD l'
It •
WRITE
LOGIC
--
WRITE DATA
WRITE GATE
WRITE PROTECT
.-
.J
~~
........
0%
:E8
ffi
tu
~
o
:t
~
....
READ HEAD 0
...... • __ R_EA_D_H_EA_D_1· __ ,., __ --t .......
SIDE
SELECT
If
READ
LOGIC
READ DATA
MOTOR
DRIVER
MC)TOR ON
....... ------
'SA465 ONLY.
FIGURE 1·2. SA455/465 FUNCTIONAL DIAGRAM
1·4
39238·02·/\

1.4 FUNCTIONAL OPERATIONS
1.4.1
Power Sequencing
Applying dc power to the SA455/465 can be done in any sequence. However, during power up, the WRITE
GATE line must be held inactive or at
4;\ high level. This wlll prevent possible "glitching" of the media. After ap-
plication of dc power, a
100 ms delay should be introduced bE!fore any operation is performed. After powering on,
Initial position of the read/write heads with respect to the data tracks on the media is indetermlnant. In order to
assure proper positioning of the
read/write heads after power on, a Step Out operation should be performed until
the TRACK
00 line becomes active (Recalibrate).
1.4.2 Drive Selection
Drive selection occurs when the propel:' DRIVE SELECT line is activated. Only the drive with this line jumpered
will respond to Input lines or gate output lines.
1.4.3 Motor On
In order for the host system to read or write data, the dc drive motor must be turned on. This is accomplished by
activating the line -MOTOR ON. A
500 ms delay must be introduced after activating this line to allow the motor to
come up to speed before reading or writing can be accomplished.
The motor must be turned off by the hoslt system by deactivating the MOTOR ON line, The control electronics
keep the motor active for 3seconds,
aliter MOTOR ON is deactivated. This allows reselectlng during copy opera-
tions
and will ensure maximum motor and media life.
1.4.4 Track Accessing
Seeking the read/write heads from one track to another is accomplished by:
a. Activating the DRIVE SELECT line.
b. Selecting desired direction IUslng the DIRECTION SELECT line.
c. WRiTE GATE being inalctive.
d. Pulsing the STEP line.
Multiple track accessing
is accomplished by repeated pulsing of the STEP line (with direction valid) until the desired
track has
been reached. Each pulse on the STEPline will cause the read/ write heads to move one track either in or
out depending
on the DIRECTION SELECT line. Head movement is initiated on the trailing edge of the step
pulse.
1.4.5 Step Out
With the DIRECTION SELECT line at aplus logic level (2.4 to 5.25 V), apulse on the STEP line will cause the
read/write heads to move one track away from the center of the disk. The pulse(s) applied to the STEP line must
have the timing characteristics shown
in 'figures 1-3 and 1-4.
1.4.6 Step In
With the DIRECTION SELECT line at minus logic level (0 to 0.4 V), apulse on the STEP line will cause the.
read/write heads to move one track <:loser to the center of the disk. The pulse(s) applied to the STEP line must
have the timing characteristics shown
in figures 1-3 and 1-4.
1.4.7 Side Selection
Head selection is controlled via the 1./0 signal line designated SIDE SELECT. Aplus logic level on the SIDE
SELECT line selects the
read/write hE!ad on the side asurface of the diskette. Aminus logic level selects the side 1
read/write head. When switching from one side to the other, a 100 p,s delay is required after SIDE SELECT
changes state before a
read or write oper,ation can be initiatE~d. Figure 1-5shows the use of SIDE SELECT prior to
a
read operation.

39239·27
~
6 rna (MIN)'* * ..- -1..,
5_00 ns (MAX) L..._ l......-
_ I~ J-:= 1 p's (MAX)
'- ~ ms (MAXlt -I ~
*18 ma (MAX) for SA465.
**3 rna (MIN) for SA465.
t1 p'sac (M AX) for SA465.
DRIVE SELECT
TRACK 00 DETECT'
POWER
ON "---,
___ ~""""'-:1-10··0-m-. S-(-M-A-X)--------
'-
.r--7-i--:-s-oo-m-S--(M-A-X-). ------
J..~ 2 P.s (MAX)
VALID READ DATA ------,-:.-, ,.------
'~,--- /"
I --l 21 rn.s (MA.X)* ..I.. t.--
j'4-~ 1 P.s (MIN) .. II
DIRECTION ._- .... 'c:::~: -.....,;,----X . X"~--
STEP ',----- .... 1---
FIGURE 1·3. ST'EP TO READ
DRIVE SELECT
VALID WRITE PROTECT
VALID READ DATA
WRITE GATE
,WRITE DATA
DIRECTION SELECT
STEP
SIDE SELECT
-,
·---1I:I"':-:50::0~nS:-:(::MA7:X:-) --------------
-~
~. l.-- 2 P.s (MAX) _I I ~
__ I .. Y 200~S(M'N);·1""---r...;l\~- __-
___ ,__ 500 ns (MAX) t=! 1.1 rns (MAX)
I
.. 1'. --..,' ~1.5rns(MIN).
___ ,__ ~ .1 8 P.s (MAX) J...- 8 p's (MAX)
500
ns (MAX)---I r-- I" I
___ ,_~ ... , ... _ _ ---...j ra- 1/LS (MAX)
" ----~
*18 ms (MAX) for SA465.
• ·SIOE SELECT to VALlD,READ DATA. 39239·20
FIGURE 1-4. WF~ITE TO STEP'
1·6

39239·26
''----
~-.
-~,------"'""'\\-\ ------
~.' .' ... 1500 ms (MAX)
.--1 r-- ,214
S(MAX)
----- ~200~S(MAX) 1.1 m:(MAX)-!
"II I
100 ~s (MIN) Iq :'
~ ""'500 NS (MIN)
~ \~ I'
-l r8 ~s (MAX)
I-----~'-.)r I
8 I4
S(MAX)
..:::t r---
WRITE GATE
MOTOR ON
SIDE SELECT
POWER ON
DRIVE SELECT
VALID READ DATA
WRITE TRANSITIONS
FIGURE 1·5. READ TO WRITE (FM)
1.4.8 Read Operation
Reading data from the SA455/465Is accomplished by:
a. Activating the DHIVE,SELECT line.
b, Selecting the heCld.
c, WRITE GATE blaing inactive.
The timing relationships requinad to initiate aread sequence are shown in figure 1-5. These timing specifications
are required in order to guarantee that the position of the read/write heads has stabilized prior to reading.
The timing of Read Data
(FM) is shown in figure 1--6.
39238·05
A=LEADING EDGE OF BIT MAY BE :t: 80008 FROM ITS NOMINAL POSITION
B=LEADING EDGE OF BIT MAY
BE ± 40008 FROM ITS NOMINAL POSITION
FIGURE 1·6. READ DATA TIMNG (FM)
1-7

The encoding scheme of the recorded data can be either FM or MFM. FM encoding rules specify aclock bit at the
start of every bit cell and a data bit at the center of the bit cell if this cell contains a one data bit. (see figure 1-7).
MFM encoding rules allow clock bits to be omitted from some bit cells with the following prerequisites:
a.
The clock bit is omitted from the current bit cell If either the preceding bit cell or the current bit
cell contains a
one data bit. See figure 1-7.
b. In the above mentioned encoding schem,~s, clock bits are written at the start of their respective
bits cells
and data bits at the centers of their bit cells.
~~LLS l ... l~
o ~ __ o __ .. __ o __ ... _o ·_I .. __ o __
39238·06
o
DOD 0
FM n....n.JL..n...n
I I. .J 1F 1_. ~",'"
~ 2F r-- ...., I ",'
I ",
I '"
I /
I ",'"
I /
, ",
~~LLS= ///
: //
I0 0 0 [). . D. ",
MFM ··IJt.JLJ1----fL.-fl-.n..-n._; ",
tvt 1--
1
F-.f
FIGURE 1·7. FM AND MFM CODE COMPARISONS
1.4.9 Write Operation
Writing data to the SA455/465 is accomplished by:
a. Activating
the DRIVE SELECT line.
b. Selecting
the head.
c. Activating the WHITE GATE line.
d. Pulsing the WRITE DATA line with the
data to be written.
The timing relationships required to Initiate aWrite Dalta sequence are shown In figure 1-5. These timinrJ specifica-
tlonsare required in order to guarantee that the position of the read/write heads has stabilized prior to writing.
The timingspecifications for the write data pulses are shown In figure 1-8. Write data encoding can be FM or MFM.
The write data should be precornpensated 250 ns starting at track 22 (SA455) or track 40 (SA465) to counter the
effects of
bit shifL The direction of compensation required for any given bit In the data stream depends on the pat-
tern
It forms with nearby bits.
1.4.10 Sequence of Event~i
The timing diagrams shown in figures 1-3, 1-4. 1-5. and 1-9 show the necessary sequence of events with
.associated timing restrictions fOli proper operation.
1-8

WRITE DATA
---uJ~
I I. 200 n8 MIN I _I
-., ,....-2100 n8 MAX ,....--8.001'8:t 40 nS
I
FIG,URE 1·8. WRITE DATA TIMING (FM)
I _ 4001'8
,....- ±20 ns
39238·12
39238·08·C
POWER ON
MOTOR ON
DRIVE SELECT
DIRECTION
STEP
~100m.
,~-----------
j=. 1 ~. (MIN)
'~~--"1.=i
I . . 11 ~. (MINI
-- -------, y"~ ------
I~ .. 11 ~8(MIN)
FIGURE 1·9. POWER ON TO STEP

SECTION II
ELECTRICAL INTERFACE
2.1 INTRODUCTION
The interface of the SA455/465 can be divided Into two categories:
a. Signal Lines
b. Power Lines
The following sections provide the electrical definition for each line.
See figure 2-1 for all Interface connections.
HOST SYSTEM DRIVE
J1
SPARE SIGNAL, LINE 2
SPARe SIGNAL. LINE 1
!
_.
III 4
DRIVE SELECT 43
~-
III 6
INDEx/SECTOR 5
~,
-87
DRIVE SELECT 1
1'---'
10
---
9
1--'
DRIVE SELECT 2 '
12
-.
11
DRIVE SELECT 3
14
~.
III
13
_.
MOTOR QIN
16
-
15
DIRECTION S:ELECT
1tJ
-
-
17
..
STEP 20
_.
-
19
WRITE DATA
_.
.-
22
WRITE GATE
21
FLAT RIBBON
OR TWISTED
'-'
III
24
23
PAIR
TRACK 00
f+-.
26
25
/7-! r-t-'
WRITE PROTECT
28
AC -27
READ DATA
GND
14-:.-
30
SIDE SELE,CT
29
'-'
32
READY
31
f4-.
34
-33
TWISTED +5
VDC:
J2
PAIR
1---'
4
+12 VDle 3
1---'
1
.2
-
rh
"'::..."-
-~
--
LOGIC "FRAME LOGIC
GND
GROUND
GND
;
FI(~URE 2·1. INTERFACE CONNECTIONS
39236·0Q·A

2.2 SIGNAl.. INTERFACE
The signal Interface consists of two categories:
a. Control Lines
b. Data Transfer Lines
All lines In the signal interface are digital in nature and either provide signals to the drive (Input). or provide signals
to the host (output). via Interface connector Pl /J 1.
2.2.1 Input Lines
The input signals are of three types: those intended to b,~ multiplexed in amultiple drive system. those which will
perform the multiplexing, and those signals which are not multiplexed and affect all the drives in ?1 daisy chain
system. .
The Input signals to
be multiplexed are:
a. DIRECTION SELECT
b. STEP
c. WRITE DATA
d. WRITE GATE
e. SIDE SELECT
The Input signals
which are Intendep to do the multlple,<Ing are:
a. DRIVE SELECT 1
b. DRIVE SELECT 2
c. DRIVE SELECT 3
d. DRIVE SELECT 4
MOTOR ON is not multiplexed.
.. .
The Input lines have the following electrical specifications. See figure 2-2 for t~e recommended circuit.
True =
L<?gical zero = Vln ±0.0 to +0.4 V@ lin =40 mA (max)
False =togl~al. an'e = Vln +2.5 to +5.25 V@ lin =: 250 JlA (open)
Input
Imped~nce =150 ohms
-1
MAX 10 FEET ~
RIBBON OR
.TWISTED PAIR .
-
-39238·10
FIGURI: 2 .. 2. INTERFACE SIGNAL DRIVER/RECEIVER

2.2.2 Input Line Terminations
The SA455/465 has been provided with the capablllty of terminating the ten input lines listed below.
1. DRIVE SELECT 1
2.
DRIVE SELECT 2
3.
DRIVE SELECT 3
4.
DRIVE SELECT 4
5. MOTOR ON
6. DIRECTION SELECT
7. STEP
8.
WRITE DATA
9. WRITE GATE
10. SIDE SELECT
These lines are terminated through a150 ohm resistor pack.
In asingle drive system, this resistor pack should be
kept in place to provide the proper terminations.
In amultiple drive system, only the ll:\st drive on the interface is to be terminated. All other drives on the Interface
must have the resistor pack removed. External terminations may also be used. However, the user must provide
the terminations beyond the last drive and each
of the five lines must be terminated to +5 V dc through a150
ohm.
1/ 4-watt fCslstor.
2.2.3 Drive Select 1- 4
The SA455/465. as shipped from the f.actory, is conflgureld to operate In asingle drive system. The SA455/465
can be easily modified by the user to operate with other drives In amultiplexed multiple-drive system.
In C1 multiple drive system. the four input lines (DRIVE SELECT 1through DRIVE SELECT 4) are provided so that
the w
.. lng system may select which drive on the Interface Is to be used. In this mode of operation. only the drive
with it!; DHIVE SEI.ECT line active will fCspond to the Input lines and gate the output lines.
2.2.4 .Motor On
This Input. when activated to a logical zero level, wilt turn on the drive motor allowing reading or writing on the
drive. A500
ms delay after activating this line must be allowed before reading or writing. This line should be deac-
tivated.
for maximum motor life. if no commands have be:en Issued to the drives within 2seconds (10 revolutions
of the media) aher completion of aprevious command.
2.2.5 Direction Select
This Interface line defines the dlrectlion of motion the read/write heads will take when the STEP line Is pulsed. An
open circuit or logical one defines the direction as out. If apulse Is applied to the STEP line, the read/write heads
wlll move away from the center of the disk. Conversely, If this Input Is shorted to ground or a logical zero level, the
direction
of motion Is defined as In. If l8 pulse is applied tn the STEP line, the read/write heads wilt move towards
the center
of the disk.
2.2.6 ~tep
Thislnte,rface line is acontrol signal which causes the read/write heads to move in the direction of motion defined
by the DIRECTION SELECT line. This signal must be a logical low going pulse with aminimum pulse width of l/ls
and then logically high for 5ms minimum between adjaclent pulses. Each subsequent pulse must be delayed by 6
ms (SA455) minimum or 3 ms (SA465) minimum from the preceding pulse.
The access'motion
Is Initiated on each logical zero to logical one transition. or at the trailing edge of the signal pulse.
Any change in the DIRECTION SELECT line must be made at least 1 p.s before the trailing edge of the STEP pulse.
The
DIRECTION sE.LECT logic level must be maintained 1 JlS after the trailing edge of STEP pulse. See figure 2-3
for these timings.
2.2.7 Write Gate
The active state of this signal, or 10!~ical zero, enables write data to be written on the diskette. The Inactive state or
IOHlcal onc. enables the read data logic and stepper logic. See figure 2-4 for timings.
2:-3

WRITE GATE -- - ~ - ~f-
------
FIGURE 2·3. STEP TIMING
"'1 P.s MIN
39238·11·A
....-1 P.s MIN
REVERSE
I
--..J ..-1 P.s MIN
-.1
STEP
DRIVE SELECT ----- ......L
L- ,~
1 pS MIN --+ I.,..;.....
-l.J1fV
1 ps MIN ~ 1_"""1.· .. ' 1 ....
5
rns MIN
~ . j.-- 6 rns MIN (SA4551
3ms MIN (SA465)
DIRECTION SELECT
WRITE DATA
I., 400 P.s
r-- ±20 ns
F'IGURE 2·4 •. WRITE DATA TIMING 39238·12
2.2.8 Write Data
This Interface line provides the data to be: writt~n on the disketh~. Each transition from alogical one to alogical zero
level, wtll cause the current through thE! read/write heads to be reversed thereby writing adata bit. This line is
enabled by WRITE GATE being active. 'Write: dat~ must·be InaiCtlve during a read operation. Awrite data clamp is
provided on the PCB at the Interface which holds tha" WRITE DATA line at alogical zero whenever WRITE GATE
. Is, .inactlve. See figure 2-4 for timings. '~
2.2.9 Side Select
. I
jThls signal defines which side of atwo-sided diskette'is to be written on or read from. Alogical one selects the side
··O:Head. When switching from one side to the'oth~r:a; 100tts delay Is required before a read or write operation can
beinitlated. :
-;;/~"- .. ',,' -.
·~.~.10 Outpu,t Lines
. f.';"':
The output control lines. have the follov/lng ~lectrlCal spe~lflcations.
,;rr~e =Logical zero =+ 0.0 to + 0.4 V@ lout = 40 rnA (max)
I;,~,/."
.false .=lLoglcal one == +5to + 2.5 V(open collector) @lout = 250 ttA (max)
2·4

2.2.11 Track 00
The active or logical zero state of this interface signal Indicates when the read/write heads are positioned at track
zero
(the outermost track) and the ac,cess circuitry Is driving current through phase A of the stepper motor. This
signal Is at a logical one level, or inactive state, when thE~ read/write heads are not at track zero. When the
read/write heads are at track zero and anadditlonal step out pulse
is issued to the drive, amechanical stop will
keep the read/write heads at track zero. However, the TRACK 00 signal will go Inactive. This is because the step-
per motor
wilt go to phase Cand not phase A. One more step out pulse wltl put the stepper motor back Into phase
Aand the
TRACK 00 signal wltl go c:lctlve again.
2.2.12 Index/ Sector
This interface signal is provided by th4a drive each time an index or sector hole is sensed at the Index/Sector photo
detector. Normally,
this signal is at a logical one level and makes the transition to the logical zero level each time a
hole
is sensed.
When
using SA154/164 media (soft sectored). there wltl he one pulse on this Interface signal per revolution of the
diskette (200
ms). This pulse indicates the physical beginning of atrack. See figure 2-5 for the timing.
--u--
I.. 200 ±4 ma
U
.. I39238·13·A
FIGiURE 2-5. INDEX TIMING (SA154/164 MEDIA)
When using SA155/165 or SA157/167 media (hard sectored). there will be 17 or 11 pulses on this Interface line
,per revolution (200 ms). To Indlcat<:! the beginning of atrack, once per revolution there Is one Index transition bet-
ween 16 or 10 equally spaced sector transitions. The timing for these signals Is shown In figures 2-6 "nd 2·7,
When using the Index/Sector signal, look for an edge or transition rather than a level for determining the status.
,
With no diskette Inserted, this signal remains active or at a logical zero level which is an erroneow; status.
12.50 ma
6.25 :1:
0.325 ma
0.5 ma MIN 39238·14
39230·15
2.2.13 Read Data
FIOURI: 2 .. 6. INDEx/SECT()R TIMING (SA155/165 MEDIA)
~R9 "I" SECTOR 10~CTOR 2
¥S I
~.o.o~-I
0.72 ms 0.35 ma
FIGURE: 2-7. INDEX/SECTOR TIMING (SA1571167 MEDIA)
This Interface line provides the raw data (clock and data together) as detected by the drive electronics. Normally,
this signal Is a logical one level and becomes a logical zero level for the active state. Seeflgure 1-5 for the timing
and bit shift tolerance within normal media variations.
2··5

2.2.14 Write Protect
This interface signal is provided by the drive to give the user an indication when awrite protected diskette Is instal1~
ed. The signal 15 logical zero level whe~n It is protected. Und4~r normal operation, the drive will Inhibit writing with a
protected diskette Installed
In addition to notifying the Interface.
2.2.15 Ready
READY informs the controller that a dlskE~tte Is properly Inserted and that the drive motor Is up to speed. 500 ms is
required for starting the motor and an additional 200 ms is required for one revolution at the rated speed. Thus.
READY is available 700 ms after pow(~r Is applied to the motor. The SA455/465 generates READY by sensing in-
dex pulses and measuring their frequency of occurence. When the index pulses are 200 ms apart. READY
becomes active.
2.3 POWER INTERFACE
The SA455/465 requires only dc power for operation. DC power to the drive is provided via P2/ J2. The two dc
voltages. their specifications.
and theil: P2/ J2 pin designatolrs are outlined in table 2-1. The specifications outlined
on current requirements are for one drive. For multiple drive systems. the current requirements are amultiple of
the maximum current times
the number of drives In the system.
T~~BL.E 2·1. DC POWER REQUIREMENTS
-
~
P2 PIN
DC VOLTAGE TOLERANCE CURRENT MAX RIPPLE (p
to p)
-
1+
12 VDC ±1.2 VDC 1.2 AMAX 50 mV MAX ALLOWABLE
i0.6 ATYP
-
2+
12 RETURN
.-
3f5RETURN-
4
+5VDC
:!: 0.25 VDC.
0.9 AMAX 50 mV MAX ALLOWABLE
0.6 ATYP
39238·17·A
2.4 FRAME GROUND
It Is Important that the drive be framC:l grounded to the host system ac ground or frame ground. Failure to do so
may result in drive noise susceptibility.

SECTION III
PHY~.I(:AL INTERF:ACE
3.1,,;;JNTRODUCTION
Theefectrlcal Interface between the SA455/465 and the host system Is via two connectors. The first connector.
Jl. provides the signal Interface. The second connector. J2. provides the dc power.
This section describes the physical connectors used on the drive and recommended connectors to be used with
them, See figure 3-1 for connector locatloml.
P1 CONNECTOR
SCOTCHFLEX PIN
3463·0001 OR
AMP PIN 583717-5
P2 CONNECTOR
AMP PIN 1-480424·0
tCEV
FRAME CONNECTOR
AMP PIN 60912·1
DRIVE
FRAME GFIOUND
AMP PIN 61664·1
J2
AMP PIN 350211·1
~92~8·18·A
FIGURE 3·1. INTE:RFACE CONNECTORS PHYSICAL LOCATIONS
3.1.1 J1/P1 Connector
Connection to J 1 is through a 34 pin PCB e:dg~~ connector. The dimensions for this connector are shown in figure
3-2 .. The pins are numbered 1through 34 with the even numbered pins on the component side of the PCB. The
oddnumbered pins are on the non-component side. Pin 2 is located on the end of the PCB connector closest to
thesorner and is labeled 2. Akey slot Is provided between pins 4 and 6for optional connector keying.
3.1.2 J2/P2 Connector
The dc power conhector. (J2. is a 4 pin AMP Mate·N-Lok connector (PIN 350211-1). The recommended mating
contierlm. P2. is AMP PIN 1-480424·0 usin~J AMP pins PIN 61473·1. J2. pin 1. Is labeled on the component
side of the PCB. Wire used should be 1118 AV·iG. Figure 3-3l\1ustrates the J2 connector as seen on the drive PCB
from the non-component side.
3-1

39238·19
r---0.063 NOM (2 x)
(1.6)
BOARD THICKNESS 0.062 ±0.007
(1.6 ±0.2)
FIIGURE 3·2. J1 CONNECTOR DIMENSIONS
x.xx ± x.xx = In.
(x.xx ± x.xx) = mm
KEY sLor--II--'0.036 ±0.004
(0.9 ± 0.1~
...... ~~ .1
f0.450 ±0.010 II
0.40 ±0.010 (11'j ± 2.5) ::
(10.2 ±0.3) t
L-............. _-. . ........-""----_~~~
_ ~-:i1=O.O~~.~OM ~ ~0.1JM
....... 11-- ,_ (1.3) 1.795 ± O.l)05 (2.5) ::
(45.6 ±0;13)
NOTE:
+12 VD(~
+5VDC
39211·16
FIGURE 3·3. J:2 CONNECTOR
3.2 FRAME GROUNDING
CAUTION
The SA455/465 must be frame grounded to the host system to ensure proper opera-
tlon. If the frame of the: drive Is not fastened directly to the frame of the host system
with a good ac ground, awire from the system ac frame ground must be connected to
the SA455/465. For this purpose, afaston tab is provided on the drive near the
motor control PCB whe:re afaston connecj~or can be attached or soldered. The tab is
AMP PIN 61664-1 and its mating connector Is AMP PIN 60972-1.
3-2

SECTIO:N IV
THEORY OF OPERATION
4.1 THEORY OF OPERATION
The SA455/465 floppy diskette driv·e electronics are packaged on one PCB which contains:
a. Read/Write Amplifier iand Transition Detector
b. Spindle
Motor Control
c. Drive Select Circuits
d. Index Detector Circuit!;
e. Track Zero Circuits
f. Track Accessing Circuits
g. Power On Reset Control
h. Write Protect Circuits
I. Drive Status Clrc:ults
The head positioning actuator move's the,
read/write head (5) 'to the desired track on the diskette. The head (5) Is
loaded onto the diskette when the c100r Is closed.
The following paragraphs describe
€~ach of the above functions In detail.
4.2 READ/WRITE OPERATIONS
a. The SA455/465 uses the double frequency non return to zero (NRZ) recording method,
b. The
read/write head, In general. Is aring with agap and acoil wound at some point on the
ring.
c. During awrite operation. abit
Is recorded when the flux direction in the ring Is reversed by
rilpldly reversing the current In the call.
d. During aread operation. abit
is read when the flux direction In the ring is reversed as aresult of
aflux reversal on the! diskette surface.
The SA455/46[) drives use the double-frequency (2F) longitudinal NRZ method of recording. Double frequency IS
the term given to the recording system that Inserts aclock bit at the beginning of each bit cell thereby doubling the
frequency
of recorded bits. This clock bit. as well as the data bit. is provided by the using system. See figure 4-1,
CDC 'D C C CDC CDC
JlJ1..J1J1....f'1-..fL.
.....
r---
- - "-
3BIT CELL 4BIT CELL 5BIT CELL 6BIT CELL 7
1010
ELL
o
-.-
BIT CELL 0BIT
CE,LL ~ BIT CELL 2BIT C
-
110
BINARY
REPRESENTATION
39211·17
HEX \
REPRESENTATION "------
r
c
./\~---......,.------/
I
A
FIGURE 4·1. BYTE
4·1

4.4 WRITE CIRCUIT OPERATI'ON
a. The write data trigger flips with each pulse on the WRITE DATA line.
b. The write data trigger alte:rnately drives one or the other of the write drivers.
c. WRITE GATE allows write current to flow to the write driver circuits If the diskette is not write
protected.
d.
Write current sensed aUows erase coil current.
e. Heads are selected
by grounding the appropriate center tap.
WRITE DATA pulses (clock and data bits) are supplied by the using system. The write trigger "flips" with each
pulse. The outputs are
fed to alternate write drivers.
WRITE GATE and NOT WRITE PROTECT are ANDed together and will cause write current to flow to the write
drivercircuits. which In turn causes the center tap switch to dose and erase current to flow after the turn on delay of
400 J.tsec.
The output of one of the write drivers allows write cutrent to flow through one half of the read/write coil. When the
write trigger "flips." the other write driver provides write current to the other half of the read/write coil.
The removal of WRITE GATE causes the turn off delay circuit to time out for 1.1 ms. At the end of the delay. the
center tap
switch opens and the eral>e current source Is turned off. See figure 4-7.
2
12
R54
1 751%
t--'--5V
,13
1
~
3 GND
C31 -
412 GND
T
C32
,
~'_---+-+-:--'_--W.-.!- H0 0CT
t-4---_.--:-- ....... 1......----,--W-fL HD 1CT
1--..JV\I\r----:.---'-.-'V\.1'V-t~12 HA ~ NC
~1 GND
-3~239.01
118
12A
1445
n5 V DP3 DP1
IM002W1r DAP201 DAP201
~
10 ~ R55 M001Wr j--::--, •_. --,
4.7K
4
9; .... ~I--..-----...--~l:
12 0Q jJ__ ~--t-"f-+--+--+_-.....-~_LJ .• , ,
~"",1>--6 __ 11_1 T 98 IlA56 I ~-_:
~ RQ ~U- ~7K 5 6: I ;- ---ll<-'~'-~'
13 : LaJ-+I~--+-+--f-"":'---+-M1l-'
7 }._~:: I ;-:9 RW10
8150 1% ,,-_~.4 5 RW20
14 6RW11
RW21
ERASE 0
4 ERASE 1
FIGURE 4~·7.WRITE CIRCUIT

4.5 READ CIRCUIT OPERATION
a. Duration of all read operations is under control of the using system.
b. As long as the drive i:s selected and WRITE GATE Is not active, the read signal Is amplified and
shaped and the square wave signals are sent to the Interface as
READ DATA.
When the using system requires data from the dlsketh! drive, the using system must select the head and disable
WRITE GATE. The read signal lis then fed to the amplifier section of the read circuit. After amplification. the read
signal Is fed to a filter where the~ out of band noise is removed. The read signal Is then fed to the dlfferentiator
amplifier.
Since aclock pulse occurs at least once every 8
p.s and data bits are present once every 4/A.s, the frequency of the
READ DATA varies (FM encoding only), The read signal amplitude decreases as the frequency increases. Note
the signals
in figure 4-8. The dlflfere!ntlal amplifier will amplify. differentiate. limit. and digitize the read signals (sine
waves).
39211·24
- READ DATA
LSI
l.-.ot----f READ + READ ENABLE
"----,----4 CH IP
+5 V REG
'----+-+---1-+
---.- ..... -+
The drive has no data separato:r. only apulse standardizeI' for the READ DATA signal.
ERASE 1 -- ...,
ERASE 0+ 12V
r -1+--
I
I
SIDE 0I
I
r-
I
I
SIDE 1I
I
L __
SELECT1------~
SELECT 0------'
FIGURE 4·8. READ CIRCUIT
4.6 DRIVE MOTOR CONTROL
a. Start/Stop
b. Speed Control
c. Over Current Protection
d. Speed Adjustm,mt
The motor used in the SA455!',l~65 is a de drive motor with aseparate motor on and off interface line. After ac·
'tivatlng the
MOTOR ON line. a500 ms delay must be introduced to allow proper motor speed before reading or
writing.
When
MOTOR ON Is activated at: pin 16 of the Interface. the mode will start by means of current flow through the
motor windings. The motor speed control
utilizes an integral brushless tachometer. The output voltage signal from
this tachometer is compared to avoltage/frequency reference level. The output from the voltage/frequency com-
parator
will control the necessary current to maintain aconstant motor speed of 300 rpm. Motor speed adjustment
changes the voltage
reference! through apotentiometer. .
4·5