Redpine Signals RS9110-N-11-22 Quick setup guide

Redpine Signals, Inc. Proprietary and Confidential
RS9110-N-11-22 –Wireless Device Server
Module Integration Guide
Redpine Signals, Inc.
2107 N. First Street, #680
San Jose, CA 95131.
Tel: [phone]
Fax: [phone]
Email: [e-mail]
Website: www.redpinesignals.com
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Part Number Descriptions
Device Number
Description
RS9110-N-11-22-04
Part with UART/SPI as
Host Interface
RS9110-N-11-22-05
Part with UART/SPI as
Host Interface and uFL
connector for external
antenna
Errata/Changes:
Version
No
Corrections
1.8
Changed UART TX/RX pin connections
in MAX3232 part in UART schematics.
Pin 11 is UART TX, pin 12 is UART RX
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Table of Contents
1RS9110-N-11-22 (UART) Reference Schematics .................. 7
1.1 RS9110-N-11-22 (UART) Bill of Materials ............................. 8
2RS9110-N-11-22 (SPI) Reference Schematics ..................... 9
2.1 RS9110-N-11-22 (SPI) Bill of Materials .............................. 10
3RS9110-N-11-22 PCB Landing Pattern............................... 12
4u.FL Connector for External Antenna ................................. 13
5Sample Layout ................................................................... 14
5.1 Top Layer............................................................................ 14
5.2 Bottom Layer ...................................................................... 15
5.3 Component Placement on mother PCB................................ 16
6Circuit and Layout Guidelines ............................................ 17
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Table of Figures
PCB Landing Pattern for RS9110-N-11-22 .................................................. 12
u.FL Connector on module [Part no. Hirose U.FL-R-SMT(01)] .................... 13
External Antenna ....................................................................................... 13
Top Layer of RS9110-N-11-22 .................................................................... 14
Bottom Layer of RS9110-N-11-22 .............................................................. 15
Component Placement ............................................................................... 16
Reference Antenna Layout ......................................................................... 18
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1RS9110-N-11-22 (UART) Reference Schematics
UART_TX
Title
Size Document Number Rev
Date: Sheet of
RS9110-N-11-22 Reference Design-UART
Custom
1 1Thursday, December 30, 2010
C23
10uF
Reset_n
UART_TX
UART_RX
Power_enable
J1
Micro Controller
DPDT(OP TI ONAL)
C4
0.1uF
R12 100K
VMOD
UART_RX
RESET_n
4
NC
19
NC
22
JPD2
44
JPD0
42
JPD1
43
JNC
45
SPI_CS
52
SPI_CLK
51
SPI_MOSI
1
SPI_MISO
2INTR
3
UART_RX
7
UART_TX
5
NC
9
NC
14
NC
18
NC
8
NC
11
NC
24
NC
15
NC
49
NC
50
NC
23 GND 21
GND 48
GND 10
GND 16
GND 20
NC 17
NC 13
NC 12
NC 25
NC 26
NC 27
NC 28
NC 29
NC 30
NC 31
NC 32
NC 33
NC 34
NC 35
NC 36
NC 37
NC 38
NC 39
NC 40
NC 41
VIN33 46
VIN33 47
SD3
6
U2
RS9110-N-11-22 Pinout
Reset_n
R3 1K
R6**
VMOD
R13
0E
Power Switch Optional
C18
0.1uF
DB9_TXD
UART Circuitry
C19
0.1uF
GND 15
VCC 16
R1IN 13
R2IN
8T2IN 10
T1IN 11
C1+
1
C1-
3
C2+
4
C2-
5R1OUT 12
R2OUT 9
T1OUT 14
T2OUT
7
V+
2
V-
6
U4
MAX3232CDBR
C20
0.1uF
C21
0.1uF
C22
0.1uF DB9_RXD
UART_RX
UART_TX
VCC33
OPTIONAL
Optional
DB9_TXD
DB9_RXD
5
9
4
8
3
7
2
6
1
P1
DB9_FEMALE
VIN
4
VOUT 3
VOUT 2
R2 1
R1,C1
6
VON/OFF
5
U3
FDC6329L
R2
20K
C1
0.1uF
R9
10K(NP)
R10
100K
Power_enable
VCC33 C2 1000pF
R11
2K
a
1b2
PB1
VMOD
C6
10uF
This value should be
between 1K to 10K
R6**
UART_TX
UART_RX
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1.1 RS9110-N-11-22 (UART) Bill of Materials
Item
Qty
Reference
Part Value
Description
Jedec
Mfg/
Part No
CAPACITORS
1
1
C23
10uF
Tant.Cap 10uF 20% EIA
6.3V CASE-B
CASE-B
AVX
TAJB106M006RNJ
RESISTORS
2
1
R13
0E
CHIP RES 0.0R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GE0R00X
3
1
R3
1K
RES 1.0K OHM 1/10W 5%
0402
Panasonic
ERJ-2GEJ102X
4
1
R6
1K to 10K
ICs
5
1
U2
RS9110-N-11-
22
802.11bgn WLAN Module
LGA
Redpine
RS9110-N-11-22
6
1
J1
Micro controller Header
Burg Header
Optional.
7
1
DPDT switch
SW DPDT
CTS Corpo.
204-221ST
8
1
PB1
2 Pin headers
Burg
9
1
P1
CONNECTOR DB9_FEMALE PCB Mount
Dip
10
1
U4
RS232
UART Level Shifter
SSOP
Texas Instr.
MAX3232CDBR
11
1
U3
FDC6329L
DC-DC Switch
SSOT-6
Fairchild Semi.
FDC6329L
12
1
C1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
13
2
C3, C6
10uF
Tant.Cap 10uF 20% EIA 6.3V CASE-B
CASE-B
AVX
TAJB106M006RNJ
14
1
C2
1000pF
CER CHIP C 1nF +/-10% X7R 0402 50V
0402
Murata
GRM155R71H102KA01D
15
5
C18, C19, C20, C21, C22,
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
16
1
C4
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
17
1
R2
20K
CHIP RES 20K 1% 100PPM 0402 1/16W
0402
Yageo
RC0402FR-0720KL
18
2
R10, R12
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ104X
19
1
R11
2K
CHIP RES 2K 5% 200PPM 0402 1/10W
0402
Yageo
RC0402JR-072KL
20
1
R9
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ103X
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2RS9110-N-11-22 (SPI) Reference Schematics
VIN
4
VOUT 3
VOUT 2
R2 1
R1,C1
6
VON/OFF
5
U2
FDC6329L
R8
20K
C1
0.1uF
R9
10K(NP)
R10
100K
VCC33
C2
1000pF
R11
2K
a
1b2
PB1
VMODR4
3.9K to 4.75K
R5**
Reset_n Reset_n
4
NC
19
MODE_SEL1
22
JPD2
44
JPD0
42
JPD1
43
JNC
45
SPI_CS
52
SPI_CLK
51
SPI_MOSI
1
SPI_MISO
2
INTR
3
UART_RX
7
UART_TX
5
NC
9
NC
14
NC
18
NC
8
NC
11
NC
24
NC
15
NC
49
NC
50
NC
23 GND 21
GND 48
GND 10
GND 16
GND 20
NC 17
NC 13
NC 12
NC 25
NC 26
NC 27
NC 28
NC 29
NC 30
NC 31
NC 32
NC 33
NC 34
NC 35
NC 36
NC 37
NC 38
NC 39
NC 40
NC 41
VIN33 46
VIN33 47
SD3
6
U1
RS9110-N-11-22 Pinout
R2 1K
VMOD
Reset_n
SPI_CS
SPI_CLK
SPI_MOSI
SPI_MISO
INTR
NC
Power_enable
J1
Micro C ontroller
Power_enablePower_enable
C4
0.1uF
R6 100K
VMOD
Power Switch Optional
C5
10uF
R7
0E
Title
Size Document Number Rev
Date: Sheet of
RS9110-N-11-22 Reference Design-SPI
Custom
1 1Thursday, December 30, 2010
OPTIONAL
C8
10uF
R5**
This value should be adjusted based
on driver output impedance and PCB
Trace Impedance,,(33E is Nominal)
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2.1 RS9110-N-11-22 (SPI) Bill of Materials
Item
Qty
Reference
Part Value
Description
Jedec
Mfg/
Part No
CAPACITORS
1
1
C5
10uF
Tant.Cap 10uF 20% EIA 6.3V CASE-B
CASE-B
AVX
TAJB106M006RNJ
RESISTORS
2
1
R2
1K
RES 1.0K OHM 1/10W 5%
0402
Panasonic
ERJ-2GEJ102X
3
1
R5
33E
CHIP RES 33R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ330X
4
1
R7
0E
CHIP RES 0.0R 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GE0R00X
5
1
R4
3.9K To 4.75K
6
ICs
7
1
U1
RS9110-N-11-
22
802.11bgn WLAN Module
LGA
Redpine
RS9110-N-11-22
8
1
J1
Micro controller Header
Burg Header
Optional.
9
1
U2
FDC6329L
DC-DC Switch
SSOT-6
Fairchild Semi.
FDC6329L
10
1
PB1
2 Pin headers
Burg
11
1
C1
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
12
1
C2
1000pF
CER CHIP C 1nF +/-10% X7R 0402 50V
0402
Murata
GRM155R71H102KA01D
13
2
C3, C8
10uF
Tant.Cap 10uF 20% EIA 6.3V CASE-B
CASE-B
AVX
TAJB106M006RNJ
14
1
C4
0.1uF
CER CHIP C 0.1U 10% X5R 0402 10V
0402
Murata
GRM155R61A104KA01D
15
1
R6
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ104X
16
1
R8
20K
CHIP RES 20K 1% 100PPM 0402 1/16W
0402
Yageo
RC0402FR-0720KL
17
1
R9
10K
CHIP RES 10K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ103X
18
1
R10
100K
CHIP RES 100K 5% 200PPM 0402 1/10W
0402
Panasonic
ERJ-2GEJ104X
19
1
R11
2K
CHIP RES 2K 5% 200PPM 0402 1/10W
0402
Yageo
RC0402JR-072KL
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NOTE: 1.The Power Switch section in the Reference Schematics is shown for guidance to the PCB designer in case
the usage of such a part is required in the system. C2 in the schematic above may range from 1000pF to 1uF to
allow for a transient inrush current when the module is powered on ( a worst-case maximum of 800mA for a
maximum of 40 usec). Alternatively, a capacitor ranging from 100uF to 400uF can be used at the output of the
power supply, depending on the current sourcing capabilities of the power supply. The values recommended here
include a reasonable safety margin as well.
2. The design of the system should provide for a peak current load of 325mA, which can be sustained when the
module is transmitting at the highest physical data rate and highest RF output power. The number indicated here
includes a safety margin as well.
3.For SPI modules, based on the Host SPI configuration, during BOOT UP, SPI Master in the Host could be coming
up as GPIO pins. In such a case, it may be necessary to add a pull up on the module’s SPI_CS and a pull up
(CPOL=1)/pull down(CPOL=0) on the SPI_CLK. The value of pull up/ pull down resistor should follow the
recommendations as given on the HOST side
Signal Integrity Guidelines for SPI interface: Glitches in the SPI clock can potentially take the SPI interface out of
synchronization. The quality and integrity of the clock line needs to be maintained. The following steps are
recommended. Please note that this is not an exhaustive list of guidelines and depending on individual cases
additional steps may be needed.
1. It is recommended to avoid using cables to connect the Host platform with the module’s SPI interface. In case
a cable is used, minimize the length of the SPI bus cable to as small as possible, preferably to within an inch or
two
2. It is recommended to use a companion card with a rigid connector to the host
3. If a cable is used, increase the number of ground connections between the WiFi PCB and the MCU PCB
4. Add a series resistor into the clock line. Choice of value is mentioned in the Module Integration Guide.
5. If the SPI clock line is mapped to a programmable I/O on the MCU, configure that I/O to an output with as
high a drive as is available.
6. Ensure that the Wi-Fi board's reset input is mapped to a MCU controllable line, so that the system can recover
through a hard reset.
* Pin MODE_SEL_1 is used to configure the module in SPI or UART mode.
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3RS9110-N-11-22 PCB Landing Pattern
PCB Landing Pattern for RS9110-N-11-22
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4u.FL Connector for External Antenna
u.FL Connector on module [Part no. Hirose U.FL-R-SMT(01)]
External Antenna
RS9110-N-22-05 comes with a U.FL connector on the module to connect to
an external antenna. The figures show the connector on the module and on
an external antenna. The connector on the external antenna should be
pushed down to fit into the U.FL connector on the module. Some reference
part numbers for external antenna are given below. This is for general
guidance only, as the choice of the antenna will depend on the application.
Manufacturer
Part No
Laird
Technologies
0600-00040
Digi
International
A24-HABUF-P5I
Connectblue
cB-ACC-27
Connectblue
cB-ACC-29
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5Sample Layout
This section provides a sample layout of a board that instantiates RS9110-
N-11-22.
5.1 Top Layer
Top Layer of RS9110-N-11-22
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5.2 Bottom Layer
Bottom Layer of RS9110-N-11-22
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5.3 Component Placement on mother PCB
Component Placement
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6Circuit and Layout Guidelines
The following are guidelines for integrating the RS9110-N-11-22 module
on customer Application boards.
1. The module has a central ground pad of size 2.7mm x 2.7mm.This
enhances the RF Chip’s Gnd contact to the Customers reference board
& also acts as a thermal pad.
a. Please provide a 2.7 mm X 2.7 mm Copper pad on the Top side
of the application board. Please open the solder mask in this
area so that the Cu is exposed.
b. Please provide a 2.7 mm X 2.7 mm or higher Copper pad on the
bottom side of the application board. Please open the solder
mask in this area so that the Cu is exposed.
c. Please provide at least 12 via’s to connect these pads to the
Ground plane. We recommend that the via’s should be at least
10 mil x 18 mil.
2. The reference schematics shown in the previous section include the
recommended power supply filtering and decoupling.
3. For RESET one of the two options should be followed
a. The RESET can be Host driven. At the time of Power-on, Please
ensure that the reset is held low for 20mSec or more. After this
the reset should be driven high
b. Reset may be driven by an R-C circuit. The recommended value
of ‘R’ is 100 Kohms and the recommended value of ‘C’ is 0.1uF
It is strongly recommended that the reset is host driven because
hardware reset is the safest way to recover the module from an
unknown state during its operation
4. Please make sure that the Copper is etched out in all the Layers in the
Antenna region. The Ground plane is removed from under & either
sides of the antenna. Please refer the picture below.
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Redpine Signals, Inc. Proprietary and confidential Page 18
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RS S9 91 11 10 0- -N N- -1 11 1- -2 22 2 – – W Wi ir re el le es ss s D De ev vi ic ce e S Se er rv ve er r
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Mo od du ul le e I In nt te eg gr ra at ti io on n G Gu ui id de e
Reference Antenna Layout
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