Renesas R-IN32M3 Series User manual

Renesas Electronics
www.renesas.com
・
R-IN32M3-CL
UPD60510BF1-HN4-A
UPD60510BF1-HN4-M1-A
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com)
ASSP
Document number: R18UZ0005EJ0400
Issue date: Dec. 28, 2018
R-IN32M3 Series
User’s Manual
Userʼs Manual
ASSP

Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation of these
circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for
any losses incurred by you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas
Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever
for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property
rights of third parties by or arising from the use of Renesas Electronics products or technical information described in
this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other
intellectual property rights of Renesas Electronics or others.
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alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
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as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio
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and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster
systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a
direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may
cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality
grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable
for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for
which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas
Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage
range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no
liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified
ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products
have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to
implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire
in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including
but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or
any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please
evaluate the safety of the final products or systems manufactured by you.
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otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set
forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as
a result of unauthorized use of Renesas Electronics products.
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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its
majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

Instructions for the use of product
In this section, the precautions are described for over whole of CMOS device.
Please refer to this manual about individual precaution.
When there is a mention unlike the text of this manual, a mention of the text takes first priority.
1.Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
- The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in
the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through
current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2.Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
- The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are
undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are not
guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not
guaranteed from the moment when power is supplied until the power reaches the level at which resetting has
been specified.
3.Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
- The reserved addresses are provided for the possible future expansion of functions. Do not access these
addresses; the correct operation of LSI is not guaranteed if they are accessed.
4.Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching
the clock signal during program execution, wait until the target clock signal has stabilized.
- When the clock signal is generated with an external resonator (or from an external oscillator) during a reset,
ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a
clock signal produced with an external resonator (or by an external oscillator) while program execution is in
progress, wait until the target clock signal is stable.
・
Arm®and Cortex®are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
・Ethernet is a registered trademark of Fuji Xerox Co., Ltd.
・IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc.
・TRON is an acronym for "The Real-time Operation system Nucleus".
・ITRON is an acronym for "Industrial TRON".
・µITRON is an acronym for "Micro Industrial TRON".
・TRON, ITRON, and µITRON do not refer to any specific product or products.
・CC-Link and CC-Link IE Field are registered trademarks of the CC-Link Partner Association (CLPA).
・Additionally all product names and service names in this document are a trademark or a registered trademark which
belongs to the respective owners.

How to Use This Manual
1. Purpose and Target Readers
This manual is intended for users who wish to understand the functions of industrial Ethernet network ASSP (application
specific standard product) "R-IN32M3-CL" (UPD60510BF1-HN4-A, UPD60510BF1-HN4-M1-A) for designing
application of it.
It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits,
and microcontrollers.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to
the text of the manual for details.
The mark "<R>" means the updated point in this revision. The mark "<R>" let users search for the updated
point in this document.
LiteratureLiterature may be preliminary versions. Note, however, that the following descriptions do not indicate
"Preliminary". Some documents on cores were created when they were planned or still under
development. So, they may be directed to specific customers. Last four digits of document number
(described as ****) indicate version information of each document. Please download the latest
document from our web site and refer to it.
The document related to R-IN32M3-CL
Document Name
Document Number
R-IN32M3 Series Datasheet
R18DS0008EJ****
R-IN32M3-EC User’s Manual
R18UZ0003EJ****
R-IN32M3 Series User’s Manual (Peripheral Modules)
R18UZ0007EJ****
R-IN32M3 Series Programming Manual (OS edition)
R18UZ0011EJ****
R-IN32M3 Series Programming Manual (Driver edition)
R18UZ0009EJ****
R-IN32M3 Series User’s Manual (Board design edition)
R18UZ0021EJ****
R-IN32M3-CL User’s Manual
This manual

2. Notation of Numbers and Symbols
Weight in data notation: Left is high-order column, right is low-order column
Active low notation:
xxxZ (capital letter Z after pin name or signal name)
or xxx_N (capital letter _N after pin name or signal name)
or xxnx (pin name or signal name contains small letter n)
Note:
Explanation of (Note) in the text
Caution:
Item deserving extra attention
Remark:
Supplementary explanation to the text
Numeric notation:
Binary …xxxx , xxxxB or n’bxxxx (n bits)
Decimal …xxxx
Hexadecimal …xxxxH or n’hxxxx (n bits)
Prefixes representing powers of 2 (address space, memory capacity):
K (kilo)…210 = 1024
M (mega)…220 = 10242
G (giga)…230 = 10243
Data Type:
Word …32 bits
Halfword …16 bits
Byte …8 bits

Contents-1
Contents
1. Overview........................................................................................................................................................1
1.1 Introduction......................................................................................................................................................... 1
1.2 Overview ............................................................................................................................................................ 2
1.3 Internal Block Diagram ...................................................................................................................................... 4
1.4 Pin Assignments (Top View).............................................................................................................................. 5
1.5 Base Addresses of the System Registers Area <R>............................................................................................ 6
2. Pin Functions.................................................................................................................................................7
2.1 List of Pins.......................................................................................................................................................... 8
2.1.1 Ethernet Pins.............................................................................................................................................. 8
2.1.2 External Memory Interface Pins.............................................................................................................. 10
2.1.3 External MCU Interface Pins............................................................................................................... 11
2.1.4 Port Pins and Real-Time Port Pins........................................................................................................... 12
2.1.5 Serial Flash ROM Interface Pins ............................................................................................................. 16
2.1.6 DMA Interface Pins................................................................................................................................. 16
2.1.7 External Interrupt Input Pins.................................................................................................................... 17
2.1.8 Timer I/O Pins ......................................................................................................................................... 17
2.1.9 Watchdog Timer Output Pin.................................................................................................................... 17
2.1.10 Trace Pins ................................................................................................................................................ 18
2.1.11 CPU Power Control Pin........................................................................................................................... 18
2.1.12 Serial Interface Pins................................................................................................................................. 18
2.1.13 CC-Link IE Field Pins (Intelligent Device Station)................................................................................. 19
2.1.14 CC-Link Pins (Intelligent Device Station)............................................................................................... 20
2.1.15 CC-Link Pins (Remote Device Station)................................................................................................... 21
2.1.16 System Pins.............................................................................................................................................. 22
2.1.17 Test Pins .................................................................................................................................................. 23
2.1.18 Operating Mode Setting Pins................................................................................................................... 23
2.2 Pin States .......................................................................................................................................................... 25
2.2.1 Pin States when Booting is from External Memory................................................................................. 26
2.2.2 Pin States when Booting is from External Serial Flash ROM ................................................................. 29
2.2.3 Pin States when Booting is for External MCU ........................................................................................ 32
2.3 Operating Mode Monitoring............................................................................................................................. 35
2.4 Buffer Switching............................................................................................................................................... 35
2.5 Buffer Types and Handling of Unused Pins ..................................................................................................... 36
2.5.1 Ethernet Pins............................................................................................................................................ 36

Contents-2
2.5.2 External Memory/MCU Interface Pins.................................................................................................... 37
2.5.3 External Interrupt Input Pins.................................................................................................................... 37
2.5.4 System Pins.............................................................................................................................................. 37
2.5.5 Test Pins .................................................................................................................................................. 38
2.5.6 Port Pins................................................................................................................................................... 39
2.5.7 Operating Mode Setting Pins................................................................................................................... 40
2.5.8 CC-Link IE Field Pin (Intelligent Device Station) .................................................................................. 40
2.5.9 CC-Link Pin (Intelligent Device Station, Remote Device Station).......................................................... 40
2.5.10 Trace Pins ................................................................................................................................................ 40
3. Memory Maps..............................................................................................................................................41
4. Exception Handling......................................................................................................................................45
4.1 Exceptions List ................................................................................................................................................. 45
4.2 List of Interrupts ............................................................................................................................................... 46
5. Peripheral Modules......................................................................................................................................51
6. CC-Link IE Field (Intelligent Device Station) Function ................................................................................52
6.1 CC-Link IE Field (Intelligent Device Station) Control Registers..................................................................... 52
6.1.1 CC-Link IE Field (Intelligent Device Station) Clock Gate Register (CIECLKGTD) ............................. 53
6.1.2 CC-Link IE Field (Intelligent Device Station) Wait Delay Register (CIEWAITDLY)........................... 54
6.1.3 CC-Link IE Field (Intelligent Device Station) Bus Size Control Register (CIEBSC)............................. 55
6.1.4 CC-Link IE Field (Intelligent Device Station) Bus Bridge Control Register (CIESMC)........................ 55
6.2 Cautionary Notes .............................................................................................................................................. 56
7. Port Functions .............................................................................................................................................57
7.1 Features............................................................................................................................................................. 57
7.2 Port Configuration ............................................................................................................................................ 58
7.3 List of Registers................................................................................................................................................ 60
7.3.1 Port Registers (P, RP).............................................................................................................................. 66
7.3.2 Port Mode Registers (PM, RPM)............................................................................................................. 69
7.3.3 Port Mode Control Registers (PMC, RPMC) .......................................................................................... 72
7.3.4 Port Function Control Registers (PFC, RPFC)........................................................................................ 76
7.3.5 Port Function Control Expansion Registers (PFCE, RPFCE).................................................................. 79
7.3.6 Port Pin Input Registers (PIN, RPIN)...................................................................................................... 82
7.4 List of Selectable Multiplexed Functions ......................................................................................................... 85
7.5 Buffer Switching Registers (DRCTL) .............................................................................................................. 89
7.5.1 Port 0 Buffer Switching Registers (DRCTLP0L, DRCTLP0H).............................................................. 90

Contents-3
7.5.2 Port 1 Buffer Switching Registers (DRCTLP1L, DRCTLP1H).............................................................. 91
7.5.3 Port 2 Buffer Switching Registers (DRCTLP2L, DRCTLP2H).............................................................. 92
7.5.4 Port 3 Buffer Switching Registers (DRCTLP3L, DRCTLP3H).............................................................. 93
7.5.5 Port 4 Buffer Switching Registers (DRCTLP4L, DRCTLP4H).............................................................. 94
7.5.6 Port 5 Buffer Switching Registers (DRCTLP5L, DRCTLP5H).............................................................. 95
7.5.7 Port 6 Buffer Switching Registers (DRCTLP6L, DRCTLP6H).............................................................. 96
7.5.8 Port 7 Buffer Switching Registers (DRCTLP7L, DRCTLP7H).............................................................. 97
7.5.9 Real-Time Port 0 Buffer Switching Registers (DRCTLRP0L, DRCTLRP0H)....................................... 98
7.5.10 Real-Time Port 1 Buffer Switching Registers (DRCTLRP1L, DRCTLRP1H)....................................... 99
7.5.11 Real-Time Port 2 Buffer Switching Registers (DRCTLRP2L, DRCTLRP2H)..................................... 100
7.5.12 Real-Time Port 3 Buffer Switching Registers (DRCTLRP3L, DRCTLRP3H)..................................... 101
7.6 Operation of Port Functions............................................................................................................................ 102
7.6.1 Reading and Writing via I/O Ports......................................................................................................... 102
7.6.2 Multiplexed Function Pin Output State in Control Mode...................................................................... 102
7.7 Trigger-Synchronous Ports (RP00 to RP37)................................................................................................... 103
8. Electrical Characteristics ...........................................................................................................................104

Contents-4
Contents of Figures
Figure 3.1 Memory Map (All).............................................................................................................................. 41
Figure 3.2 Memory Map (APB Peripheral Registers Area) ................................................................................. 42
Figure 3.3 Memory Map (External Memory Area).............................................................................................. 43
Figure 3.4 Memory Map (CC-Link Master Area)................................................................................................ 43
Figure 3.5 External MCU Interface Area............................................................................................................. 44
Figure 6.1 Timing of Data Sampling and Period of Waiting for the Bus of a CC-Link IE Field Network.......... 54
Figure 6.2 Procedure for Switching Access Path to the CC-Link IE Field .......................................................... 56
Figure 7.1 Basic Circuit Configuration of Ports................................................................................................... 59
Figure 7.2 Port Registers (in 8-Bit Notation) ....................................................................................................... 66
Figure 7.3 Port Registers (in 16-Bit Notation) ..................................................................................................... 67
Figure 7.4 Port Registers (in 32-Bit Notation) ..................................................................................................... 68
Figure 7.5 Port Mode Registers (in 8-Bit Notation)............................................................................................. 69
Figure 7.6 Port Mode Registers (in 16-Bit Notation)........................................................................................... 70
Figure 7.7 Port Mode Registers (in 32-Bit Notation)........................................................................................... 71
Figure 7.8 Port Mode Control Registers (in 8-Bit Notation)................................................................................ 72
Figure 7.9 Port Mode Control Registers (in 16-Bit Notation).............................................................................. 73
Figure 7.10 Port Mode Control Registers (in 32-Bit Notation).............................................................................. 75
Figure 7.11 Port Function Control Registers (in 8-Bit Notation)........................................................................... 76
Figure 7.12 Port Function Control Registers (in 16-Bit Notation)......................................................................... 77
Figure 7.13 Port Function Control Registers (in 32-Bit Notation)......................................................................... 78
Figure 7.14 Port Function Control Expansion Registers (in 8-Bit Notation)......................................................... 79
Figure 7.15 Port Function Control Expansion Registers (in 16-Bit Notation)....................................................... 80
Figure 7.16 Port Function Control Expansion Registers (in 32-Bit Notation)....................................................... 81
Figure 7.17 Port Pin Input Registers (in 8-Bit Notation) ....................................................................................... 82
Figure 7.18 Port Pin Input Registers (in 16-Bit Notation) ..................................................................................... 83
Figure 7.19 Port Pin Input Registers (in 32-Bit Notation) ..................................................................................... 84
Figure 7.20 Configuration of Trigger-Synchronous Ports.................................................................................... 103

Contents-5
Contents of Tables
Table 1.1 Overview of R-IN32M3-CL .....................................................................................................................2
Table 2.1 Meanings of the Items in the List of Pins.................................................................................................. 7
Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins .............................................................. 7
Table 2.3 Operating Mode Setting Pins for which the Settings can be Checked.................................................... 35
Table 4.1 List of Interrupts ..................................................................................................................................... 47
Table 6.1 Outline Specifications of CC-Link IE Field............................................................................................ 52
Table 6.2 Overview of CC-Link IE Field (Intelligent Device Station) Control Registers...................................... 52

R18UZ0005EJ0400
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1. Overview
1.1 Introduction
Ethernet communication continues to spread rapidly in the field of industrial automation as manufacturers seek to
improve the capability, efficiency, and flexibility of their organizations. Modern industrial Ethernet applications require
high-speed real-time response, low power consumption, and high performance. These requirements are not necessarily
met by traditional methods such as hard-wired Ethernet processors or dedicated high-speed CPUs.
Renesas R-IN32M3-CL of large-scale integrated circuits (LSI) are specifically tailored to meet the demands of industrial
Ethernet applications. Key features include:
• Integrated Arm®Cortex®-M3 core for flexibility
• Integrated real-time OS accelerator with support for μITRON version 4.0
• Integrated Gigabit Ethernet MAC
• Dedicated DMA controller and buffer for the network processor
• Timers, multiple serial interfaces, general purpose I/O (GPIO), external memory interfaces
• High-speed, real-time, deterministic, low-latency, low-jitter response for real-time applications
• High performance with low CPU usage by offloading functions to real-time OS accelerator
• Low power consumption

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1.2 Overview
Table 1.1 Overview of R-IN32M3-CL
(1/2)
Product
Item
R-IN32M3-CL
CPU cores Arm Cortex-M3 32-bit RISC CPU
+ Real-Time OS Accelerator (Hardware Real-Time OS, HW-RTOS)
Operating frequency
100 MHz
Instruction set
Thumb
®
-2 instruction Arm v7-M architecture
Instruction RAM
768 Kbytes (RAM with ECC)
Data RAM
512 Kbytes (RAM with ECC)
Buffer RAM
64 Kbytes (RAM with ECC)
Internal system bus - 32-bit system bus at 100 MHz
- 128-bit communication bus at 100 MHz
DMA bus (system bus side) - 4 channels + 1 channel (for real-time port)
- Supports software and various interrupt-triggered DMA
Boot options - Serial flash ROM boot
- External memory boot
- External MCU boot
External memory support - 16-bit or 32-bit bus interface
- Page ROM / ROM / SRAM interface
- Synchronous burst memory interface
- Four chip selects for external SRAM
- 256-Mbyte (max) external memory space
- Programmable wait function
External MCU interface - 16-bit or 32-bit bus interface
- General-purpose interface for static memory
- Address space: 2 Mbytes (instruction RAM, data RAM, register area)
Serial flash ROM memory controller - Support serial interface compatible with SPI of the companies
- Support direct boot from serial memory device
- Support Fast Read, Fast Read Dual Output, Fast Read Dual I/O mode
- Direct layout in memory space
Interrupt
- 29 external interrupt pins
Internal peripheral circuit
I/O ports
CMOS I/O: 96 pins (max.)
Timers (three systems)
- Internal timer of Hardware RTOS
- Internal timer of CPU
- 4-channel timer array
- 32-bit counter & 32-bit data register
- Counter by external signal

R-IN32M3-CL User’s Manual 1. Overview
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Dec. 28, 2018
(2/2)
Product
Item
R-IN32M3-CL
Internal peripheral circuit
Watchdog timer - 1 channel
- Software-triggered start mode
- Selectable operations in response to errors:
- Generation of a non-maskable interrupt (NMIZ)
- Generation of a reset
Asynchronous serial interface - 2 channels
- Full duplex
- FIFOs: 10 bits x 16 receive and 8 bits x 16 transmit
- Support output of receive errors and status
- Character length: 7 or 8 bits
- Parity bit options: Odd, even, 0, none
- Transmit stop bits: 1 or 2 bits
I2C serial interface - 2 channels
- Operating modes: Normal or high-speed
- Transfer modes: Single-transfer mode or continuous-transfer mode
- Transmission data length: 8 bits
CAN controller - 2 channels
- Conforming to ISO11898
- Support to transfer and receive normal frame and expand frame
- Transmission speed: 1 Mbps (max.)
Clock synchronous serial interface - 2 channels
- Synchronized serial data transmission by three-wire system
- Selectable master mode or slave mode
- Built-in baud-rate generator
- Transmission data length: 7 bits to 16 bits
CC-Link - Intelligent device stationNote
- Remote device station
10/100/1000-Mbps Ether MAC - 1 channel
- Built-in 2-port switch
- GMII / MII interface
CC-Link IE
CC-Link IE field (intelligent device station)
On-chip debug function - Select serial wire or JTAG
- Support Full Trace (Built-in ETM)
Internal PLL
Generates various clocks from 25-MHz input clock
Power supply voltage I/O: VDD33 = 3.3±0.3 V
Internal circuit: VDD10 = 1.0±0.1 V
Note:
Please contact our sales representative for details.

R-IN32M3-CL User’s Manual 1. Overview
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Dec. 28, 2018
1.3 Internal Block Diagram
R-IN32M3-CL
Cortex-M3
CPU
Debug
NVIC
Hardware
Real-Time
OS
OS
DMAC MEMC
Selector
Serial Flash
ROM
MEMC
Data RAM
512KB(ECC)
Instruction
RAM
768KB(ECC)
Ext_
Micon
Interface
AHB_APB
Bridge
Hardware
Function
Control
Header
Endec
Ether
SWITCH
CC-Link IE
Field Network
Buffer
Allocator
128bit Hardware Function Bus
128bit Communication Bus
APB
PHY
PHY
MAC_TOP
DMAC
_RTPORT
MAC_DMA Gigabit
Ether
Buffer ID
INT_DMA
Timer Array
UART × 2ch
I2C × 2ch
CAN × 2ch
CSI × 2ch
WDT
Bridge
MUX
Bridge
CC-Link
Real-Time
GPIO
GPIO
MUX
Buffer RAM
64KB(ECC)
AHB2DMA
SSS
SSSS
SSSS
MUX
SSSSS
MUX
SSS
MUXMUX
SSSSSSS
MUX
SS
S
MUX
SS
MUX
SSSS
MUX
M
MSM S
S
M
MMM S
M MSMM
S
S
CPU System
CPU D-Code
CPU I-Code
DMAC
DMAC_RTPORT
HOST_CPU
CPU System
CPU D-Code CPU I-Code
DMAC
DMAC_RTPORT
HOST_CPU

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Dec. 28, 2018
1.4 Pin Assignments (Top View)
18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
V
GND
TRACE
CLK
TRACE
DATA2
RESETZ
CCI_CLK
2_097M
CCM_CL
K80M
P03 P07 P23 P24 P10 P14 P17 P32
GND
XT2 XT1
GND
V
U
P53
NMIZ
TRACE
DATA1
RST
OUTZ
HWRZ
SEL
BOOT0
P02 P06 P22 P25 P11 P15 P30 P33 P35 P37
ETH1_
RXD7
CLKOUT
25M1
U
T
P54 P55
TRACE
DATA0
JTAG
SEL
MEMIF
SEL
BOOT1
P01 P05 P21 P26 P12 P16 P31 P34 P36
ETH1_
RXD6
ETH1_
RXD5
ETH1_
RXD4
T
R
P52 P57 P56
TRACE
DATA3
PONRZ
HIF
SYNC
P00 P04 P20 P27 P13
TDI
TMS TDO
ETH1_
RXD3
ETH1_
RXD2
ETH1_
RXD1
ETH1_
RXD0
R
P
P66 P67 P50 P51
BUS32
EN
TMC2
ADMUX
MODE
MEMC
SEL
GND GND GND
PLL_
VDD
PLL_
GND
OSCTH
ETH1_
RXDV
ETH1_
RXER
ETH1_
CRS
ETH1_
RXC
P
N
P62 P63 P64 P65
HOT
RESETZ
GND
VDD33
GND
VDD33
GND GND
VDD33
GND GND
TRSTZ
ETH1_
COL
ETH1_
GE_INT
ETH1_
TXC
N
M
P76 P77 P60 P61
TMODE
0
VDD33
GND
VDD10
VDD10
VDD10
VDD10
GND
VDDQ_
MII
GND
TCK
ETH1_
TXER
ETH1_
TXEN
ETH1_
GTXC
M
L
GND
P73 P74 P75
TMODE
1
GND
VDD10
GND GND GND GND
VDD10
GND
VDD33
ETH1_
TXD0
ETH1_
TXD1
ETH1_
TXD2
ETH1_
TXD3
L
K
P47 P70 P71 P72
TMODE
2
GND
VDD10
GND GND GND GND
VDD10
VDDQ_
MII
GND
ETH1_
TXD4
ETH1_
TXD5
ETH1_
TXD6
ETH1_
TXD7
K
J
P43 P44 P45 P46
GND
VDD33
VDD10
GND GND GND GND
VDD10
GND GND
ETH0_
RXD4
ETH0_
RXD5
ETH0_
RXD6
ETH0_
RXD7
J
H
BUSCLK
P42 P41 P40
GND GND
VDD10
GND GND GND GND
VDD10
GND
VDD33
ETH0_
RXD0
ETH0_
RXD1
ETH0_
RXD2
ETH0_
RXD3
H
G
RDZ
CSZ0
WRST
BZ
WRZ0
GND
VDD33
GND
VDD10
VDD10
VDD10
VDD10
GND
VDDQ_
MII
GND
ETH_
MDC
ETH0_
GE_INT
ETH0_
RXER
ETH0_
RXDV
G
F
WRZ1
A2 A3 A4
GND GND
VDD33
GND GND
VDD33
GND
VDD33
GND GND
ETH0_
CRS
ETH0_
COL
ETH_
MDIO
ETH0_
TXC
F
E
A5 A6 A7 A8
GND GND GND GND GND GND GND GND GND GND
ETH0_
TXD0
ETH0_
TXEN
ETH0_
TXER
ETH0_
RXC
E
D
A9
A10 A11 A12
D3 D7
D11
TMC1
RP20
RP31
RP35
RP12
RP16
RP06
ETH0_
TXD3
ETH0_
TXD2
ETH0_
TXD1
ETH0_
GTXC
D
C
A13 A14 A15 A16
D4 D8
D12 D15
RP21
RP30
RP34
RP11
RP15
RP07
RP03
ETH0_
TXD6
ETH0_
TXD5
ETH0_
TXD4
C
B
A17 A18 A19
D1 D5 D9
D13
RP22
RP24
RP27
RP33
RP37
RP14
RP10
RP04
RP01
ETH0_
TXD7
CLKOUT
25M0
B
A
GND
A20
D0 D2 D6
D10 D14
RP23
RP25
RP26
RP32
RP36
RP13
RP17
RP05
RP02
RP00
GND
A
18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1

R-IN32M3-CL User’s Manual 1. Overview
R18UZ0005EJ0400 Page 6 of 104
Dec. 28, 2018
1.5 Base Addresses of the System Registers Area <R>
The addresses of registers given in the subsequent sections are relative to the base addresses. In access to the registers via
the external MCU interface, the base address is D_0000H. In access by the internal CPU or DMA controller, the base
address is 4001_0000H.
• In access by the CPU or DMA controller
BASE = 4001_0000H
• In access via the external microcontroller interface
BASE = D_0000H

R-IN32M3-CL User’s Manual 2. Pin Functions
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Dec. 28, 2018
2. Pin Functions
The meanings of the symbols and abbreviations used in this document are given below.
Table 2.1 Meanings of the Items in the List of Pins
Item
Meaning
Pin name
Name of the pin shown in section 1.4, Pin Assignments (Top View).
I/O
I/O direction of the given pin
Function
Summary of the given pin function
Active
Active level of the given pin
Level during reset
Level after reset "Level during reset" indicates the pin state while RSTOUTZ = low, and "Level after reset" indicates the pin state directly after the transition to RSTOUTZ = high.
For details on the reset specifications, see the R-IN32M3 Series User’s Manual (Peripheral
Modules).
Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins
Target
Symbol and
Abbreviation
Meaning
Pin name - (hyphen) Indicates that the pin is a dedicated pin and is not multiplexed with a
port-pin function.
I/O - (hyphen) Indicates that the pin is a pin such as a power supply or ground pin and so
does not have an I/O direction.
Active - (hyphen) Indicates that there is no active level (clock signals, data bus, and address
bus).
High
The active level is high.
Low
The active level is low.
Level during reset
Level after reset - (hyphen) Indicates an input-dedicated pin that has no initial level or state following a
reset.
High
The pin state during a reset is high.
Low
The pin state during a reset is low.
Hi-Z (high) The pin state during a reset is Hi-Z (high) with the internal pull-up resistor
pulling it to the high level.
Hi-Z (low) The pin state during a reset is Hi-Z (low) with the internal pull-up resistor
pulling it to the low level.

R-IN32M3-CL User’s Manual 2. Pin Functions
R18UZ0005EJ0400 Page 8 of 104
Dec. 28, 2018
2.1 List of Pins
2.1.1 Ethernet Pins
(1) PHY Interface Pins
Pin Name
I/O
Function
Active
Level during
Reset
Level after
Reset
ETH0_TXC I Ethernet 0 10-M/100-M transmit clock
(2.5 MHz/25 MHz)
- -
ETH0_GTXC
Note
O
Ethernet 0 1-G transmit clock (125 MHz)
-
High
ETH0_TXEN
Note
O
Ethernet 0 transmit enable output signal
High
Low
ETH0_TXER
Note
O
Ethernet 0 transmit error output signal
High
Low
ETH0_TXD0-
ETH0_TXD7
Note
O Ethernet 0 transmit data output signal - Low
ETH0_GE_INT
I
Ethernet 0 PHY interrupt signal
High/Low
-
ETH0_RXC
I
Ethernet 0 receive clock
-
-
ETH0_RXDV
I
Ethernet 0 receive data enable input signal
High
-
ETH0_RXER
I
Ethernet 0 receive data error input signal
High
-
ETH0_RXD0-
ETH0_RXD7
I Ethernet 0 receive data input signal - -
ETH0_CRS
I
Ethernet 0 carrier sense input signal
High
-
ETH0_COL
I
Ethernet 0 collision detection input signal
High
-
ETH1_TXC I Ethernet 1 10-M/100-M transmit clock
(2.5 MHz/25 MHz)
- -
ETH1_GTXC
Note
O
Ethernet 1 1-G transmit clock (125 MHz)
-
High
ETH1_TXEN
Note
O
Ethernet 1 transmit enable output signal
High
Low
ETH1_TXER
Note
O
Ethernet 1 transmit error output signal
High
Low
ETH1_TXD0-
ETH1_TXD7
Note
O Ethernet 1 transmit data output signal - Low
ETH1_GE_INT
I
Ethernet 1 PHY interrupt signal
High/Low
-
ETH1_RXC
I
Ethernet 1 receive clock
-
-
ETH1_RXDV
I
Ethernet 1 receive data enable input signal
High
-
ETH1_RXER
I
Ethernet 1 receive data error input signal
High
-
ETH1_RXD0-
ETH1_RXD7
I Ethernet 1 receive data input signal - -
ETH1_CRS
I
Ethernet 1 carrier sense input signal
High
-
ETH1_COL
I
Ethernet 1 collision detection input signal
High
-
ETH_MDC
O
Ethernet management interface clock
-
Low
Clock output
ETH_MDIO
I/O
Ethernet management data signal
-
Hi-Z
Note
:
The driving ability can be switched by the setting of the ETHDRCTRL
register. For details, see
s
ection 7.3.3.2, Ethernet Interface Buffer Function Select Register (ETHDRCTRL), in the
R-IN32M3 Series User’s Manual (Peripheral Modules).

R-IN32M3-CL User’s Manual 2. Pin Functions
R18UZ0005EJ0400 Page 9 of 104
Dec. 28, 2018
(2) Other Pins
Pin Name
I/O
Function
Shared
Port
Active
Level
during
Reset
Level
after
Reset
PHYLINK0,
PHYLINK1
I PHY Link port (for EtherSwitch) P06-P07 High Hi-Z (High)
ETHSWSECOUT O EtherSwitch event output per second
(output pulses have a width of 2 cycles of
HCLK)
P24 High

R-IN32M3-CL User’s Manual 2. Pin Functions
R18UZ0005EJ0400 Page 10 of 104
Dec. 28, 2018
2.1.2 External Memory Interface Pins
Pin Name
I/O
Function
Shared Pin
Shared Port
Active
Level during
Reset
Level after
Reset
BUSCLK
O
Bus clock output
-
-
-
Clock output
CSZ0
O
Chip select signal
output
HCSZ
-
Low Hi-Z (High)
High
CSZ1
O
HPGCSZ
P44
Hi-Z (High)
CSZ2
O
-
P51
CSZ3
O
-
P50
A1/MA0
Note4
O
Address output
HA1
P40
-
Hi-Z (High)
Low
A2-A20/
MA1-MA19
Note4
O HA2-HA20 - Hi-Z (Low)
A21-A27/
MA20-MA26
Note4
O - RP21-
RP27
Hi-Z (Low)
D0-D15/
MD0-MD15
Note1 Note4
I/O Data bus HD0-HD15 -
D16-D31/
MD16-MD31
Note1 Note4
I/O HD16-HD31 RP30-RP37
RP10-RP17
- Hi-Z (High)
RDZ
O
Read strobe output
HRDZ
-
Low
Hi-Z (High) High
WRSTBZ
O
Write strobe output
HWRSTBZ
-
Low
WRZ0, WRZ1/
BENZ0, BENZ1 O Valid byte lane strobe output HWRZ0, HWRZ1/
HBENZ0,
HBENZ1
- Low
WRZ2, WRZ3/
BENZ2, BENZ3 O HWRZ2, HWRZ3/
HBENZ2,
HBENZ3
RP06,
RP07 Hi-Z (High)
WAITZ
I
Wait signal input
HWAITZ
P41
Low
Hi-Z (High)
WAITZ1-WAITZ3
Note2
I
Wait signal input
-
P45-P47
Low
BCYSTZ / ADVZ
Note3
O
Address valid output
HBCYSTZ
RP20
Low
Remark
:
Pins of the external memory interface pins other than BUSCLK are input pins while the
internal reset signal (HRESETZ) is at its active level.
Notes
1.
While the synchronous burst access memory controller is in use, these signals are multiplexed
with the address signals if t
he ADMUXMODE pin is driven high.
ADMUXMODE = 0: MD0
-MD31 (Separate address and data lines)
ADMUXMODE = 1: MD0-MD31/MA0-MA31 (Multiplexed address and data lines)
2.
These pins are only available when the synchronous burst access memory controller is in use.
3.
This pin functions as BCYSTZ when the asynchronous SRAM memory controller is in use and
as ADVZ when the synchronous burst access memory controller is in use.
4
.
This pin functions as A1
-A27 and D0-D31 functions when the asynchronous SRAM memory
controller is in use and as MA
0-MA26 and MD0-MD31 functions when the synchronous burst
access memory controller is in use.