Renesas R-IN32M3 Series User manual

Renesas Electronics
www.renesas.com
・
R-IN32M3-CL
UPD60510BF1-HN4-A
UPD60510BF1-HN4-M1-A
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com)
ASSP
Document number: R18UZ0005EJ0400
Issue date: Dec. 28, 2018
R-IN32M3 Series
User’s Manual
Userʼs Manual
ASSP

Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation of these
circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for
any losses incurred by you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas
Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever
for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property
rights of third parties by or arising from the use of Renesas Electronics products or technical information described in
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Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a
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6. You should use the Renesas Electronics products described in this document within the range specified by Renesas
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range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no
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have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
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any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please
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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its
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(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.

Instructions for the use of product
In this section, the precautions are described for over whole of CMOS device.
Please refer to this manual about individual precaution.
When there is a mention unlike the text of this manual, a mention of the text takes first priority.
1.Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
- The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in
the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through
current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2.Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
- The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are
undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are not
guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not
guaranteed from the moment when power is supplied until the power reaches the level at which resetting has
been specified.
3.Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
- The reserved addresses are provided for the possible future expansion of functions. Do not access these
addresses; the correct operation of LSI is not guaranteed if they are accessed.
4.Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching
the clock signal during program execution, wait until the target clock signal has stabilized.
- When the clock signal is generated with an external resonator (or from an external oscillator) during a reset,
ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a
clock signal produced with an external resonator (or by an external oscillator) while program execution is in
progress, wait until the target clock signal is stable.
・
Arm®and Cortex®are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
・Ethernet is a registered trademark of Fuji Xerox Co., Ltd.
・IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc.
・TRON is an acronym for "The Real-time Operation system Nucleus".
・ITRON is an acronym for "Industrial TRON".
・µITRON is an acronym for "Micro Industrial TRON".
・TRON, ITRON, and µITRON do not refer to any specific product or products.
・CC-Link and CC-Link IE Field are registered trademarks of the CC-Link Partner Association (CLPA).
・Additionally all product names and service names in this document are a trademark or a registered trademark which
belongs to the respective owners.

How to Use This Manual
1. Purpose and Target Readers
This manual is intended for users who wish to understand the functions of industrial Ethernet network ASSP (application
specific standard product) "R-IN32M3-CL" (UPD60510BF1-HN4-A, UPD60510BF1-HN4-M1-A) for designing
application of it.
It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits,
and microcontrollers.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to
the text of the manual for details.
The mark "<R>" means the updated point in this revision. The mark "<R>" let users search for the updated
point in this document.
LiteratureLiterature may be preliminary versions. Note, however, that the following descriptions do not indicate
"Preliminary". Some documents on cores were created when they were planned or still under
development. So, they may be directed to specific customers. Last four digits of document number
(described as ****) indicate version information of each document. Please download the latest
document from our web site and refer to it.
The document related to R-IN32M3-CL
Document Name
Document Number
R-IN32M3 Series Datasheet
R18DS0008EJ****
R-IN32M3-EC User’s Manual
R18UZ0003EJ****
R-IN32M3 Series User’s Manual (Peripheral Modules)
R18UZ0007EJ****
R-IN32M3 Series Programming Manual (OS edition)
R18UZ0011EJ****
R-IN32M3 Series Programming Manual (Driver edition)
R18UZ0009EJ****
R-IN32M3 Series User’s Manual (Board design edition)
R18UZ0021EJ****
R-IN32M3-CL User’s Manual
This manual

2. Notation of Numbers and Symbols
Weight in data notation: Left is high-order column, right is low-order column
Active low notation:
xxxZ (capital letter Z after pin name or signal name)
or xxx_N (capital letter _N after pin name or signal name)
or xxnx (pin name or signal name contains small letter n)
Note:
Explanation of (Note) in the text
Caution:
Item deserving extra attention
Remark:
Supplementary explanation to the text
Numeric notation:
Binary …xxxx , xxxxB or n’bxxxx (n bits)
Decimal …xxxx
Hexadecimal …xxxxH or n’hxxxx (n bits)
Prefixes representing powers of 2 (address space, memory capacity):
K (kilo)…210 = 1024
M (mega)…220 = 10242
G (giga)…230 = 10243
Data Type:
Word …32 bits
Halfword …16 bits
Byte …8 bits

Contents-1
Contents
1. Overview........................................................................................................................................................1
1.1 Introduction......................................................................................................................................................... 1
1.2 Overview ............................................................................................................................................................ 2
1.3 Internal Block Diagram ...................................................................................................................................... 4
1.4 Pin Assignments (Top View).............................................................................................................................. 5
1.5 Base Addresses of the System Registers Area <R>............................................................................................ 6
2. Pin Functions.................................................................................................................................................7
2.1 List of Pins.......................................................................................................................................................... 8
2.1.1 Ethernet Pins.............................................................................................................................................. 8
2.1.2 External Memory Interface Pins.............................................................................................................. 10
2.1.3 External MCU Interface Pins............................................................................................................... 11
2.1.4 Port Pins and Real-Time Port Pins........................................................................................................... 12
2.1.5 Serial Flash ROM Interface Pins ............................................................................................................. 16
2.1.6 DMA Interface Pins................................................................................................................................. 16
2.1.7 External Interrupt Input Pins.................................................................................................................... 17
2.1.8 Timer I/O Pins ......................................................................................................................................... 17
2.1.9 Watchdog Timer Output Pin.................................................................................................................... 17
2.1.10 Trace Pins ................................................................................................................................................ 18
2.1.11 CPU Power Control Pin........................................................................................................................... 18
2.1.12 Serial Interface Pins................................................................................................................................. 18
2.1.13 CC-Link IE Field Pins (Intelligent Device Station)................................................................................. 19
2.1.14 CC-Link Pins (Intelligent Device Station)............................................................................................... 20
2.1.15 CC-Link Pins (Remote Device Station)................................................................................................... 21
2.1.16 System Pins.............................................................................................................................................. 22
2.1.17 Test Pins .................................................................................................................................................. 23
2.1.18 Operating Mode Setting Pins................................................................................................................... 23
2.2 Pin States .......................................................................................................................................................... 25
2.2.1 Pin States when Booting is from External Memory................................................................................. 26
2.2.2 Pin States when Booting is from External Serial Flash ROM ................................................................. 29
2.2.3 Pin States when Booting is for External MCU ........................................................................................ 32
2.3 Operating Mode Monitoring............................................................................................................................. 35
2.4 Buffer Switching............................................................................................................................................... 35
2.5 Buffer Types and Handling of Unused Pins ..................................................................................................... 36
2.5.1 Ethernet Pins............................................................................................................................................ 36

Contents-2
2.5.2 External Memory/MCU Interface Pins.................................................................................................... 37
2.5.3 External Interrupt Input Pins.................................................................................................................... 37
2.5.4 System Pins.............................................................................................................................................. 37
2.5.5 Test Pins .................................................................................................................................................. 38
2.5.6 Port Pins................................................................................................................................................... 39
2.5.7 Operating Mode Setting Pins................................................................................................................... 40
2.5.8 CC-Link IE Field Pin (Intelligent Device Station) .................................................................................. 40
2.5.9 CC-Link Pin (Intelligent Device Station, Remote Device Station).......................................................... 40
2.5.10 Trace Pins ................................................................................................................................................ 40
3. Memory Maps..............................................................................................................................................41
4. Exception Handling......................................................................................................................................45
4.1 Exceptions List ................................................................................................................................................. 45
4.2 List of Interrupts ............................................................................................................................................... 46
5. Peripheral Modules......................................................................................................................................51
6. CC-Link IE Field (Intelligent Device Station) Function ................................................................................52
6.1 CC-Link IE Field (Intelligent Device Station) Control Registers..................................................................... 52
6.1.1 CC-Link IE Field (Intelligent Device Station) Clock Gate Register (CIECLKGTD) ............................. 53
6.1.2 CC-Link IE Field (Intelligent Device Station) Wait Delay Register (CIEWAITDLY)........................... 54
6.1.3 CC-Link IE Field (Intelligent Device Station) Bus Size Control Register (CIEBSC)............................. 55
6.1.4 CC-Link IE Field (Intelligent Device Station) Bus Bridge Control Register (CIESMC)........................ 55
6.2 Cautionary Notes .............................................................................................................................................. 56
7. Port Functions .............................................................................................................................................57
7.1 Features............................................................................................................................................................. 57
7.2 Port Configuration ............................................................................................................................................ 58
7.3 List of Registers................................................................................................................................................ 60
7.3.1 Port Registers (P, RP).............................................................................................................................. 66
7.3.2 Port Mode Registers (PM, RPM)............................................................................................................. 69
7.3.3 Port Mode Control Registers (PMC, RPMC) .......................................................................................... 72
7.3.4 Port Function Control Registers (PFC, RPFC)........................................................................................ 76
7.3.5 Port Function Control Expansion Registers (PFCE, RPFCE).................................................................. 79
7.3.6 Port Pin Input Registers (PIN, RPIN)...................................................................................................... 82
7.4 List of Selectable Multiplexed Functions ......................................................................................................... 85
7.5 Buffer Switching Registers (DRCTL) .............................................................................................................. 89
7.5.1 Port 0 Buffer Switching Registers (DRCTLP0L, DRCTLP0H).............................................................. 90

Contents-3
7.5.2 Port 1 Buffer Switching Registers (DRCTLP1L, DRCTLP1H).............................................................. 91
7.5.3 Port 2 Buffer Switching Registers (DRCTLP2L, DRCTLP2H).............................................................. 92
7.5.4 Port 3 Buffer Switching Registers (DRCTLP3L, DRCTLP3H).............................................................. 93
7.5.5 Port 4 Buffer Switching Registers (DRCTLP4L, DRCTLP4H).............................................................. 94
7.5.6 Port 5 Buffer Switching Registers (DRCTLP5L, DRCTLP5H).............................................................. 95
7.5.7 Port 6 Buffer Switching Registers (DRCTLP6L, DRCTLP6H).............................................................. 96
7.5.8 Port 7 Buffer Switching Registers (DRCTLP7L, DRCTLP7H).............................................................. 97
7.5.9 Real-Time Port 0 Buffer Switching Registers (DRCTLRP0L, DRCTLRP0H)....................................... 98
7.5.10 Real-Time Port 1 Buffer Switching Registers (DRCTLRP1L, DRCTLRP1H)....................................... 99
7.5.11 Real-Time Port 2 Buffer Switching Registers (DRCTLRP2L, DRCTLRP2H)..................................... 100
7.5.12 Real-Time Port 3 Buffer Switching Registers (DRCTLRP3L, DRCTLRP3H)..................................... 101
7.6 Operation of Port Functions............................................................................................................................ 102
7.6.1 Reading and Writing via I/O Ports......................................................................................................... 102
7.6.2 Multiplexed Function Pin Output State in Control Mode...................................................................... 102
7.7 Trigger-Synchronous Ports (RP00 to RP37)................................................................................................... 103
8. Electrical Characteristics ...........................................................................................................................104

Contents-4
Contents of Figures
Figure 3.1 Memory Map (All).............................................................................................................................. 41
Figure 3.2 Memory Map (APB Peripheral Registers Area) ................................................................................. 42
Figure 3.3 Memory Map (External Memory Area).............................................................................................. 43
Figure 3.4 Memory Map (CC-Link Master Area)................................................................................................ 43
Figure 3.5 External MCU Interface Area............................................................................................................. 44
Figure 6.1 Timing of Data Sampling and Period of Waiting for the Bus of a CC-Link IE Field Network.......... 54
Figure 6.2 Procedure for Switching Access Path to the CC-Link IE Field .......................................................... 56
Figure 7.1 Basic Circuit Configuration of Ports................................................................................................... 59
Figure 7.2 Port Registers (in 8-Bit Notation) ....................................................................................................... 66
Figure 7.3 Port Registers (in 16-Bit Notation) ..................................................................................................... 67
Figure 7.4 Port Registers (in 32-Bit Notation) ..................................................................................................... 68
Figure 7.5 Port Mode Registers (in 8-Bit Notation)............................................................................................. 69
Figure 7.6 Port Mode Registers (in 16-Bit Notation)........................................................................................... 70
Figure 7.7 Port Mode Registers (in 32-Bit Notation)........................................................................................... 71
Figure 7.8 Port Mode Control Registers (in 8-Bit Notation)................................................................................ 72
Figure 7.9 Port Mode Control Registers (in 16-Bit Notation).............................................................................. 73
Figure 7.10 Port Mode Control Registers (in 32-Bit Notation).............................................................................. 75
Figure 7.11 Port Function Control Registers (in 8-Bit Notation)........................................................................... 76
Figure 7.12 Port Function Control Registers (in 16-Bit Notation)......................................................................... 77
Figure 7.13 Port Function Control Registers (in 32-Bit Notation)......................................................................... 78
Figure 7.14 Port Function Control Expansion Registers (in 8-Bit Notation)......................................................... 79
Figure 7.15 Port Function Control Expansion Registers (in 16-Bit Notation)....................................................... 80
Figure 7.16 Port Function Control Expansion Registers (in 32-Bit Notation)....................................................... 81
Figure 7.17 Port Pin Input Registers (in 8-Bit Notation) ....................................................................................... 82
Figure 7.18 Port Pin Input Registers (in 16-Bit Notation) ..................................................................................... 83
Figure 7.19 Port Pin Input Registers (in 32-Bit Notation) ..................................................................................... 84
Figure 7.20 Configuration of Trigger-Synchronous Ports.................................................................................... 103

Contents-5
Contents of Tables
Table 1.1 Overview of R-IN32M3-CL .....................................................................................................................2
Table 2.1 Meanings of the Items in the List of Pins.................................................................................................. 7
Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins .............................................................. 7
Table 2.3 Operating Mode Setting Pins for which the Settings can be Checked.................................................... 35
Table 4.1 List of Interrupts ..................................................................................................................................... 47
Table 6.1 Outline Specifications of CC-Link IE Field............................................................................................ 52
Table 6.2 Overview of CC-Link IE Field (Intelligent Device Station) Control Registers...................................... 52