Renesas HD49335HNP User manual

Rev.1.0, Feb.12.2004, page 1 of 29
HD49335NP/HNP
CDS/PGA & 10-bit A/D TG Converter REJ03F0097-0100Z
Rev.1.0
Feb.12.2004
Description
The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.
There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.
Functions
• Correlated double sampling
• PGA
• Serial interface control
• 10-bit ADC
• Timing generator
• Operates using only the 3 V voltage
• Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)
• ADC direct input mode
• QFN 64-pin package
Features
• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.
• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 10-bit-resolution A/D converter.
• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization
(wave pattern). It is patented by Renesas.
• Timing generator generates the all of pulse which are needed for CCD driving.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 2 of 29
Pin Arrangement
48 47 3946 45 44 43 42 41 40 38 36 35 3437
12 103 4 5 6 7 8 9 11 12 13 14 15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(Top view)
AV
DD
BLKC
CDS_in
AV
DD
BLKFB
BLKSH
AV
SS
Test2
Test1
DLL_C
DV
DD
1
MON
41cont
CS
SDATA
SCK
XV3
XV2
XV1
DV
DD
3
DV
DD
4
1/4clk_o
H2A
DV
SS
4
DV
SS
4
1/2clk_o
H1A
DV
DD
4
DV
DD
3
RG
Reset
VD_in
VRM VRT VRB BIAS ADC_in AV
SS
DV
SS
3
STROB SUB_PD SUB_SW XSUB CH4 CH3 CH2 CH1 XV4
ID
DV
SS
1,2
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DV
DD
2
DV
SS
3
CLK_in
HD_in
33
16
Pin Description
Pin No. Symbol Description I/O Analog(A) or Digital(D) Remarks
1 ID Odd/even number line detecting pulse output pin O D 2 mA/10 pF
2 DVSS1,2 CDS Digital ground + ADC output buffer ground (0 V) — D
3 to 12 D0 to D9 Digital output (D0; LSB, D9; MSB) O D 2 mA/10 pF
13 DVDD2 ADC output buffer power supply (3 V) — D
14 DVSS3 General ground for TG (0 V) — D
15 CLK_in CLK input (max 72 MHz) I D
16 HD_in HD input I/O D
17 VD_in VD input I/O D
18 Reset Hardware reset (for DLL reset) I D Schmitt trigger
19 RG Reset gate pulse output O D 3 mA/10 pF
20 DVDD3 General power supply for TG (3 V) — D
21 DVDD4 H1 buffer power supply (3 V) — D
22 H1A H.CCD transfer pulse output-1A O D 30 mA/165 pF
23 1/2clk_o CLK_in 2 divided output. 3 divided output at 3 divided mode O D 2 mA/10 pF
24 DVSS4 H1 buffer ground (0 V) — D
25 DVSS4 H1 buffer ground (0 V) — D
26 H2A H.CCD transfer pulse output-2A O D 30 mA/165 pF
27 1/4clk_o CLK_in 4 divided output. 6 divided output at 3 divided mode O D 2 mA/10 pF
28 DVDD4 H2 buffer power supply (3 V) — D
29 DVDD3 General power supply for TG (3 V) — D

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 3 of 29
Pin Description (cont.)
Pin No. Symbol Description I/O Analog(A) or Digital(D) Remarks
30 XV1 V.CCD transfer pulse output-1 O D 2 mA/10 pF
31 XV2 V.CCD transfer pulse output-2 O D 2 mA/10 pF
32 XV3 V.CCD transfer pulse output-3 O D 2 mA/10 pF
33 XV4 V.CCD transfer pulse output-4 O D 2 mA/10 pF
34 CH1 Read out pulse output-1 O D 2 mA/10 pF
35 CH2 Read out pulse output-2 O D 2 mA/10 pF
36 CH3 Read out pulse output-3 O D 2 mA/10 pF
37 CH4 Read out pulse output-4/XV6 at stripe mode O D 2 mA/10 pF
38 XSUB Pulse output for electronic shutter O D 2 mA/10 pF
39 SUB_SW SUB voltage control output-1. ADCK input I/O D 2 mA/10 pF
40 SUB_PD SUB voltage control output-2/ XV5 at stripe mode O D 2 mA/10 pF
41 STROB Flash control output. Input Vgate at Hi of pin 61 I/O D 2 mA/10 pF
42 DVSS3 General ground for TG (0 V) — D
43 AVSS Analog ground (0 V) — A
44 ADC_in AD converter input pin I A
45 BIAS Bias standard resistance — A
46 VRB ADC bottom standard voltage (0.1 µF for GND) — A
47 VRT ADC top standard voltage (0.1 µF for GND) — A
48 VRM ADC middle standard voltage (0.1 µF for GND) — A
49 AVDD Analog power supply (3 V) — A
50 BLKC Black level C pin (1000 pF for GND) — A
51 CDS_in CDS input pin I A
52 AVDD Analog power supply (3 V) — A
53 BLKFB Black level FB pin (1 µF between BLKFB and BLKSH) I A
54 BLKSH Black level S/H pin O A
55 AVSS Analog ground (0 V) — A
56 Test2
H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCK, Input 40; SP2, Input 41; SP1
I D
57 Test1 L: Slave mode, H: Master mode I D
58 DLL_C Analog delay DLL external C pin (100 pF for GND) O A
59 DVDD1 Digital power supply (3 V) CDS, PAG, ADC part — D
60 MON Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input) O D 2 mA/10 pF
61 41cont
Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi I D
62 CS Serial data CS at CDS part I D
63 SDATA Input serial data I D
64 SCK Input serial clock I D

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 4 of 29
Input/Output Equivalent Circuit
Pin Name Equivalent Circuit
D0 to D9, HD_in, VD_in,
H1A, H2A, 1/2clk_o,
1/4clk_o, 41cont,
SUB_SW, SUB_PD
DIN
DV
DD
ENABLE
Digital
output
Digital output
ID, RG, MON, XV1 to XV4,
CH1 to CH4, XSUB
DIN
DV
DD
Digital
output
Digital input CLK_in, HD_in, VD_in,
ADCLK, OBP, SPBLK,
SPSIG, CS, SCK, SDATA,
PBLK, OEB, Reset, Test1,
Test2, SUB_SW, STROB
*1
Digital
input
DVDD
Note: Only OEB is pulled down to about 70 kΩ.
CDS_in
CDS_in
AVDD
Internally
connected
to VRT
ADC_in
A
DC_in
AV
DD
Internally
connected
to VRT
BLKSH, BLKFB, BLKC
BLKFB
AVDD
BLKSH
BLKC
−
+
VRT, VRM, VRB
−
+
−
+
VRT
VRM
VRB AV
DD
−
+
Analog
BIAS
BIAS
AV
DD

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 5 of 29
Block Diagram
10bit
ADC
AVSS
VRB
VRM
VRT
CDS_in CDS
BLKSH
BLKC
ADC_in
SUB_SW
SUB_PD
STROB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Reset
DVSS1 to 4
BLKFB
CS
SDATA
SCK
DLL_C
MON
ID
BIAS
Timing
generator
VD_in HD_in CLK_in XSUB CH4 CH3 CH2 CH1 XV4 XV3
PBLK
CPDM
OBP
ADCLK
SP2
SP1
XV2 XV1 1/4clk_o H2A 1/2clk_o H1A RG AVDD DVDD1 to 4
PGA
DLL
Output latch circuit
DC offset
compensation
circuit
Serial
interface
Bias
generator

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 6 of 29
Internal Functions
Functional Description
• CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2
• ADC input
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57
times (–4.86 dB) to 5.14 times (14.22 dB). *2
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
 Digital output is fixed at clamp level
• Digital outputs enable function
Note: 1. It is not covered by warranty when 14LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
DAC
C3
CDS
AMP
PG
AMP
CDS_in
BLKFB BLKSH
SH
AMP
C2
C1
VRT
SP1 SP1
SP2 10bit
ADC
D0 to D9
BLKC
C4
OBP
ADC_in
Offset
calibration
logic
DC offset
feedback
logic
Gain setting
(register) Clamp data
(register)
Current
DAC
Figure 1 CDS/PGA Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) ×N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.001784 times) ×N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 7 of 29
3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings
The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compensation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk ×C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example:When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation
Table 2 High-Speed Lead-In Operation
Cancellation Time
HGain-Nsel
(register settings) Multiplication
Factor N
HGstop-Hsel
(register settings) Cancellation
Time
[0]
L
H
L
H
[1]
L
H
H
L
4
32
16
8
[0]
L
H
L
H
[1]
L
H
H
L
1 H
8 H
4 H
2 H
5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 8 of 29
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
Table 3 ADC Digital Output Functions
H
L
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
X
L
L
L
L
H
L
L
L
L
H
X
X
X
X
X
L
H
L
H
X
L
H
L
H
X
L
H
L
H
X
L
L
H
H
X
L
L
H
H
X
L
L
H
H
X
L
H
X
X
L
H
H
L
STBY
D9
TEST0
D0D1D2D3D4D5D6D7D8
PBLK MINV TEST1 LINV
Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
Low-power wait state
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
Operating Mode
ADC Digital Output
Note: 1. STBY, TEST, LINV, and MINV are set by register.
Table 4 ADC Output Code (Binary)
D1
H
L
L
H
H
L
L
L
H
H
D0
H
L
H
L
H
L
L
H
L
H
D2
L
H
H
H
H
L
H
H
H
H
D7
L
L
L
L
H
L
H
H
H
H
D5
L
L
L
L
H
L
H
H
H
H
D4
L
L
L
L
H
L
H
H
H
H
D3
L
L
L
L
H
L
H
H
H
H
D6
L
L
L
L
H
L
H
H
H
H
D8
L
L
L
L
H
L
H
H
H
H
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
Output Pin
Output
codes
Steps
Table 5 ADC Output Code (Gray)
D8
L
L
L
L
H
H
L
L
L
L
D9
L
L
L
L
L
H
H
H
H
H
3
4
5
6
511
512
1020
1021
1022
1023
D1
H
H
H
L
L
L
H
H
L
L
D0
L
L
H
H
L
L
L
H
H
L
D2
L
H
H
H
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
L
L
L
Output Pin
Output
codes
Steps

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 9 of 29
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.
Table 6 SHSW CR Time Constant Setting
31
BLKC
C
Recommendation value of C is 1000 pF
The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
8.
2.20 nsec
(72 MHz)
2.30 nsec
(69 MHz)
2.51 nsec
(63 MHz)
2.64 nsec
(60 MHz)
2.93 nsec
(54 MHz)
3.11 nsec
(51 MHz)
3.52 nsec
(45 MHz)
3.77 nsec
(42 MHz)
L
[3]
L
[0]
L
[0]
4.40 nsec
(36 MHz)
4.80 nsec
(33 MHz)
L
[1]
L
[1]
L
[2]
L
[2]
5.87 nsec
(27 MHz)
6.60 nsec
(24 MHz)
8.80 nsec
(18 MHz)
10.6 nsec
(15 MHz)
17.6 nsec
(9 MHz)
26.4 nsec
(6 MHz)
L
[3]
H
[3]
H
[0]
H
[0]
L
[1]
L
[1]
L
[2]
L
[2]
L
[3]
H
[3]
L
[0]
L
[0]
H
[1]
H
[1]
L
[2]
L
[2]
L
[3]
H
[3]
H
[0]
H
[0]
H
[1]
H
[1]
L
[2]
L
[2]
L
[3]
H
[3]
L
[0]
L
[0]
L
[1]
L
[1]
H
[2]
H
[2]
L
[3]
H
[3]
H
[0]
H
[0]
L
[1]
L
[1]
H
[2]
H
[2]
L
[3]
H
[3]
L
[0]
L
[0]
H
[1]
H
[1]
H
[2]
H
[2]
L
[3]
H
[3]
H
[0]
H
[0]
H
[1]
H
[1]
H
[2]
H
[2]
H
[3]
SHSW-fsel (Register setting)
SHSW-fsel (Register setting)
CR Time Constant (Typ)
(cutoff frequency conversion)
CR Time Constant (Typ)
(cutoff frequency conversion)
Table 7 SHAMP Frequency Characteristics Setting
230 MHz
6800 pF
(240 pF)
56 MHz
18000 pF
(360 pF)
116 MHz
10000 pF
(270 pF)
100 MHz
10000 pF
(560 pF)
"Lo"
"Hi" 24 MHz
27000 pF
(820 pF)
75 MHz
13000 pF
(300 pF)
32 MHz
22000 pF
(750 pF)
49 MHz
15000 pF
(620 pF)
L
[0]
H
[0]
L
[1]
L
[1]
L
[0]
H
[1]
H
[0]
H
[1]
SHA-fsel (Register setting)
LoPwr
(Register setting)
Note: Upper line
Middle line
Lower line
: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 10 of 29
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
012 91011
N+1 N+2 N+9 N+10 N+11N
CDS_in
SP1
SP2
ADCLK
D0 to D9
N+2
N+8 N+9
N+10 N+11
N−8N−9N−1
ADC_in
ADCLK
D0 to D9 NN+1
NN+1
N−9N−8N−1 NN−10
•When CDS_in input mode is used
•When ADC_in input mode is used
~
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 11 of 29
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
CDS_in
SP1 Vth
(2) (3)
SP2
A
DCLK
(7)
Vth
Vth
(8)
(9)
(10)
(4)
(1)
(5)
(11)
(6)
(13)
(12)
D0 to D9
H1
Black
level
Signal
level
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when the CDSIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Black-level signal fetch time tCDS1 — (1.5) — ns
(2) SP1 ‘Hi’ period tCDS2 Typ ×0.8 1/4fCLK Typ ×1.2 ns
(3) Signal-level fetch time tCDS3 — (1.5) — ns
(4) SP2 ‘Hi’ period tCDS4 Typ ×0.8 1/4fCLK Typ ×1.2 ns
(5) SP1 falling to SP2 falling time tCDS5 Typ ×0.85 1/2fCLK Typ ×1.15 ns
(6) SP1 falling to ADCLK rising inhibit time tCDS6 — (5) — ns
(7), (8) ADCLK tWH min./tWL min tCDS7, 8 11 — — ns
(9) ADCLK rising to digital output holding time t
CHLD9 — (7) — ns
(10) ADCLK rising to digital output delay time tCOD10 — (16) — ns
(11) H1 rising to ADCLK rising time tCDS11 — (1/4fCLK) — ns
(12) H1 rising to SPSIG falling time tCDS12 — (1/fCLK) — ns
(13) H1 rising to SPBLK falling time tCDS13 — (1/2fCLK) — ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
CDS_in
OBP
NN+1 N+5 N+12 N+13
Note:
OB pulse > 2 clock cycles
OB period *
1
1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 12 of 29
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
Digital output
(D0 to D9)
ADC
data Clamp Level ADC
data
PBLK
ADCLK ×2 clock ADCLK ×10 clock
Vth
V
OL
V
OH
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
A
DC_in (1)
A
DCLK
D0 to D9
(2)
Vth
VDD/2
(3)
(5)
(4)
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Signal fetch time tADC1 — (6) — ns
(2), (3) ADCLK tWH min./tWL min. tADC2, 3 Typ ×0.85 1/2fADCLK Typ ×1.15 ns
(4) ADCLK rising to digital output hold time tAHLD4 — (14.5) — ns
(5) ADCLK rising to digital output delay time tAOD5 — (23.5) — ns

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 13 of 29
Dummy Clamp
It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it
woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes
to clamp processing by dummy bit level. Resister settings are follows.
D12, D11, D10 of address H'F7 (Dummy CP)
0, 0, 0 ; OFF
0, 0, 1 ; +32
0, 1, 0 ; +64
0, 1, 1 ; +96
:
:
1, 1, 1 ; +224
The amount of offset are changes automatically
depends on PGA gain in the LSI.
D8, D8 of address H'F7 (DMCG)
The amount of feed back current can be
reduced with only dummy clamp.
Data = 0:1/4
1:1/8
2:1/16
3:1/32
D10 to D12 of address H'F7
Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.
D8 to D9 of address H'F7
Digital output
CDS
AGC
CDS_in
BLKFB BLKSH
SH
AMP
VRT
SP1
SP2
SP1
on/off
Clamp level
+
−
−
+
+
(+)
(−)
ADC
OB
DET
Current
cell
Dummy
DET
Detect 4clk
from OPDM edge
Detect 8clk
from OBP edge
Figure 7 Internal Bias Circuitry

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 14 of 29
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Power supply voltage VDD 4.1 V
Analog input voltage VIN –0.3 to AVDD +0.3 V
Digital input voltage VI–0.3 to DVDD +0.3 V
Operating temperature range Ta –10 to +75 °C
Power dissipation Pt 750 mW
Storage temperature Tstg –55 to +125 °C
Power supply voltage Vopr 2.70 to 3.30 V
Note: AVDD, AVSS are analog power source systems of CDS, PGA, and ADC.
DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC.
DVDD2, DVSS2 are buffer power source systems of ADC output.
DVDD3, DVSS3 are general digital power source systems of TG.
DVDD4, DVSS4 are buffer power source systems of H1 and H2.
•Pin 2 multi bonds the DVSS1 and DVSS2
•When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCK input
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items Common to CDSIN and ADCIN Input Modes
Item Symbol Min Typ Max Unit Test Conditions Remarks
Power supply voltage
range VDD 2.70 3.00 3.30 V
fCLK hi 20 — 36 MHz LoPwr = low *2HD49335HNPConversion frequency fCLK low 5.5 — 25 MHz LoPwr = high *2HD49335NP
VIH2
DV
DD
3.0
2.25 ×
— DVDD V
Digital input voltage
VIL2 0 —
DVDD
3.0
0.6 ×
V
CS, SCK, SDATA
VOH DVDD –0.5 — — V IOH = –1 mADigital output voltage VOL — — 0.5 V IOL = +1 mA
IIH — — 50 µA VIH = 3.0 VDigital input current IIL –50 — — µA VIL = 0 V
ADC resolution RES 10 10 10 bit
ADC integral linearity INL — (2) — LSBp-p fCLK = 25 MHz
ADC differential linearity+ DNL+ — 0.3 0.99 LSB fCLK = 25 MHz *1
ADC differential linearity– DNL– –0.99 –0.3 — LSB fCLK = 25 MHz *1
Sleep current ISLP –100 0 100 µA Digital input pin is
set to 0 V, output
pin is open
Standby current ISTBY — 3 5 mA Digital I/O pin is set
to 0 V
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. 2 divided mode: fCLK = 1/2CLK_in
3 divided mode: fCLK = 1/3CLK_in
3. Values within parentheses ( ) are for reference.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 15 of 29
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumption current (1) IDD1 — 84 96.6 mA fCLK = 36 MHz CDSIN mode
LoPwr = low
Consumption current (2) IDD2 — 58 66.7 mA fCLK = 20 MHz CDSIN mode
LoPwr = high
CCD offset tolerance range VCCD (–100) — (100) mV
Timing specifications (1) tCDS1 — (1.5) — ns
Timing specifications (2) tCDS2 Typ ×0.8 1/4fCLK Typ ×1.2 ns
Timing specifications (3) tCDS3 — (1.5) — ns
Timing specifications (4) tCDS4 Typ ×0.8 1/4fCLK Typ ×1.2 ns
Timing specifications (5) tCDS5 Typ ×0.85 1/2fCLK Typ ×1.15 ns
Timing specifications (6) tCDS6 1 5 9 ns
Timing specifications (7) tCDS7 — 1/2fCLK — ns
Timing specifications (8) tCDS8 — 1/2fCLK — ns
Timing specifications (9) tCHLD9 — (7) — ns CL= 10 pF
Timing specifications (10) tCOD10 — (16) — ns CL= 10 pF
Timing specifications (11) tCDS11 — (1/4fCLK) — ns
Timing specifications (12) tCDS12 — (1/fCLK) — ns
Timing specifications (13) tCDS13 — (1/2fCLK) — ns
Refer to table 8
CLP(00) — (14) — LSB
CLP(09) — (32) — LSB
Clamp level
CLP(31) — (76) — LSB
AGC(0) –4.4 –2.4 –0.4 dB
AGC(63) 4.1 6.1 8.1 dB
AGC(127) 12.5 14.5 16.5 dB
AGC(191) 21.0 23.0 25.0 dB
PGA gain at CDS input
AGC(255) 29.4 31.4 33.4 dB
*1
DLL_2 11 — 25 MHz *2
DLL_3 7 — 11 MHz *3
DLL operation frequency
DLL_4 5.5 — 7 MHz *4
T/G 3/1divided operation
frequency range CLK_in3 28.6 — 28.6 MHz fCLK = 1/3CLK_in3
VOH 2.94 2.97 — V 30 mA Buff, IOH = –5 mA
VOL — 22 47 MV 30 mA Buff, IOL = +5 mA
VOH 2.89 2.94 — V 14 mA Buff, IOH = –5 mA
VOL — 50 112 MV 14 mA Buff, IOL = +5 mA
VOH 2.91 2.96 — V 10 mA Buff, IOH = –3 mA
VOL — 36 78 MV 10 mA Buff, IOL = +3 mA
VOH 2.85 2.93 — V 4 mA Buff, IOH = –2 mA
VOL — 60 129 MV 4 mA Buff, IOL = +2 mA
VOH 2.69 2.86 — V 2 mA Buff, IOH = –2 mA
H Buffer output voltage
VOL — 115 262 mV 2 mA Buff, IOL = +2 mA
VOH 2.81 2.90 — V IOH = –2 mARG output voltage VOL — 78 141 mV IOL = +2 mA
Notes: 1. Define digital output full scall with 1 V input as 0 dB.
2. Number of master steps: 60 steps, DLL current High
3. Number of master steps: 40 steps, DLL current Low
4. Number of master steps: 60 steps, DLL current Low
5. Values within parentheses ( ) are for reference.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 16 of 29
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for ADCIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumption current (3) IDD3 — 32 38.4 mA fCLK = 36 MHz ADCIN mode
LoPwr = low
Consumption current (4) IDD4 — 22 27.5 mA fCLK = 25 MHz ADCIN mode
LoPwr = high
Timing specifications (14) tADC1 — (6) — ns
Timing specifications (15) tADC2 Typ ×0.85 1/2fADCLK Typ ×1.15 ns
Timing specifications (16) tADC3 Typ ×0.85 1/2fADCLK Typ ×1.15 ns
Timing specifications (17) tAHLD4 — (14.5) — ns CL= 10 pF
Timing specifications (18) tAOD5 — (23.5) — ns CL= 10 pF
Refer to table 9
Input current at ADC input IINCIN –110 — 110 µA VIN = 1.0 to 2.0 V
Clamp level at ADC input OF2 — (512) — LSB
GSL(0) 0.45 0.57 0.72 Times
GSL(63) 1.36 1.71 2.16 Times
GSL(127) 2.27 2.86 3.60 Times
GSL(191) 3.18 4.00 5.04 Times
PGA gain at ADC input
GSL(255) 4.08 5.14 6.47 Times
Note : Values within parentheses ( ) are for reference.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 17 of 29
Serial Interface Specifications
Timing Specifications
SDATA
STD2(Upper data) STD1(Lower data) address(address)
SCK
CS
f
SCK
D9D8 D11D10 D13D12 D15D14 D1D0 D3D2 D5D4 D7D6 D0 D2D1 D4D3 D6D5 D7
t
INT1
t
INT2
t
su
t
ho
Latches SDATA
at SCK rising edge
Data is determined
at CS rising edge
Figure 8 Serial Interface Timing Specifications
Item Min Max
fSCK — 5 MHz
tINT1,2 50 ns —
tsu 50 ns —
tho 50 ns —
Notes: 1. 3 byte continuous communications.
2. Input SCK with 24 clock when CS is Low.
3. It becomes invalid when data communications are stopped on the way.
4. Data becomes a default with hardware reset.
5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
The Kind of Data
Data address has 256 type. H’00 to H’FF
H’00
:
:
H’EF
Data at timing generator part
H’F0
:
:
H’FF
Data at CDS part
Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 18 of 29
Explanation of Serial Data of CDS Part
Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows.
Address STD1[7:0] (L)
PGA gain
STD2[15:8] (H)
1 1 1 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
test_I1
• PGA gain (D0 to D7 of address H’F0)
Details are referred to page 5 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB ×N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times ×N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
(1) Level dia explain
CDS PGA
0 dB when set N = 18 which correspond to 2.36 dB
ADC
(2) Level dia on the circuit
CDS PGA
3.64 dB + 0.132 dB ×N
(CDS = 0 dB)
ADC
2 V 1023
(1.0 V)
(1.0 V) (2.0 V) (1023)
Figure 9 Level Dia of PGA
• Test_I1 (D13 to D15 of address H’F0)
It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.
When data = 0, 50% current value with default
When data = 4, default
When data = 7, 150% current value with default
Address STD1[7:0] (L) STD2[15:8] (H)
1 1 1 1 0 0 0 1 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
SHA_fseltest_I2 SHSW_fsel
test0
MINV
LINV
STBY
SLP
• SLP and STBY (D0, D1 of address H’F1)
SLP: Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 19 of 29
• Output mode (D2 to D4 of address H’F1 and address H’F4 of D6)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
• SHA-fsel (D8 to D9 of address H’F1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the
double cut off frequency point with using.
• SHSW-fsel (D10 to D13 of address H’F1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
8. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
• Test_I2 (D14 to D15 of address H’F1)
Current of ADC analog part can be set minutely. Normally use data = 0.
0: Default (100%)
1: 150%
2: 50%
3: 80%
Address STD1[7:0] (L)
HGain-Nsel
STD2[15:8] (H)
1 1 1 1 0 0 1 0 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
Clamp level
Reset
AD_sel
CDS_buff
Low_pwr
HGstop-Hsel
• Clamp (D0 to D4 of address H’F2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data ×2 + 14
Default data is 9 = 32 LSB.
• HGstop-Hsel, HGain-Nsel (D8 to D11 of address H’F2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
• Low_PWR (D12 of address H’F2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
• ADSEL (D14 of address H’F2)
Data = 0: Select CDS_in
Data = 1: Select ADC_in
• Reset (D15 of address H’F2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 23.
Address STD1[7:0] (L) STD2[15:8] (H)
11110011 D4D3D2D7 D6 D5 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
• Address H'F3 are all testing data.
Normally set to all 0., or do not transfer the data.

HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 20 of 29
Address STD1[7:0] (L) STD2[15:8] (H)
11110100 D4D3D2D7 D6 D5 D1 D0 D12 D11 D10 D9 D8
Gray_test VD latch MON Gray code H12_Buff
• MON (D0 to D2 of address H’F4)
Select the pulse which output to pin MON (pin 60).
When D0 to D2: 0, Fix to Low When 1, ADCLK
When 2, SP1 When 3, SP2
When 4, OBP When 5, PBLK
When 6, CPDM When 7, DLL_test
• H12Baff (D3 to D6 of address H’F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer
Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)
• VD latch (D7 of address H’F4)
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling
Differential Code and Gray Code (D8 to D12 of address H’F4)
• Gray code (D8 to D9 of address H’F4)
DC output code can be change to following type.
Gray Code [1] Gray Code [0] Output Code
0 0 Binary code
0 1 Gray code
1 0 Differential encoded binary
1 1 Differential encoded gray
• Serial data setting items (D10 to D12 of address H’F4)
Setting Bit Setting Contents
Gray_test[0]
Gray_test[1] Standard data output timing control signal
(Refer to the following table)
Gray_test[2] ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
•Standard data output timing
Gray_test[1] Gray_test[0] Standard Data Output Timing
Low Low Third and fourth
Low High Fourth and fifth
High Low Fifth and sixth
High High Sixth and seventh