Rohm BD5446EFV Instruction Manual

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© 2010 ROHM Co., Ltd. All rights reserved.
Middle Power Class-D Speaker Amplifiers
Class-D Speaker Amplifier
for Digital Input
BD5446EFV
●Description
BD5446EFV is a Class D Speaker Amplifier designed for Flat-panel TVs in particular for space-saving and low-power
consumption, delivers an output power of 20W+20W. This IC employs state-of-the-art Bipolar, CMOS, and DMOS (BCD)
process technology that eliminates turn-on resistance in the output power stage and internal loss due to line resistances up
to an ultimate level. With this technology, the IC can achieve high efficiency of 87% (10W+10W output with 8Ωload). In
addition, the IC is packaged in a compact reverse heat radiation type power package to achieve low power consumption
and low heat generation and eliminates necessity of external heat-sink up to a total output power of 40W. This product
satisfies both needs for drastic downsizing, low-profile structures and many function, high quality playback of sound system.
●Features
1) BD5446EFV has two system of digital audio interface.
(I2S/LJ format, SDATA: 16 / 20 / 24bit, LRCLK: 32kHz / 44.1kHz / 48kHz, BCLK: 64fs (fixed), SYS_CLK: 256fs (fixed))
2) Within the wide range of the power supply voltage, it is possible to operate in a single power supply. (10~26V)
3) It contributes to miniaturizing, making to the thin type, and the power saving of the system by high efficiency and low heat.
4) S/N of the system can be optimized by adjusting the gain setting among 8 steps. (20~34dB / 2dB step)
5) It has the output power limitation function that can be adjusted to an arbitrary output power.
6) The decrease in sound quality because of the change of the power supply voltage is prevented with the feedback
circuitry of the output. In addition, a low noise and low distortion are achieved.
7) It provides with the best stereo DAC output for the headphone usage. As a result, the output of the selection of the
digital input in two systems is possible.
8) Eliminates pop noise generated when the power supply goes on/off, or when the power supply is suddenly shut off.
High quality muting performance is realized by using the soft-muting technology.
9) BD5446EFV is a highly reliable design to which it has various protection functions.
(High temperature protection, Under voltage protection, Output short protection, Output DC voltage protection and
Clock stop protection)
●Applications
Flat Panel TVs (LCD, Plasma), Home Audio, Desktop PC, Amusement equipments, Electronic Music equipments, etc.,
No.10075EBT14
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BD5446EFV
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●Absolute maximum ratings (Ta=25℃)
Parameter Symbol Ratings Unit Conditions
Supply voltage VCC 30 V Pin 25, 28, 29, 53, 54 *1 *2
Power dissipation Pd
2.0 W *3
4.5 W *4
6.2 W *5
Input voltage VIN -0.3 ~ 4.5 V Pin 7 ~ 18, 21 *1
Open-drain terminal voltage VERR -0.3 ~ 30 V Pin24 *1
Operating temperature range Topr -25 ~ +85 ℃
Storage temperature range Tstg -55 ~ +150 ℃
Maximum junction temperature Tjmax +150 ℃
*1 The voltage that can be applied reference to GND (Pin 6, 36, 37, 45, 46).
*2 Do not, however exceed Pd and Tjmax=150℃.
*3 70mm×70mm×1.6mm, FR4, 1-layer glass epoxy board (Copper on bottom layer 0%)
Derating in done at 16mW/℃for operating above Ta＝25℃.
*4 70mm×70mm×1.6mm, FR4, 2-layer glass epoxy board (Copper on bottom layer 100%)
Derating in done at 36mW/℃for operating above Ta＝25℃. There are thermal via on the board.
*5 70mm×70mm×1.6mm, FR4, 4-layer glass epoxy board (Copper on bottom layer 100%)
Derating in done at 49.6mW/℃for operating above Ta＝25℃. There are thermal via on the board.
●Operating conditions (Ta=25℃)
Parameter Symbol Ratings Unit Conditions
Supply voltage VCC 10 ~ 26 V Pin 25, 28, 29, 53, 54 *1 *2
Minimum load impedance
(Speaker Output) RL_SP 5.4 Ω*6
Minimum load impedance
(DAC Output) RL_DA 20 kΩPin 22, 23
*6 Do not, however exceed Pd.
* No radiation-proof design.
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BD5446EFV
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●Electrical characteristics
(Unless otherwise specified Ta=25℃,Vcc=13V,f=1kHz,RL_SP=8Ω,RL_DA=20kΩ,RESETX=3.3V,MUTEX=3.3V,PDX=3.3V,
Gain=20dB,fs=48kHz)
Item Symbol
Limits Unit Conditions
Min Typ Max
Total circ uit
Circuit current ICC1 - 45 90 mA
Pin 25, 28, 29, 53, 54
No load
Circuit current
(Power down mode) ICC2 - 1.5 3 mA
Pin 25, 28, 29, 53, 54,No load
RESETX=0V,MUTEX=0V,PDX=0V
Open-drain terminal
Low level voltage VERR - - 0.8 V Pin 24,IO=0.5mA
Regulator output voltage 1 VREG_G 5.0 5.5 6.0 V Pin 1, 27
Regulator output voltage 2 VREG_3 3.0 3.3 3.6 V Pin 5
High level input voltage VIH 2.5 - 3.3 V Pin 7 ~ 18, 21
Low level input voltage VIL 0 - 0.8 V Pin 7 ~ 18, 21
Input current
(Input pull-down terminal) IIH 33 66 132 µA Pin 7 ~ 18, 21,VIN = 3.3V
Speaker Output
Maximum momentary
output power 1 PO1 - 10 - W
THD+n=10%
GAIN=26dB *7
Maximum momentary
output power 2 PO2 - 20 - W
VCC=18V, THD+n=10%
GAIN =26dB *7
Total harmonic distortion THDSP - 0.07 - % PO=1W, BW=20~20kHz *7
Crosstalk CTSP 65 80 - dB PO=1W, BW=IHF-A *7
Output noise voltage
(Sampling mode) VNO_SP - 140 280 µVrms -∞dBFS, BW=IHF-A *7
Residual noise voltage
(Mute mode) VNOR_SP - 5 10 µVrms MUTEX=0V,-∞dBFS, BW=IHF-A *7
PWM sampling frequency
fPWM1 - 512 - KHz fs=32kHz *7
fPWM2 - 705.6 - KHz fs=44.1kHz *7
fPWM3 - 768 - KHz fs=48kHz *7
DAC Output
Maximum output voltage VOMAX 0.85 1.0 - Vrms 0dBFS,THD+n=1%
Channel Balance CB -1 0 1 dB 0dBFS
Total harmonic distortion THDDA - 0.05 0.5 % -20dBFS,BW=20~20kHz
Crosstalk CTDA 65 80 - dB 0dBFS,BW=IHF-A
Output noise voltage VNO_DA - 10 20 µVrms -∞dBFS, BW=IHF-A
Residual noise voltage VNOR_DA - 3 10 µVrms MUTEX=0V,PDX=0V,
-∞dBFS, BW=IHF-A
*7 These items show the typical performance of device and depend on board layout, parts, and power supply.
The standard value is in mounting device and parts on surface of ROHM’s board directly.
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●Electrical characteristic curves(VCC=13V,Ta=25℃,RL_SP=8Ω,RL_DA=20kΩ,Gain=20dB,fin=1kHz,fs=48kHz)
Measured by ROHM designed 4 layer board.
0
10
20
30
40
50
60
70
80
90
100
8 10 1214 161820 222426 28
VCC(V)
ICC(mA)
0
1
2
3
0 5 10 15 20 25 30 35 40
TOTAL OUTPUT POWER(W)
ICC(A)
0
4
8
12
16
20
24
28
32
36
40
44
8 10 121416 18202224 2628
VCC(V)
OUTPUT POWER(W/ch)
Fig.1 Fig.2 Fig.3
Fig.4 Fig.5 Fig.6
Fig.7 Fig.8 Fig.9
Fig.10 Fig.11 Fig.12
Current consumption
- Power su
pp
l
y
volta
g
e
Output power
- Power supply voltage
Current consumption
- Out
p
ut
p
owe
r
Efficiency - Output power Voltage gain - Frequency FFT of Output noise voltage
THD+N - Output power THD+N - Frequency Crosstalk - Output power
Crosstalk –Frequency Wave form when
Releasing Soft-mute
Wave form when
Activating Soft-mute
Sampling
Mute
10
12
14
16
18
20
22
24
26
28
30
10 100 1k 10k 100k
FREQUENCY(Hz)
VOLTAGE GAIN( dB)
Po=1W
L=22µH
C=0.47µF
C
g
=0.068
µ
F
-140
-120
-100
-80
-60
-40
-20
0
10 100 1k 10k 100k
FREQUENCY(Hz)
NOISE FFT(dBV)
Without signal
BW=20～20KHz
0.01
0.1
1
10
100
10 100 1k 10k 100k
FREQUENCY(Hz)
THD+N(%)
Po=1W
BW=20～20KHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 1 10
OUTPUT POWER(W)
CROSSTALK(dB)
BW=20～20KHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k
FREQUENCY(Hz)
CROSSTALK(dB)
Po=1W
BW=20～20KHz
fin=300Hz
P
o
=
3
.
3
W
5V/div
2V/div
S
p
eaker out
p
u
t
10ms/div
MUTEX
S
p
eaker out
p
u
t
MUTEX
10ms/div
fin=300Hz
P
o
=
3
.
3
W
2V/div
5V/div
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10 100
OUTPUT POWER(W)
THD+N(%)
BW=20～20KHz
100Hz
1KHz
6KHz
THD=10%
THD=1%
VCC=13V
VCC=18V
0
10
20
30
40
50
60
70
80
90
100
024681012
OUTPUT POWER(W/ch)
EFFICIENCY(%)
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BD5446EFV
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●Electrical characteristic curves(VCC=18V,Ta=25℃,RL_SP=8Ω,RL_DA=20kΩ,Gain=20dB,fin=1kHz,fs=48kHz)
Measured by ROHM designed 4layer board.
Fig.13 Fig.14 Fig.15
Fig.16 Fig.17 Fig.18
Fig.19
Efficiency – Output power Voltage gain - Frequency FFT of output noise voltage
THD+N - Output power THD+N - Frequency Crosstalk - Output power
Crosstalk - Frequency
20
22
24
26
28
30
32
34
36
38
40
10 100 1k 10k 100k
FREQUENCY(Hz)
V OL T AG E G AI N(d B)
Po=1W
L=22µH
C=0.47µF
Cg=0.068µF
-140
-120
-100
-80
-60
-40
-20
0
10 100 1k 10k 100k
FREQUENCY(Hz)
NOISE FFT(dBV)
Without signal
BW=20～20KHz
0.01
0.1
1
10
100
10 100 1k 10k 100k
FREQUENCY(Hz)
THD+N(%)
Po=1W
BW=20～20KHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.001 0.01 0.1 1 10 100
OUTPUT POWER(W)
CROSSTALK(dB)
BW=20～20KHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k
FREQUENCY(Hz)
CROSSTALK(dB)
Po=1W
BW=20～20KHz
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10 100
OUTPUT POWER(W)
THD+N(%)
BW=20～20KHz
6KHz
100Hz
1KHz
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20
OUTPUT POWER(W /ch)
EFFICIENCY(%)
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BD5446EFV
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© 2010 ROHM Co., Ltd. All rights reserved.
●Pin configuration and Block diagram
40
39
38
37
36
35
34
33
32
31
30
29
48
47
46
45
44
43
42
41
28
3
4
5
6
7
8
9
14
15
16
17
18
19
20
21
10
11
12
13
22
23
24
51
50
49
54
53
52
27
26
25
I2S/LJ
Interface
Gain
Selector
PWM
Modulator
×8 Over
Sampling
Digital
Filter
Control
Interface
TEST
DAC
Selector
High Temperature Protection
Under Voltage Protection
Clock Stop Protection
Output Short Protection
Output DC Voltage Protection
1
2
VCCA
NC
REG_G2
FILA
Power
Limiter
GNDA
DAC
REG_3
REG_G1
Driver
1P
Driver
1N GNDP1
REG_G1
REG_G1
VCCP1
NC
NC
NC
Driver
2P
Driver
2N
GNDP2
REG_G2
REG_G2
VCCP2
NC
NC
NC
NC
I2S/LJ
Selector
FILP
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BD5446EFV
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●Pin function explanation (Provided pin voltages are typ. Values)
No. Pin name Pin voltage Pin explanation Internal equivalence circuit
1
27
REG_G1
REG_G2 5.5V
Internal power supply pin for ch1 Gate driver
Internal power supply pin for ch2 Gate driver
Please connect the capacitor.
2 FILP 1.75V~2.55V
Bias pin for PWM signal
Please connect the capacitor.
3 PLMT 0V Power limiter setting terminal
4
FILA 2.5V
Bias pin for Analog signal
Please connect the capacitor.
5 REG3 3.3V
Internal power supply pin for Digital circuit
Please connect the capacitor.
6 GNDA 0V GND pin for Analog signal －
25
2
6
400K
25
3
6
27
4
6
50K
50K
25
5
6
500K
1
27
550K
53,54
28,29
45,46
36,37
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BD5446EFV
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No. Pin name Pin voltage Pin explanation Internal equivalence circuit
7
8
9
10
11
SYS_CLK
BCLK
LRCLK
SDATA1
SDATA2
0V Digital audio signal input pin
12 RESETX
0V
Reset pin for Digital circuit
H: Reset OFF
L: Reset ON
13 MUTEX
Speaker output mute control pin
H: Mute OFF
L: Mute ON
14 PDX
Power down control pin
H: Power down OFF
L: Power down ON
15 IIS_LJ 0V
Digital audio signal data format setting terminal
H: Left Justified format
L: I2S format
16
17
18
GAIN1
GAIN2
GAIN3
0V
Gain setting terminal
Gain=20dB~34dB, 2dB step
19
20
TEST1
TEST2 0V
Test pin
Please connect to GND.
21 SEL_DAC 0V
DAC output selection terminal
H: SDATA2 is output from the DAC
L: SDATA1 is output from the DAC
5
7,8,9
10,11
6
50K
5
12,13,14
6
50K
5
6
15
50K
5
16,17,18
6
50K
5
19,20
6
50K
5
6
21
50K
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No. Pin name Pin voltage Pin explanation Internal equivalence circuit
22
23
OUT_DAC2
OUT_DAC1 2.5V
ch2 DAC output pin
ch1 DAC output pin
Please connect it with the latter part circuit
through the capacitor.
24 ERROR 3.3V
Error flag pin
Please connect pull-up resistor.
H: While Normal
L: While Error
25 VCCA VCC
Power supply pin for Analog signal －
26,30
34,35
41,47
48,52
N.C. －Non connection pin －
500
25
24
6
25
6
22,23
50K
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BD5446EFV
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No. Pin name Pin voltage Pin explanation Internal equivalence circuit
28,29 VCCP2 Vcc Power supply pin for ch2 PWM signal
31,32 OUT2P Vcc~0V
Output pin of ch2 positive PWM
Please connect to Output LPF.
33 BSP2P
－Boot-strap pin of ch2 positive Please connect the capacitor.
36,37 GNDP2 0V GND pin for ch2 PWM signal
38,39 OUT2N Vcc~0V
Output pin of ch2 negative PWM
Please connect to Output LPF.
40 BSP2N －Boot-strap pin of ch2 negative
Please connect the capacitor.
42 BSP1N －Boot-strap pin of ch1 negative
Please connect the capacitor.
43,44 OUT1N Vcc~0V
Output pin of ch1 negative PWM
Please connect to Output LPF.
45,46 GNDP1 0V GND pin for ch1 PWM signal
49 BSP1P －Boot-strap pin of ch1 positive
Please connect the capacitor.
50,51 OUT1P Vcc~0V
Output pin of ch1 positive PWM
Please connect to Output LPF.
53,54 VCCP1 －Power supply pin for ch1 PWM signal
28,29
33
40
31,32
38,39
36,37
53,54
42
49
43,44
50,51
45,46
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BD5446EFV
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●GAIN1 pin, GAIN2 pin, GAIN3 pin function
GAIN3
(18pin)
GAIN2
(17pin)
GAIN1
(16pin) Speaker output gain
L L L 20dB
L L H 22dB
L H L 24dB
L H H 26dB
H L L 28dB
H L H 30dB
H H L 32dB
H H H 34dB
●SEL_DAC pin function
SEL_DAC
(21pin) OUT_DAC1 (23pin) OUT_DAC2 (24pin)
L The Lch signal of SDATA1 is output The Rch signal of SDATA1 is output
H The Lch signal of SDATA2 is output The Rch signal of SDATA2 is output
●RESETX pin function
RESETX
(10pin) State of Digital block
L Reset ON
H Reset OFF
●RESETX pin
RESETX
(12pin) State of Digital block
L Reset ON
H Reset OFF
●PDX pin,MUTEX pin function
PDX
(12pin)
MUTEX
(11pin) Power Down DAC output
(24,25pin)
PWM output
(33,34,38,39,43,44,48pin)
L L or H ON HiZ_Low HiZ_Low
H L OFF Normal operation
H H Normal operation
●IIS_LJ pin function
IIS_LJ
(15pin) Digital data format
L I2S
H Left Justified
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BD5446EFV
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●Input digital audio signal sampling frequency (fs) explanation
PWM sampling frequency, Soft-start, Soft-mute time, and the detection time of the DC voltage protection in the speaker
depends on sampling frequency (fs) of the digital audio input.
Sampling frequency of the
digital audio input
(fs)
PWM sampling frequency
(fpwm) Soft-start / Soft-mute time DC voltage protection in the speaker detection time
32kHz 512kHz 64msec. 64msec.
44.1kHz 705.6kHz 46msec. 46msec.
48kHz 768kHz 43msec. 43msec.
●For voltage gain (Gain setting)
BD5446EFV prescribe voltage gain at speaker output (BTL output) under the definition 0dBV (1Vrms) as full scale input of
the digital audio input signal. For example, digital audio input signal = Full scale input, Gain setting = 20dB, Load resistance
RL_SP = 8Ωwill give speaker output (BTL output) amplitude as Vo=10Vrms. (Output power Po = Vo2/RL_SP = 12.5W )
●Speaker output and DAC output
Digital audio input signal SDATA1 will be output to the speaker. (SDATA2 will not be output to the speaker. DAC output can
be selected either from digital audio input signal SDATA1 or SDATA2.)
●Format of digital audio input
・SYS_CLK: It is System Clock input signal.
It will input LRCLK, BCLK, SDATA1 (SDATA2) that synchronizes with this clock that are 256 times of sampling frequency
(256fs).
・LRCLK: It is L/R clock input signal.
It corresponds to 32kHz/44.1kHz/48kHz with those clock (fs) that are same to the sampling frequency (fs) .
The data of a left channel and a right channel for one sample is input to this section.
・BCLK: It is Bit Clock input signal.
It is used for the latch of data in every one bit by sampling frequency’s 64 times sampling frequency (64fs).
・SDATA1 & SDATA2: It is Data input signal.
It is amplitude data. The data length is different according to the resolution of the input digital audio data.
It corresponds to 16/ 20/ 24 bit.
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LRCLK
(SDATA2)
BCLK
SDATA1
Lch Rch
32 clocks 32 clocks
Fig.20 I2SData Format 64fs, 24 bit Data
MSB 22 21 20 19 18 17 16 15 14 MSB 22 21 20 19 18 17 16 15 1413 12 11 10 9 813 12 11 10 9 87 676
3
54 1
2LSB 3
54 12 LSB
MSB 18 17 9 8 7 6 5 MSB 18 1716 15 14 13 12 11 10 4321
LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
LRCLK
(SDATA2)
BCLK
SDATA1
Lch Rch
Fig.21 I2SData Format 64fs, 20 bit Data
MSB MSB
LRCLK
(SDATA2)
BCLK
SDATA1
Lch Rch
9876514 13 12 11 10 4321
LSB 9876514 13 12 11 10 4321
LSB
Fig.22 I2SData Format 64fs, 16 bit Data
1/64fs
LRCLK
(SDATA2)
BCLK
SDATA1
Lch1/64fs Rch
32 clocks 32 clocks
Fig.23 Left-Justified Data Format 64fs, 24 bit Data
MSB 22 21 20 19 18 17 16 15 14 MSB 22 21 20 19 18 17 16 15 1413 12 11 10 9 813 12 11 10 9 87 676
3
54 1
2LSB 354 12LSB
MSB 18 17 9 8 7 6 5 MSB 18 1716 15 14 13 12 11 10 4321
LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB
LRCLK
(SDATA2)
BCLK
SDATA1
Lch Rch
Fig.24 Left-Justified Data Format 64fs, 20 bit Data
MSB MSB
LRCLK
(SDATA2)
BCLK
SDATA1
Lch Rch
9876514 13 12 11 10 4321
LSB 9876514 13 12 11 10 4321
LSB
Fig.25 Left-Justified Data Format 64fs, 16 bit Data
●I2S data format
The Low section of LRCLK becomes Lch, the High section of LRCLK becomes Rch.
After changing LRCLK, second bit becomes MSB.
●Left-justified format
The High section of LRCLK becomes Lch, the Low section of LRCLK becomes Rch.
After changing LRCLK, first bit becomes MSB.
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BD5446EFV
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●Power supply start-up sequence
VCCP1 (53, 54pin)
VCCP2 (28, 29pin)
VCCA (25pin)
REG_G1 (1pin)
REG_3 (5pin)
PDX (14pin)
BCLK (8pin)
LRCLK (9pin)
Speaker output
SDATA1 (10pin)
SDATA2 (11pin)
REG_G2 (27pin)
①Power up VCCA, VCCP1, VCCP2 simultaneously.
REG_G1, REG_G2
REG_3
③Degital audio data communication.
④Set PDX to High.
⑤Set MUTEX to High.
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
t
t
t
t
t
t
t
MUTEX (13pin)
RESETX (12pin)
②Set RESETX to High after power up.
t
SYS_CLK (7pin)
Soft-start
43msec(fs=48kHz)
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●Power supply shut-down sequence
VCCP1 (53, 54pin)
VCCP2 (28, 29pin)
VCCA (25pin)
REG_G1 (1pin)
REG_3 (5pin)
RESETX (12pin)
MUTEX (13pin)
PDX (14pin)
BCLK (8pin)
LRCLK (9pin)
SDATA1 (10pin)
SDATA2 (11pin)
REG_G2 (27pin)
REG_G1, REG_G2
REG_3
①Set MUTEX to Low.
②Set PDX to Low.
③Stop digital audio date signal.
④Set RESETX to Low
⑤Power down VCCA, VCCP1, VCCP2, simultaneously.
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
t
t
t
t
t
t
t
t
SYS_CLK (7pin)
Soft-mute
43msec(fs=48kHz)
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Technical Note
16/30
BD5446EFV
www.rohm.com 2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
●About the protection function
Protection function Detecting & Releasing condition DAC
Output
PWM
Output
ERROR
Output
Output short
protection
Detecting
condition Detecting current = 10A (TYP.)
Normal
operation
HiZ_Low
(Latch)
L
(Latch)
DC voltage protection
in the speaker
Detecting
condition
PWM output Duty=0% or 100%
43msec(fs=48kHz) above fixed
HiZ_Low
(Latch)
L
(Latch)
High temperature
protection
Detecting
condition Chip temperature to be above 150℃(TYP.)
Normal
operation
HiZ_Low
H
Releasing
condition Chip temperature to be below 120℃(TYP.) Normal
operation
Under voltage
protection
Detecting
condition Power supply voltage to be below 8V (TYP.)
Normal
operation
HiZ_Low
H
Releasing
condition Power supply voltage to be above 9V (TYP.) Normal operation
Clock stop protection
Detecting
condition No change to SYS_CLK more than 1usec (TYP.) Irregular
output HiZ_Low
H
Releasing
condition Normal input to SYS_CLK Normal operation
Normal
operation
*The ERROR pin is Nch open-drain output.
*Once an IC is latched, the circuit is not released automatically even after an abnormal status is removed.
The following procedures ①or ②is available for recovery.
①After the MUTEX pin is made Low once, the MUTEX pin is returned to High again.
②Turning on the power supply again.
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Technical Note
17/30
BD5446EFV
www.rohm.com 2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
1) High temperature protection
This IC has the high temperature protection circuit that prevents thermal reckless driving under an abnormal state for the
temperature of the chip to exceed Tjmax=150℃.
Detecting condition - It will detect when MUTE pin is set High and the temperature of the chip becomes 150℃(TYP.) or
more. The speaker output is muted through a soft-mute when detected.
Releasing condition - It will release when MUTE pin is set High and the temperature of the chip becomes 120℃(TYP.)
or less. The speaker output is outputted through a soft-start when released.
OUT1P (50, 51pin)
Temperature of
IC chip junction(℃)
Speaker output
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
150℃
120℃
HiZ-Low
Soft-mute
43msec(fs=48KHz)
3.3V
ERROR (24pin)
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
t
t
t
t
t
Soft-start
43msec(fs=48KHz)
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Technical Note
18/30
BD5446EFV
www.rohm.com 2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
2) Under voltage protection
This IC has the under voltage protection circuit that make speaker output mute once detecting extreme drop of the power
supply voltage.
Detecting condition – It will detect when MUTE pin is set High and the power supply voltage becomes lower than 8V.
The speaker output is muted through a soft-mute when detected.
Releasing condition – It will release when MUTE pin is set High and the power supply voltage becomes more than 9V.
The speaker output is outputted through a soft-start when released.
OUT1P (50, 51pin)
VCCA (25pin)
Speaker output
ERROR (24pin)
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
9V
8V
HiZ-Low
Soft-mute
43msec(fs=48kHz)
3.3V
VCCP1 (53, 54pin)
VCCP2 (28, 29pin)
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
t
t
t
t
t
Soft-start
43msec(fs=48kHz)
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Technical Note
19/30
BD5446EFV
www.rohm.com 2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
3) Clock stop protection
This IC has the clock stop protection circuit that make the speaker output mute when the SYS_CLK signal of the digital
audio input stops.
Detecting condition - It will detect when MUTE pin is set High and the SYS_CLK signal stops for about 1usec or more.
The speaker output is muted through a soft-mute when detected.
Releasing condition - It will release when MUTE pin is set High and the SYS_CLK signal returns to the normal clock
operation. The speaker output is outputted through a soft-start when released.
OUT1P (50, 51pin)
SYS_CLK (7pin)
Speaker output
ERROR (24pin)
OUT_DAC2 (22pin)
OUT_DAC1 (23pin)
Clock stop Clock recover
HiZ-Low
Protection start with
about 1μsec clock stop.
3.3V
Unstable
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
t
t
t
t
t
Soft-start
43msec(fs=48kHz)
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Technical Note
20/30
BD5446EFV
www.rohm.com 2010.05 - Rev.B
© 2010 ROHM Co., Ltd. All rights reserved.
4)Output short protection(Short to the power supply)
This IC has the PWM output short protection circuit that stops the PWM output when the PWM output is short-circuited to
the power supply due to abnormality.
Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output pin
becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if
detected, and IC does the latch.
Releasing method - ①After the MUTEX pin is set Low once, the MUTEX pin is set High again.
②Turning on the power supply again.
5) Output short protection(Short to GND)
This IC has the PWM output short protection circuit that stops the PWM output when the PWM output is short-circuited to
GND due to abnormality.
Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output terminal
becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if
detected, and IC does the latch.
Releasing method – ①After the MUTEX pin is set Low once, the MUTEX pin is set High again.
②Turning on the power supply again.
ERROR (24pin)
MUTEX(13pin)
Short to GND Release from short to
GND
PWM out ： IC latches with HiZ-Low. Released from latch state.
１μsec(TYP.)
t
t
t
OUT1P (50, 51pin)
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
10A(TYP.)
Over current
t
Latch release
ERROR (24pin)
MUTEX（13pin）
Short to VCC Release from short to VCC
PWM out ： IC latches with HiZ-Low. Released from latch state.
１μsec(TYP.)
t
t
t
OUT1P (50, 51pin)
OUT1N (43, 44pin)
OUT2N (38, 39pin)
OUT2P (31, 32pin)
10A(TYP.)
Over current
t
Latch release
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