rtd DM35425HR User manual

DM35425HR
PCI Express Data Acquisition Board
User’s Manual
BDM-610010047 Rev E

RTD Embedded Technologies, Inc. | www.rtd.com ii DM35425HR User’s Manual
Revision History
Rev A Initial Release
Rev B Add Parallel Bus set up note
Add Power Consumption
Updated IDAN Dimensions Picture
Added a Channel Delay Section
Added Equation 1
Rev C Corrected Signal Names in IDAN Pin Out
Rev D Update Register Map to FPGA Rev C
i. ADC Function Block changed to 0x01031000
ii. DAC Function Block changed to 0x01032000
iii. ADIO Function Block changed to 0x01003001
iv. Add CH_FIFO_ACCESS register to ADC, DAC and ADIO
Add Section 5.6 External Clocking
Add Clock Source description
Rev E Changed references of CLK_SRC_GBL to CLK_BUS
Corrected mis-labelling of CN4 in connector picture
Changed references of “driver”to “user”, for clarification
Added mating connector info
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2017 by RTD Embedded Technologies, Inc. All rights reserved.
RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, expressMate, ExpressPlatform, HiDANplus, “MIL Value for
COTS prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, RTD, and the RTD logo are registered trademarks of RTD Embedded
Technologies, Inc (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104, PCIe/104,
PCI/104-Express and 104 are trademarks of the PC/104 Embedded Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2017 by RTD Embedded Technologies, Inc. All rights reserved.

RTD Embedded Technologies, Inc. | www.rtd.com iii DM35425HR User’s Manual
Table of Contents
1Introduction 8
1.1 Product Overview........................................................................................................................................................................ 8
1.2 Board features ............................................................................................................................................................................ 8
1.3 Ordering Information................................................................................................................................................................... 8
1.4 Contact Information .................................................................................................................................................................... 8
1.4.1 Sales Support 8
1.4.2 Technical Support 9
2Specifications 10
2.1 Operating Conditions ................................................................................................................................................................ 10
2.2 Electrical Characteristics .......................................................................................................................................................... 10
2.2.1 Analog Input FFT plots 12
2.2.2 Analog input histograms 12
3Board Connection 13
3.1 Board Handling Precautions ..................................................................................................................................................... 13
3.2 Physical Characteristics............................................................................................................................................................ 13
3.3 Connectors and Jumpers.......................................................................................................................................................... 14
3.3.1 Bus Connectors 14
CN1(Top) & CN2(Bottom): PCIe Connector 14
3.3.2 DM35425 External I/O Connectors 15
CN3 & CN4: Analog/Digital I/O Connector 15
Other Connectors 16
3.3.3 Jumpers 16
3.4 Steps for Installing .................................................................................................................................................................... 17
4IDAN Connections 18
4.1 Module Handling Precautions................................................................................................................................................... 18
4.2 Physical Characteristics............................................................................................................................................................ 18
4.3 Connectors................................................................................................................................................................................ 18
4.3.1 Bus Connectors 18
CN1(Top) & CN2(Bottom): PCIe Connector 18
4.4 Connectors................................................................................................................................................................................ 19
4.4.1 External I/O Connectors 19
P2 Connector - 68-pin Subminiature “D” Female Connector 19
P3 Connector - 68-pin Subminiature “D” Female Connector 20
P2 Connector - 62-pin High Density “D” Female Connector 21
P3 Connector - 62-pin High Density “D” Female Connector 22
4.5 Steps for Installing .................................................................................................................................................................... 23
5Functional Description 24
5.1 Block Diagram........................................................................................................................................................................... 24
5.2 Control Interface with DMA Engine........................................................................................................................................... 24
5.3 Analog input.............................................................................................................................................................................. 24
5.3.1 Initialization 25
5.3.2 Simplified block diagram of analog input 25
Single-Ended Input Mode 25
Differential Input Mode 25
Full-Scale Input Range 25
Bipolar/Unipolar Mode 26

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Channel Delay 26
Effective Sampling Rate 26
5.4 Analog output............................................................................................................................................................................ 27
5.4.1 Initializing the DAC Converter 27
5.4.2 Simplified block diagram of analog output 27
5.5 Advanced Digital I/O ................................................................................................................................................................. 28
DMA 28
Advanced Interrupts 28
Parallel Bus Mode 28
5.6 External Clocking...................................................................................................................................................................... 29
6Register Address Space 30
Register Types 30
Clock Source 30
6.1 BAR0 –General Board Control ................................................................................................................................................ 31
6.1.1 GBC_BRD_RST (Read/Write) 31
6.1.2 GBC_EOI (Read/Clear) 31
6.1.3 GBC_REV (Read-Only) 31
6.1.4 GBC_FMT (Read-Only) 31
6.1.5 GBC_PDP (Read-Only) 31
6.1.6 GBC_BUILD (Read-Only) 31
6.1.7 GBC_SYS_CLK_FREQ (Read Only) 32
6.1.8 GBC_IRQ_STATUS (Read/Clear) 32
6.1.9 GBC_DIRQ_STATUS (Read/Clear) 32
6.1.10 FBn_ID (Read-Only) 32
6.1.11 FBn_Offset (Read-Only) 32
6.1.12 FBn_Offset_DMA (Read-Only) 32
6.2 BAR2 –Functional Block Standard DMA ................................................................................................................................. 33
6.2.1 FB_DMAm_Action (Read/Write) 33
6.2.2 FB_DMAm_LAST_ACTION (READ/WRITE) 33
6.2.3 FB_DMAm_Setup (Read/Write) 34
6.2.4 FB_DMAm_Stat_Used (Read/Write) 34
6.2.5 FB_DMAm_Stat_Invalid (Read/Write) 34
6.2.6 FB_DMAm_Stat_Overflow (Read/Write) 34
6.2.7 FB_DMAm_Stat_Underflow (Read/Write) 34
6.2.8 FB_DMAm_Stat_Complete (Read/Write) 34
6.2.9 FB_DMAm_Current_Buffer (Read-Only) 34
6.2.10 FB_DMAm_COUNT (Read-Only) 34
6.2.11 FB_DMAm_RD_FIFO_CNT (Read-Only) 34
6.2.12 FB_DMAm_WR_FIFO_CNT (Read-Only) 35
6.2.13 FB_DMAm_ADDRESSn (Read/Write) 35
6.2.14 FB_DMAm_SIZEn (Read/Write) 35
6.2.15 FB_DMAm_CTRLn (Read/Write) 35
6.2.16 FB_DMAm_STATn (Read/Clear) 35
6.3 BAR2 –ADC Functional Block ................................................................................................................................................. 36
6.3.1 FB_ID (Read-Only) 36
6.3.2 FB_DMA_CHANNELS (Read -Only) 37
6.3.3 FB_DMA_BUFFERS (Read-Only) 37
6.3.4 Mode_Status (Read/Write, Read-Only) 37
6.3.5 CLK_SRC (Read/Write) 37
6.3.6 START_TRIG (Read/Write) 37
6.3.7 STOP_TRIG (Read/Write) 37
6.3.8 CLK_DIV (Read/Write) 37
6.3.9 CLK_DIV_CNTR (Read Only) 38
6.3.10 PRE_TRIGGER_CAPTURE (Read/Write) 38
6.3.11 POST_STOP_CAPTURE (Read/Write) 38
6.3.12 SAMPLE_CNT (Read Only) 38
6.3.13 INT_ENA (Maskable Read/Write) 38
6.3.14 INT_STAT (Read/Clear) 38
6.3.15 CLK_BUSn 38
6.3.16 CHn_FRONT_END_CONFIG (Maskable Read/Write) 39
6.3.17 CHn_FIFO_DATA_CNT (Read) 39
6.3.18 CHn_FILTER (Read/Write) 39

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6.3.19 CHn_THRESH_STAT(Read/Clear) 40
6.3.20 CHn_THRESH_ENA (Read/Write) 40
6.3.21 CHn_THRESH_LOW (Read/Write) 40
6.3.22 CHn_THRESH_HIGH (Read/Write) 41
6.3.23 CHn_LAST_SAMPLE (Read-Only) 41
6.3.24 CH_FIFO_ACCESS (Read/Write) 41
6.4 BAR2 –DAC Functional Block ................................................................................................................................................. 42
6.4.1 FB_ID (Read-Only) 42
6.4.2 FB_DMA_CHANNELS (Read -Only) 42
6.4.3 FB_DMA_BUFFERS (Read-Only) 42
6.4.4 Mode_Status (Read/Write, Read-Only) 42
6.4.5 CLK_SRC (Read/Write) 43
6.4.6 START_TRIG (Read/Write) 43
6.4.7 STOP_TRIG (Read/Write) 43
6.4.8 CLK_DIV (Read/Write) 43
6.4.9 CLK_DIV_CNTR (Read Only) 43
6.4.10 POST_STOP_CONVERSIONS (Read/Write) 43
6.4.11 CONVERSION_CNT (Read Only) 43
6.4.12 INT_ENA (Maskable Read/Write) 44
6.4.13 INT_STAT (Read/Clear) 44
6.4.14 CLK_BUSn 44
6.4.15 CH_FRONT_END_CONFIG (Maskable Read/Write) 44
6.4.16 CHn_FIFO_DATA_CNT (Read) 45
6.4.17 CH_MARKER_STAT(Read/Clear) 45
6.4.18 CH_MARKER_ENA (Read/Write) 45
6.4.19 CH_LAST_CONVERSION (Read/Write) 45
6.4.20 CH_FIFO_ACCESS (Read/Write) 45
6.5 BAR2 –Advanced Digital I/O Functional Block ........................................................................................................................ 46
6.5.1 FB_ID (Read-Only) 46
6.5.2 FB_DMA_CHANNELS (Read -Only) 46
6.5.3 FB_DMA_BUFFERS (Read-Only) 46
6.5.4 Mode_Status (Read/Write, Read-Only) 46
6.5.5 CLK_SRC (Read/Write) 47
6.5.6 START_TRIG (Read/Write) 47
6.5.7 STOP_TRIG (Read/Write) 47
6.5.8 CLK_DIV (Read/Write) 47
6.5.9 CLK_DIV_CNTR (Read Only) 47
6.5.10 PRE_TRIGGER_CAPTURE (Read/Write) 48
6.5.11 POST_STOP_CAPTURE (Read/Write) 48
6.5.12 SAMPLE_CNT (Read Only) 48
6.5.13 INT_ENA (Maskable Read/Write) 48
6.5.14 INT_STAT (Read/Clear) 48
6.5.15 CLK_BUSn 48
6.5.16 DIO_INPUT (Read Only) 49
6.5.17 DIO_OUTPUT (Read/Write) 49
6.5.18 DIO_DIRECTION (Read/Write) 49
6.5.19 ADV_INT_MODE (Read/Write) 50
6.5.20 ADV_INT_MASK (Read/Write) 50
6.5.21 ADV_INT_COMP (Read/Write) 50
6.5.22 ADV_INT_CAPT (Read/Write) 50
6.5.23 P_BUS_EN (Read/Write) 50
6.5.24 P_BUS_READY_EN (Read/Write) 50
6.5.25 CH_FIFO_ACCESS (Read/Write) 50
6.6 BAR2 –External Clocking Functional Block............................................................................................................................. 51
6.6.1 FB_ID (Read-Only) 51
6.6.2 FB_DMA_CHANNELS (Read -Only) 51
6.6.3 FB_DMA_BUFFERS (Read-Only) 51
6.6.4 EXT_CLK_IN (Read-Only) 51
6.6.5 EXT_CLK_GATE_IN (Read Only) 51
6.6.6 EXT_CLK_DIR (Read/Write) 51
6.6.7 EXT_CLK_EDGE (Read/Write) 52
6.6.8 EXT_CLK_PWn (Read/Write) 52
6.6.9 EXT_CLKn_CFG (Read/Write) 52

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7Calibration 53
7.1 Required Equipment ................................................................................................................................................................. 53
7.2 ADC Calibration ........................................................................................................................................................................ 54
7.2.1 Bipolar Calibration 54
Bipolar Range Adjustment: -5 to +5 V 54
Bipolar Range Adjustment: -10 to +10 V 54
Bipolar Range Ideal Bit Weight 54
7.2.2 Unipolar Calibration 54
Unipolar Range Ideal Bit Weight 55
7.2.3 Gain Adjustment 55
7.3 DAC Calibration ........................................................................................................................................................................ 56
8Troubleshooting 57
9Additional Information 58
9.1 PC/104 Specifications............................................................................................................................................................... 58
9.2 PCI and PCI Express Specification .......................................................................................................................................... 58
10 Limited Warranty 59
Table of Figures
Figure 1: Channel FFT............................................................................................................................................................................................ 12
Figure 2: Histogram ................................................................................................................................................................................................ 12
Figure 3: Board Dimensions ................................................................................................................................................................................... 13
Figure 4: Board Connections .................................................................................................................................................................................. 14
Figure 5: Example 104™Stack............................................................................................................................................................................... 17
Figure 6: IDAN Dimensions .................................................................................................................................................................................... 18
Figure 7: Example IDAN System ............................................................................................................................................................................ 23
Figure 8: DM35425 Block Diagram......................................................................................................................................................................... 24
Figure 9: Filter Response with each ORDER Value............................................................................................................................................... 40
Figure 10: DM35425HR Trimpots........................................................................................................................................................................... 53
Table of Tables
Table 1: Ordering Options ........................................................................................................................................................................................ 8
Table 2: Operating Conditions ................................................................................................................................................................................ 10
Table 3: Electrical Characteristics .......................................................................................................................................................................... 10
Table 4: CN3 Differential Mode Pin-out.................................................................................................................................................................. 15
Table 5: CN3 Single-Ended Mode Pin-out.............................................................................................................................................................. 15
Table 6: CN4 Differential Mode Pin-out.................................................................................................................................................................. 16
Table 7: CN4 Single-Ended Mode Pin-out.............................................................................................................................................................. 16
Table 8: IDAN- DM35425 68-Pin Subminiature "D" Connector.............................................................................................................................. 19
Table 9: IDAN- DM35425 68-Pin Subminiature "D" Connector.............................................................................................................................. 20
Table 10: IDAN- DM35425 62-Pin High Density "D" Connector............................................................................................................................. 21
Table 11: IDAN- DM35425 62-Pin High Density "D" Connector............................................................................................................................. 22
Table 12: ADC Bipolar Code ( ±5 V Input Range) ................................................................................................................................................. 26
Table 13: ADC Bipolar Code ( ±10 V Input Range) ............................................................................................................................................... 26
Table 14: ADC Unipolar Code ( 0 to 10 V Input Range)......................................................................................................................................... 26
Table 15: BAR0 Registers ...................................................................................................................................................................................... 31
Table 16: DMA Registers........................................................................................................................................................................................ 33
Table 17: Multi-Channel ADC Functional Block ..................................................................................................................................................... 36
Table 18: ADC Full-Scale Settings ......................................................................................................................................................................... 39
Table 19: Multi-Channel DAC Functional Block ..................................................................................................................................................... 42

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Table 20: DAC Full-Scale Settings ......................................................................................................................................................................... 44
Table 21: Digital I/O Functional Block..................................................................................................................................................................... 46
Table 22:External Clocking Functional Block ......................................................................................................................................................... 51
Table 23: Data Values for Calibrating Bipolar 10 V Range .................................................................................................................................... 54
Table 24: Data Values for Calibrating Bipolar 20 V Range .................................................................................................................................... 54
Table 25: ADC Bit Weights, Bipolar........................................................................................................................................................................ 54
Table 26: Data Values for Calibrating Bipolar 20 V Range .................................................................................................................................... 55
Table 27: ADC Bit Weights, Unipolar...................................................................................................................................................................... 55
Table 28: Trimpots for Calibrating ADC Gain ......................................................................................................................................................... 55
Table 29: DAC Bit Weights..................................................................................................................................................................................... 56
Table 30: Trimpots for Calibrating DAC Gain ......................................................................................................................................................... 56

RTD Embedded Technologies, Inc. | www.rtd.com 8DM35425HR User’s Manual
1Introduction
1.1 Product Overview
The DM35425 is a software configurable high-speed, 12-bit data acquisition module in the PCIe/104 format. This module provides 16
differential or 32 single-ended analog input channels, with programmable gain and input ranges. The DM35425 also features four 12-bit high-
speed analog outputs with programmable output ranges, and a 32-bit port of digital I/O.
1.2 Board features
PCIe x 1 Interface
oUniversal Board can be used with a PCIe/104 Type 1 or Type 2 host
oDedicated DMA channel per I/O for maximum efficiency
Analog inputs:
o16 Differential or 32 Single-ended analog input channels
o1.25 MSPS maximum input sampling rate
o12 bits resolution
oProgrammable single ended or differential inputs per channels
oThreshold detection can generate an interrupt, or be used as a start or stop trigger
oConfigurable IIR filter on each channel
Analog outputs:
o4 channels high-speed
o12 bit D/A converters
o±5, +5, ±10, & +10V output ranges
o7 µs full-scale settling time
Advanced Digital I/O
o32-bit port of digital I/O
oBit programmable direction
oAdvanced digital interrupts
oParallel Bus Mode
External Clocking
oProvides 6 external clocking pins that can be used as inputs or outputs
oProvides external triggering
oExternal gate for each clock pin
1.3 Ordering Information
The DM35425 is available with the following options:
Table 1: Ordering Options
Part Number
Description
DM35425HR
PCIe/104 Analog I/O dataModule
IDAN-DM35425HR-62S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 62-pin D-Sub Connector
IDAN-DM35425HR-68S
PCIe/104 Analog I/O dataModule in IDAN enclosure with 68-pin High-Density Connector
The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to
create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus High Reliability
Intelligent Data Acquisition Node. Contact RTD sales for more information on our high reliability systems.
1.4 Contact Information
1.4.1 SALES SUPPORT
For sales inquiries, you can contact RTD Embedded Technologies sales via the following methods:

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Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]
1.4.2 TECHNICAL SUPPORT
If you are having problems with you system, please try the steps in the Troubleshooting section of this manual on page 57.
For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the
following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]

RTD Embedded Technologies, Inc. | www.rtd.com 10 DM35425HR User’s Manual
2Specifications
2.1 Operating Conditions
Table 2: Operating Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
Vcc5
5V Supply Voltage
4.75
5.25
V
Vcc3
3.3V Supply Voltage
n/a
n/a
V
Vcc12
12V Supply Voltage
n/a
n/a
V
Vcc-12
-12V Supply Voltage
n/a
n/a
V
Ta
Operating Temperature
-40
+70
C
Ts
Storage Temperature
-55
+125
C
RH
Relative Humidity
Non-Condensing
0
90%
%
MTBF
Mean Time Before Failure
Telcordia Issue 2
30°C, Ground benign, controlled
TBD
Hours
2.2 Electrical Characteristics
Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Typical
Max
Unit
P
Power Consumption
Vcc5 = 5.0V
4.35
W
Icc5
5V Input Supply Current
Active
0.87
A
PCIe/104 Bus
Differential Output Voltage
0.8
1.2
V
DC Differential TX Impedance
80
120
Ω
Differential Input Voltage
0.175
1.2
V
DC Differential RX Impedance
80
120
Ω
Electrical Idle Detect Threshold
65
175
mV
Analog to Digital Converter
Linear Input Voltage
IN+ or IN-
-10
+10
V
FSR
Full-Scale Differential Input
Voltage
VIN=(IN+ -IN-)
G = PGA Gain




V
Resolution
12
Bits
Data Rate
1.25
MSPS
Input Impedance
>6
MΩ
ENOB
Inputs= 0.8dBFS @ 10Khz
Single-Ended, ±5V
11.55
Bits
SNR
Inputs= 0.8dBFS @ 10Khz
Single-Ended, ±5V
70.54
dB
SINAD
Inputs= 0.8dBFS @ 10Khz
Single-Ended, ±5V
70.44
dB
THD
Inputs= 0.8dBFS @ 10Khz
Single-Ended, ±5V
-86.78
dB
SFDR
Inputs= 0.8dBFS @ 10Khz
Single-Ended, ±5V
89.50
dB
Third Order Intermodulation
FIN1=0.8dBFS @
10.0708Khz
FIN2=0.8dBFS @
39.0625Khz
83.4
dB
Noise Free Bits
Inputs Grounded
Differential Inputs, ±5V
11
Bits
Channel to Channel Cross Talk
No Channel Delay
-20.46
dB
½ Sample Delay
-41.68
dB
Sample Delay
-59.54
dB
2 Sample Delay
-66.41
dB
G
Gains
0.5,1,2,4,8
Digital to Analog Converter
Full-Scale Analog Output Voltage
G = 1
-5
4.99756
V

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Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Typical
Max
Unit
Resolution
12
Bits
Relative Accuracy
±1
LSB
Gain Error
±2
LSB
Settling Time
5
µs
Output Current
5
mA
Slew Rate
2
V/µs
G
Gains
1,2
Output Impedance
45
Ω
Digital I/O
VIL
Input High Voltage
2
5.5
V
VIH
Input Low Voltage
-0.5
0.8
V
VOL
Output Low Voltage
IO= 12mA
0.0
0.4
V
VOH
Output High Voltage
IO= -12mA
2.6
3.3
V
5V Output
CN3, CN4
200
mA

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2.2.1 ANALOG INPUT FFT PLOTS
In Figure 1, a coherent 10 kHz sine wave signal was attached to input Channel 0 in the +/-5V, Single-ended mode. The FFT absolute value
was calculated using 8192 data sample.
Figure 1: Channel FFT
2.2.2 ANALOG INPUT HISTOGRAMS
In Figure 2 you can see a histogram of samples from sampling a grounded input in +/-10 V, differential input range. The number of samples is
32768.
Figure 2: Histogram
-140
-120
-100
-80
-60
-40
-20
0
0 100 200 300 400 500 600
dBFS
Frequency (kHz)
0
5000
10000
15000
20000
25000
30000
-1 0 1
Frequency
Bin
ADC Noise Floor

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3Board Connection
3.1 Board Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your board in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic
environment, and use a grounded workbench for testing and handling of your hardware.
3.2 Physical Characteristics
Weight: Approximately 55 g (0.12 lbs.)
Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W)
Figure 3: Board Dimensions

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3.3 Connectors and Jumpers
Figure 4: Board Connections
3.3.1 BUS CONNECTORS
CN1(Top) & CN2(Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 58)
The DM35425 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
CN1 & CN2: PCIe Connector
CN3: Analog/Digital I/O
CN4: Analog/Digital I/O

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3.3.2 DM35425 EXTERNAL I/O CONNECTORS
CN3 & CN4: Analog/Digital I/O Connector
The Digital I/O Connector is a 2 x 25, 0.1” spacing right-angle connector. The pin assignments are shown in Tables below. A typical mating
connector is an FCI 65043-012LF. Pin 1 is indicated by a square solder pad on the board.
Table 4: CN3 Differential Mode Pin-out
AIN0+
1
2
AIN0-
AIN1+
3
4
AIN1-
AIN2+
5
6
AIN2-
AIN3+
7
8
AIN3-
AIN4+
9
10
AIN4-
AIN5+
11
12
AIN5-
AIN6+
13
14
AIN6-
AIN7+
15
16
AIN7-
AOUT0
17
18
AGND
AOUT1
19
20
AGND
AGND
21
22
AGND
DIO7
23
24
DIO15
DIO6
25
26
DIO14
DIO5
27
28
DIO13
DIO4
29
30
DIO12
DIO3
31
32
DIO11
DIO2
33
34
DIO10
DIO1
35
36
DIO9
DIO0
37
38
DIO8
EXT_CLK_2
39
40
GND
EXT_CLK_3
41
42
EXT_CLK_4
EXT_CLK_5
43
44
EXT_CLK_6
EXT_CLK_7
45
46
Reserved
Reserved
47
48
+5V
Reserved
49
50
GND
Table 5: CN3 Single-Ended Mode Pin-out
AIN0
1
2
AIN8
AIN1
3
4
AIN9
AIN2
5
6
AIN10
AIN3
7
8
AIN11
AIN4
9
10
AIN12
AIN5
11
12
AIN13
AIN6
13
14
AIN14
AIN7
15
16
AIN15
AOUT0
17
18
AGND
AOUT1
19
20
AGND
AGND
21
22
AGND
DIO7
23
24
DIO15
DIO6
25
26
DIO14
DIO5
27
28
DIO13
DIO4
29
30
DIO12
DIO3
31
32
DIO11
DIO2
33
34
DIO10
DIO1
35
36
DIO9
DIO0
37
38
DIO8
EXT_CLK_2
39
40
GND
EXT_CLK_3
41
42
EXT_CLK_4
EXT_CLK_5
43
44
EXT_CLK_6
EXT_CLK_7
45
46
Reserved
Reserved
47
48
+5V
Reserved
49
50
GND

RTD Embedded Technologies, Inc. | www.rtd.com 16 DM35425HR User’s Manual
Table 6: CN4 Differential Mode Pin-out
AIN8+
1
2
AIN8-
AIN9+
3
4
AIN9-
AIN10+
5
6
AIN10-
AIN11+
7
8
AIN11-
AIN12+
9
10
AIN12-
AIN13+
11
12
AIN13-
AIN14+
13
14
AIN14-
AIN15+
15
16
AIN15-
AOUT2
17
18
AGND
AOUT3
19
20
AGND
AGND
21
22
AGND
DIO23
23
24
DIO31
DIO22
25
26
DIO30
DIO21
27
28
DIO29
DIO20
29
30
DIO28
DIO19
31
32
DIO27
DIO18
33
34
DIO26
DIO17
35
36
DIO25
DIO16
37
38
DIO24
EXT_CLK_GATE2
39
40
GND
EXT_CLK_GATE3
41
42
EXT_CLK_GATE4
EXT_CLK_GATE5
43
44
EXT_CLK_GATE6
EXT_CLK_GATE7
45
46
Reserved
Reserved
47
48
+5V
Reserved
49
50
GND
Table 7: CN4 Single-Ended Mode Pin-out
AIN16
1
2
AIN24
AIN17
3
4
AIN25
AIN18
5
6
AIN26
AIN19
7
8
AIN27
AIN20
9
10
AIN28
AIN21
11
12
AIN29
AIN22
13
14
AIN30
AIN23
15
16
AIN31
AOUT2
17
18
AGND
AOUT3
19
20
AGND
AGND
21
22
AGND
DIO23
23
24
DIO31
DIO22
25
26
DIO30
DIO21
27
28
DIO29
DIO20
29
30
DIO28
DIO19
31
32
DIO27
DIO18
33
34
DIO26
DIO17
35
36
DIO25
DIO16
37
38
DIO24
EXT_CLK_GATE2
39
40
GND
EXT_CLK_GATE3
41
42
EXT_CLK_GATE4
EXT_CLK_GATE5
43
44
EXT_CLK_GATE6
EXT_CLK_GATE7
45
46
Reserved
Reserved
47
48
+5V
Reserved
49
50
GND
Other Connectors
CN5 and CN6 are for Factory Use only
3.3.3 JUMPERS
There are no jumpers on the board.

RTD Embedded Technologies, Inc. | www.rtd.com 17 DM35425HR User’s Manual
3.4 Steps for Installing
1. Always work at an ESD protected workstation, and wear a grounded wrist-strap.
2. Turn off power to the PC/104 system or stack.
3. Select and install stand-offs to properly position the module on the stack.
4. Remove the module from its anti-static bag.
5. Check that pins of the bus connector are properly positioned.
6. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
7. Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack.
8. Gently and evenly press the module onto the PC/104 stack.
9. If any boards are to be stacked above this module, install them.
10. Attach any necessary cables to the PC/104 stack.
11. Re-connect the power cord and apply power to the stack.
12. Boot the system and verify that all of the hardware is working properly.
Figure 5: Example 104™Stack

RTD Embedded Technologies, Inc. | www.rtd.com 18 DM35425HR User’s Manual
4IDAN Connections
4.1 Module Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your module in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the module by the aluminum enclosure, and do not touch the components or connectors. Handle the
module in an antistatic environment, and use a grounded workbench for testing and handling of your hardware.
4.2 Physical Characteristics
Weight: Approximately 0.33 Kg (0.72 lbs.)
Dimensions: 151.972 mm L x 129.978 mm W x 34.011 mm H (5.983 in L x 5.117 in W x 1.339 in H)
Figure 6: IDAN Dimensions
4.3 Connectors
4.3.1 BUS CONNECTORS
CN1(Top) & CN2(Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 58)
The DM35425 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.

RTD Embedded Technologies, Inc. | www.rtd.com 19 DM35425HR User’s Manual
4.4 Connectors
4.4.1 EXTERNAL I/O CONNECTORS
P2 Connector - 68-pin Subminiature “D” Female Connector
Connector Part #: Amp 749070-7
Sample Mating Connector: Amp 786090-7(IDC Crimp)
Table 8: IDAN- DM35425 68-Pin Subminiature "D" Connector
IDAN Pin#
Signal
DM35425 Pin #
1
AIN0+/AIN0
CN3
1
2
AIN0-/AIN8
CN3
2
3
AIN1+/AIN1
CN3
3
4
AIN1-/AIN9
CN3
4
5
AIN2+/AIN2
CN3
5
6
AIN2-/AIN10
CN3
6
7
AIN3+/AIN3
CN3
7
8
AIN3-/AIN11
CN3
8
9
AIN4+/AIN4
CN3
9
10
AIN4-/AIN12
CN3
10
11
AIN5+/AIN5
CN3
11
12
AIN5-/AIN13
CN3
12
13
AIN6+/AIN6
CN3
13
4
AIN6-/AIN14
CN3
14
15
AIN7+/AIN7
CN3
15
16
AIN7-/AIN15
CN3
16
17
AOUT0
CN3
17
18
AGND
CN3
18
19
AOUT1
CN3
19
20
AGND
CN3
20
21
AGND
CN3
21
22
AGND
CN3
22
23
DIO7
CN3
23
24
DIO15
CN3
24
25
DIO6
CN3
25
26
DIO14
CN3
26
27
DIO5
CN3
27
28
DIO13
CN3
28
29
DIO4
CN3
29
30
DIO12
CN3
30
31
DIO3
CN3
31
32
DIO11
CN3
32
33
DIO2
CN3
33
34
DIO10
CN3
34
Table 8: IDAN- DM35425 68-Pin Subminiature "D" Connector
IDAN Pin#
Signal
DM35425 Pin #
35
DIO1
CN3
35
36
DIO9
CN3
36
37
DIO0
CN3
37
38
DIO8
CN3
38
39
EXT_CLK_2
CN3
39
40
GND
CN3
40
41
EXT_CLK_3
CN3
41
42
EXT_CLK_4
CN3
42
43
EXT_CLK_5
CN3
43
44
EXT_CLK_6
CN3
44
45
EXT_CLK_7
CN3
45
46
Reserved
CN3
46
47
Reserved
CN3
47
48
+5V
CN3
48
49
Reserved
CN3
49
50
GND
CN3
50
51
N/C
52
N/C
53
N/C
54
N/C
55
N/C
56
N/C
57
N/C
58
N/C
59
N/C
60
N/C
61
N/C
62
N/C
63
N/C
64
N/C
65
N/C
66
N/C
67
N/C
68
N/C

RTD Embedded Technologies, Inc. | www.rtd.com 20 DM35425HR User’s Manual
P3 Connector - 68-pin Subminiature “D” Female Connector
Connector Part #: Amp 749070-7
Sample Mating Connector: Amp 786090-7(IDC Crimp)
Table 9: IDAN- DM35425 68-Pin Subminiature "D" Connector
IDAN Pin#
Signal
DM35425 Pin #
1
AIN8+/AIN16
CN4
1
2
AIN8-/AIN24
CN4
2
3
AIN9+/AIN17
CN4
3
4
AIN9-/AIN25
CN4
4
5
AIN10+/AIN18
CN4
5
6
AIN10-/AIN26
CN4
6
7
AIN11+/AIN19
CN4
7
8
AIN11-/AIN27
CN4
8
9
AIN12+/AIN20
CN4
9
10
AIN12-/AIN28
CN4
10
11
AIN13+/AIN21
CN4
11
12
AIN13-/AIN29
CN4
12
13
AIN14+/AIN22
CN4
13
4
AIN14-/AIN30
CN4
14
15
AIN15+/AIN23
CN4
15
16
AIN15-/AIN31
CN4
16
17
AOUT2
CN4
17
18
AGND
CN4
18
19
AOUT3
CN4
19
20
AGND
CN4
20
21
AGND
CN4
21
22
AGND
CN4
22
23
DIO23
CN4
23
24
DIO31
CN4
24
25
DIO22
CN4
25
26
DIO30
CN4
26
27
DIO21
CN4
27
28
DIO29
CN4
28
29
DIO20
CN4
29
30
DIO28
CN4
30
31
DIO19
CN4
31
32
DIO27
CN4
32
33
DIO18
CN4
33
34
DIO26
CN4
34
Table 8: IDAN- DM35425 68-Pin Subminiature "D" Connector
IDAN Pin#
Signal
DM35425 Pin #
35
DIO17
CN4
35
36
DIO25
CN4
36
37
DIO16
CN4
37
38
DIO24
CN4
38
39
EXT_CLK_GATE2
CN4
39
40
GND
CN4
40
41
EXT_CLK_GATE3
CN4
41
42
EXT_CLK_GATE4
CN4
42
43
EXT_CLK_GATE5
CN4
43
44
EXT_CLK_GATE6
CN4
44
45
EXT_CLK_GATE7
CN4
45
46
Reserved
CN4
46
47
Reserved
CN4
47
48
+5V
CN4
48
49
Reserved
CN4
49
50
GND
CN4
50
51
N/C
52
N/C
53
N/C
54
N/C
55
N/C
56
N/C
57
N/C
58
N/C
59
N/C
60
N/C
61
N/C
62
N/C
63
N/C
64
N/C
65
N/C
66
N/C
67
N/C
68
N/C