Segger J-Link User manual

A product of SEGGER Microcontroller GmbH & Co. KG
J-Link / J-Trace
User Guide
JTAG Emulators for
ARM Cores
Release date: 07-12-04

2
J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
Disclaimer
Specifications written in this document are believed to be accurate, but are not guar-
anteed to be entirely free of error. The information in this manual is subject to
change for functional or performance improvements without notice. Please make sure
your manual is the latest edition. While the information herein is assumed to be
accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no
responsibility for any errors or omissions. The manufacturer makes and you receive
no warranties or conditions, express, implied, statutory or in any communication with
you. The manufacturer specifically disclaims any implied warranty of merchantability
or fitness for a particular purpose.
Copyright notice
You may not extract portions of this manual or modify the PDF file in any way without
the prior written permission of the manufacturer. The software described in this doc-
ument is furnished under a license and may only be used or copied in accordance
with the terms of such a license.
©2007 SEGGER Microcontroller GmbH & Co. KG, Hilden / Germany
Trademarks
Names mentioned in this manual may be trademarks of their respective companies.
Brand and product names are trademarks or registered trademarks of their respec-
tive holders.
Contact address
SEGGER Microcontroller GmbH & Co. KG
Heinrich-Hertz-Str. 5
D-40721 Hilden
Germany
Tel.[phone]
Fax.[phone]
Email: [e-mail]
Internet: http://www.segger.com
Revisions
This manual describes the J-Link and J-Trace device.
For further information on topics or routines not yet specified, please contact us.
Revision Date By Explanation
29 070912 SK Chapter "Hardware", section "Target board design"
updated.
28 070912 SK
Chapter "Related software":
Section "J-LinkSTR91x Commander" added.
Chapter "Device specifics":
Section "ST Microelectronics" added.
Section "Texas Instruments" added.
Subsection "AT91SAM9" added.
28 070912 AG Chapter "Working with J-Link/J-Trace":
Section "Command strings" updated.
27 070827 TQ Chapter "Working with J-Link/J-Trace":
Section "Command strings" updated.

J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
3
26 070710 SK
Chapter "Introduction":
Section "Features of J-Link" updated.
Chapter "Background Information":
Section "Embedded Trace Macrocell" added.
Section "Embedded Trace Buffer" added.
25 070516 SK
Chapter "Working with J-Link/J-Trace":
Section "Reset strategies in detail"
- "Software, for Analog Devices ADuC7xxx
MCUs" updated
- "Software, for ATMEL AT91SAM7 MCUs"
added.
Chapter "Device specifics"
Section "Analog Devices" added.
Section "ATMEL" added.
24 070323 SK
Chapter "Setup":
"Uninstalling the J-Link driver" updated.
"Supported ARM cores" updated.
23 070320 SK Chapter "Hardware":
"Using the JTAG connector with SWD" updated.
22 070316 SK Chapter "Hardware":
"Using the JTAG connector with SWD" added.
21 070312 SK
Chapter "Hardware":
"Differences between different versions"
supplemented.
20 070307 SK Chapter "J-Link / J-Trace related software":
"J-Link GDB Server" licensing updated.
19 070226 SK
Chapter "J-Link / J-Trace related software" updated
and reorganized.
Chapter "Hardware"
"List of OEM products" updated
18 070221 SK Chapter "Device specifics" added
Subchapter "Command strings" added
17 070131 SK
Chapter "Hardware":
"Version 5.3": Current limits added
"Version 5.4" added
Chapter "Setup":
"Installating the J-Link USB driver" removed.
"Installing the J-Link software and documentation
pack" added.
Subchapter "List of OEM products" updated.
"OS support" updated
16 061222 SK Chapter "Preface": "Company description" added.
J-Link picture changed.
15 060914 OO
Subchapter 1.5.1: Added target supply voltage and
target supply current to specifications.
Subchapter 5.2.1: Pictures of ways to connect J-
Trace.
14 060818 TQ Subchapter 4.7 "Using DCC for memory reads"
added.
13 060711 OO Subchapter 5.2.2: Corrected JTAG+Trace connec-
tor pinout table.
12 060628 OO Subchapter 4.1: Added ARM966E-S to List of sup-
ported ARM cores.
11 060607 SK Subchapter 5.5.2.2 changed.
Subchapter 5.5.2.3 added.
Revision Date By Explanation

4
J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
10 060526 SK
ARM9 download speed updated.
Subchapter 8.2.1: Screenshot "Start sequence"
updated.
Subchapter 8.2.2 "ID sequence" removed.
Chapter "Support" and "FAQ" merged.
Various improvements
9 060324 OO
Chapter "Literature and references" added.
Chapter "Hardware":
Added common information trace signals.
Added timing diagram for trace.
Chapter "Designing the target board for trace"
added.
8 060117 OO Chapter "Related Software": Added JLinkARM.dll.
Screenshots updated.
7 051208 OO Chapter Working with J-Link: Sketch added.
6 051118 OO
Chapter Working with J-Link: "Connecting multiple
J-Links to your PC" added.
Chapter Working with J-Link: "Multi core debug-
ging" added.
Chapter Background information: "J-Link firm-
ware" added.
5 051103 TQ Chapter Setup: "JTAG Speed" added.
4 051025 OO
Chapter Background information: "Flash program-
ming" added.
Chapter Setup: "Scan chain configuration" added.
Some smaller changes.
3 051021 TQ Performance values updated.
2 051011 TQ Chapter "Working with J-Link" added.
1 050818 TW Initial version.
Revision Date By Explanation

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
5
About this document
This document describes J-Link and J-Trace. It provides an overview over the major
features of J-Link and J-Trace, gives you some background information about JTAG,
ARM and Tracing in general and describes J-Link and J-Trace related software pack-
ages available from Segger. Finally, the chapter Support and FAQs on page 107 helps
to troubleshoot common problems.
For simplicity, we will refer to J-Link ARM as J-Link in this manual.
Typographic conventions
This manual uses the following typographic conventions:
Style Used for
Body Body text.
Keyword Text that you enter at the command-prompt or that appears on the
display (that is system functions, file- or pathnames).
Reference Reference to chapters, tables and figures or other documents.
GUIElement Buttons, dialog boxes, menu names, menu commands.
Table 1.1: Typographic conventions

6
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
EMBEDDED SOFTWARE
(Middleware)
emWin
Graphics software and GUI
emWin is designed to provide an effi-
cient, processor- and display control-
ler-independent graphical user
interface (GUI) for any application that
operates with a graphical display.
Starterkits, eval- and trial-versions are
available.
embOS
Real Time Operating System
embOS is an RTOS designed to offer
the benefits of a complete multitasking
system for hard real time applications
with minimal resources. The profiling
PC tool embOSView is included.
emFile
File system
emFile is an embedded file system with
FAT12, FAT16 and FAT32 support.
emFile has been optimized for mini-
mum memory consumption in RAM and
ROM while maintaining high speed.
Various Device drivers, e.g. for NAND
and NOR flashes, SD/MMC and Com-
pactFlash cards, are available.
emUSB
USB device stack
A USB stack designed to work on any
embedded system with a USB client
controller. Bulk communication and
most standard device classes are sup-
ported.
SEGGER TOOLS
Flasher
Flash programmer
Flash Programming tool primarily for microcon-
trollers.
J-Link
JTAG emulator for ARM cores
USB driven JTAG interface for ARM cores.
J-Trace
JTAG emulator with trace
USB driven JTAG interface for ARM cores with
Trace memory. supporting the ARM ETM (Embed-
ded Trace Macrocell).
J-Link / J-Trace Related Software
Add-on software to be used with SEGGER’s indus-
try standard JTAG emulator, this includes flash
programming software and flash breakpoints.
SEGGER Microcontroller GmbH & Co. KG develops
and distributes software development tools and ANSI
C software components (middleware) for embedded
systems in several industries such as telecom, medi-
cal technology, consumer electronics, automotive
industry and industrial automation.
SEGGER’s intention is to cut software development-
time for embedded applications by offering compact flexible and easy to use middleware,
allowing developers to concentrate on their application.
Our most popular products are emWin, a universal graphic software package for embed-
ded applications, and embOS, a small yet efficent real-time kernel. emWin, written
entirely in ANSI C, can easily be used on any CPU and most any display. It is comple-
mented by the available PC tools: Bitmap Converter, Font Converter, Simulator and
Viewer. embOS supports most 8/16/32-bit CPUs. Its small memory footprint makes it
suitable for single-chip applications.
Apart from its main focus on software tools, SEGGER developes and produces program-
ming tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in devel-
opment, debugging and production, which has rapidly become the industry standard for
debug access to ARM cores.
Corporate Office:
http://www.segger.com
United States Office:
http://www.segger-us.com

J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
7
1 Introduction....................................................................................................................11
1.1 J-Link overview .......................................................................................12
1.1.1 Features of J-Link .................................................................................... 12
1.2 J-Trace overview ..................................................................................... 13
1.2.1 Features of J-Trace .................................................................................. 13
1.2.2 Test environment .................................................................................... 14
1.3 Specifications..........................................................................................15
1.3.1 Specifications for J-Link ............................................................................ 15
1.3.2 Specifications for J-Trace .......................................................................... 15
1.3.3 Download speed ...................................................................................... 16
1.4 Requirements..........................................................................................17
2 Setup..............................................................................................................................19
2.1 Installing the J-Link ARM software and documen-tation pack .........................20
2.1.1 Setup procedure......................................................................................21
2.1.2 Verifying correct driver installation.............................................................24
2.2 Uninstalling the J-Link USB driver .............................................................. 26
2.3 Connecting the target system....................................................................27
2.3.1 Power-on sequence..................................................................................27
2.3.2 Verifying target device connection .............................................................27
2.3.3 Problems ................................................................................................ 27
2.4 Scan chain configuration...........................................................................28
2.4.1 Sample configuration dialog boxes .............................................................28
2.4.2 Determining values for scan chain configuration...........................................30
2.5 JTAG Speed ............................................................................................ 31
2.5.1 Fixed JTAG speed ....................................................................................31
2.5.2 Automatic JTAG speed..............................................................................31
2.5.3 Adaptive clocking.....................................................................................31
3 J-Link and J-Trace related software...............................................................................33
3.1 J-Link related software ............................................................................. 34
3.1.1 J-Link software and documentation package................................................34
3.1.2 List of additional software packages ........................................................... 34
3.2 J-Link software and documentation package in
detail .....................................................................................................35
3.2.1 J-Link Commander (Command line tool) .....................................................35
3.2.2 J-Link STR9 Commander (Command line tool) .............................................35
3.2.3 J-Link TCP/IP Server (Remote J-Link / J-Trace use)...................................... 36
3.2.4 J-Mem Memory Viewer .............................................................................36
3.2.5 J-Flash ARM (Program flash memory via JTAG) ............................................37
3.2.6 J-Link RDI (Remote Debug Interface) .........................................................38
3.2.7 J-Link GDB Server ...................................................................................40
3.3 Additional software packages in detail ........................................................41
3.3.1 JTAGLoad (Command line tool)..................................................................41
3.3.2 J-Link Software Developer Kit (SDK) ..........................................................41
3.3.3 J-Link Flash Software Developer Kit (SDK) ..................................................41
3.4 Using the J-LinkARM.dll ............................................................................42
3.4.1 What is the JLinkARM.dll? .........................................................................42
3.4.2 Updating the DLL in third-party programs ...................................................42
3.4.3 Determining the version of JLinkARM.dll ..................................................... 42
Table of Contents

8
J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
3.4.4 Determining which DLL is used by a program.............................................. 43
4 Working with J-Link and J-Trace....................................................................................45
4.1 Supported ARM Cores .............................................................................. 46
4.2 Reset strategies ...................................................................................... 47
4.2.1 Reset strategies in detail .......................................................................... 47
4.3 Cache handling ....................................................................................... 49
4.3.1 Cache coherency..................................................................................... 49
4.3.2 Cache clean area..................................................................................... 49
4.3.3 Cache handling of ARM7 cores .................................................................. 49
4.3.4 Cache handling of ARM9 cores .................................................................. 49
4.4 Connecting multiple J-Links / J-Traces to your PC ........................................ 50
4.4.1 How does it work? ................................................................................... 50
4.4.2 Configuring multiple J-Links / J-Traces ....................................................... 51
4.4.3 Connecting to a J-Link / J-Trace with non default USB-Address...................... 52
4.5 Multi-core debugging ............................................................................... 53
4.5.1 How multi-core debugging works............................................................... 53
4.5.2 Using multi-core debugging in detail .......................................................... 54
4.5.3 Things you should be aware of .................................................................. 56
4.6 Multiple devices in the scan chain.............................................................. 57
4.6.1 Configuration.......................................................................................... 57
4.7 Using DCC for memory access .................................................................. 58
4.7.1 What is required ? ................................................................................... 58
4.7.2 Target DCC handler ................................................................................. 58
4.7.3 Target DCC abort handler......................................................................... 58
4.7.4 Testing DCC memory access ..................................................................... 59
4.8 Command strings .................................................................................... 60
4.8.1 List of available commands....................................................................... 60
4.8.2 Using command strings............................................................................ 64
4.9 Switching off CPU clock during debug......................................................... 66
5 Device specifics.............................................................................................................67
5.1 Analog Devices ....................................................................................... 68
5.1.1 ADuC7xxx .............................................................................................. 68
5.2 ATMEL ................................................................................................... 69
5.2.1 AT91SAM7 ............................................................................................. 69
5.2.2 AT91SAM9 ............................................................................................. 69
5.3 NXP....................................................................................................... 70
5.3.1 LPC ....................................................................................................... 70
5.4 ST Microelectronics.................................................................................. 71
5.4.1 STR 71x................................................................................................. 71
5.4.2 STR 73x................................................................................................. 71
5.4.3 STR 75x................................................................................................. 71
5.4.4 STR91x.................................................................................................. 71
5.4.5 STM32 ................................................................................................... 71
5.5 Texas Instruments .................................................................................. 71
5.5.1 TMS470 ................................................................................................. 71
6 Hardware .......................................................................................................................73
6.1 JTAG Connector ...................................................................................... 74
6.1.1 Pinout.................................................................................................... 74
6.1.2 Target board design for JTAG.................................................................... 75
6.2 Using the JTAG connector with SWD .......................................................... 76
6.2.1 Pin Out .................................................................................................. 76
6.3 JTAG+Trace connector ............................................................................. 77
6.3.1 Connecting the target board ..................................................................... 77
6.3.2 Pinout.................................................................................................... 78
6.3.3 Assignment of trace information pins between ETM architecture versions ........ 79
6.3.4 Trace signals .......................................................................................... 79
6.4 RESET, nTRST ........................................................................................ 81

J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG
9
6.5 Adapters ................................................................................................82
6.5.1 JTAG 14 pin adapter ................................................................................82
6.5.2 5 Volt adapter .........................................................................................83
6.6 How to determine the hardware version......................................................84
6.6.1 Differences between different versions .......................................................85
6.7 J-Link OEM versions ................................................................................. 87
6.7.1 List of OEM products ................................................................................87
7 Background information.................................................................................................89
7.1 JTAG......................................................................................................90
7.1.1 Test access port (TAP)..............................................................................90
7.1.2 Data registers .........................................................................................90
7.1.3 Instruction register ..................................................................................90
7.1.4 The TAP controller ................................................................................... 91
7.2 The ARM core.......................................................................................... 93
7.2.1 Processor modes .....................................................................................93
7.2.2 Registers of the CPU core .........................................................................93
7.2.3 ARM / Thumb instruction set .....................................................................94
7.3 EmbeddedICE ......................................................................................... 95
7.3.1 Breakpoints and watchpoints.....................................................................95
7.3.2 The ICE registers.....................................................................................96
7.4 Embedded Trace Macrocell (ETM)...............................................................97
7.5 Embedded Trace Buffer (ETB) ...................................................................98
7.6 Flash programming ..................................................................................99
7.6.1 How does flash programming via J-Link / J-Trace work ?...............................99
7.6.2 Data download to RAM ............................................................................. 99
7.6.3 Data download via DCC ............................................................................99
7.6.4 Available options for flash programming ..................................................... 99
7.7 J-Link / J-Trace firmware ........................................................................ 101
7.7.1 Firmware update ................................................................................... 101
7.7.2 Invalidating the firmware........................................................................ 101
8 Designing the target board for trace ............................................................................103
8.1 Overview of high-speed board design ....................................................... 104
8.1.1 Avoiding stubs ...................................................................................... 104
8.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)............................... 104
8.1.3 Minimizing Crosstalk .............................................................................. 104
8.1.4 Using impedance matching and termination .............................................. 104
8.2 Terminating the trace signal.................................................................... 105
8.2.1 Rules for series terminators .................................................................... 105
8.3 Signal requirements ............................................................................... 106
9 Support and FAQs.......................................................................................................107
9.1 Troubleshooting .................................................................................... 108
9.1.1 General procedure ................................................................................. 108
9.1.2 Typical problem scenarios....................................................................... 108
9.2 Signal analysis ...................................................................................... 110
9.2.1 Start sequence ...................................................................................... 110
9.2.2 Troubleshooting .................................................................................... 110
9.3 Contacting support ................................................................................ 111
9.4 Frequently Asked Questions .................................................................... 112
10 Glossary.....................................................................................................................113
11 Literature and references...........................................................................................119

10
J-Link / J-Trace User Guide © 2004 - 2007 SEGGER Microcontroller GmbH & Co. KG

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
11
Chapter 1
Introduction
This chapter gives a short overview about J-Link and J-Trace.

12 CHAPTER 1 Introduction
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
1.1 J-Link overview
J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC run-
ning Microsoft Windows 2000, Windows XP, Windows 2003 or Windows Vista. J-Link
has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin
connector defined by ARM.
1.1.1 Features of J-Link
• USB 2.0 interface
• Any ARM7/ARM9 core supported, including thumb mode
• Automatic core recognition
• Maximum JTAG speed 12 MHz
• Download speed up to 720 Kbytes/second *
• DCC speed up to 800 Kbytes/second *
• Seamless integration into the IAR Embedded Workbench® IDE
• No power supply required, powered through USB
• Auto speed recognition
• Support for adaptive clocking
• All JTAG signals can be monitored, target voltage can be measured
• Support for multiple devices
• Fully plug and play compatible
• A Standard 20-pin JTAG connector
• Optional 14-pin JTAG adapter available
• Wide target voltage range: 1.2V - 3.3V
• Optional adapter for 5V targets available
• An USB and 20-pin ribbon cable included
• Memory viewer (J-Mem) included
• A TCP/IP server included, which allows using J-Link via TCP/IP networks
• A RDI DLL available, which allows using J-Link with RDI compliant software
• Flash programming software (J-Flash) available
• A Flash DLL available, which allows using flash functionality in custom applica-
tions
• A Software Developer Kit (SDK) available
• Embedded Trace Buffer (ETB) support
* = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed.

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
13
1.2 J-Trace overview
J-Trace is a JTAG emulator designed for ARM cores which includes trace (ETM) sup-
port. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Win-
dows 2003 or Windows Vista. J-Trace has a built-in 20-pin JTAG connector and a built
in 38-pin JTAG+Trace connector, which is compatible with the standard 20-pin con-
nector and 38-pin connector defined by ARM.
1.2.1 Features of J-Trace
• USB 2.0 interface
• Any ARM7/ARM9 core supported, including thumb mode
• Automatic core recognition
• Maximum JTAG speed 12 MHz
• Download speed up to 420 Kbytes/second *
• DCC speed up to 600 Kbytes/second *
• Seamless integration into the IAR Embedded Workbench® IDE
• No power supply required, powered through USB
• Auto speed recognition
• Support for adaptive clocking
• All JTAG signals can be monitored, target voltage can be measured
• Support for multiple devices
• Fully plug and play compatible
• Standard 20-pin JTAG connector, standard 38-pin JTAG+Trace connector
• An Optional 14-pin JTAG adapter available
• Wide target voltage range: 3.0V - 3.6V
• An Optional adapter for 5V targets available
• An USB and 20-pin ribbon cable included
• Memory viewer (J-Mem) included
• A TCP/IP server included, which allows using J-Trace via TCP/IP networks
• Flash programming software (J-Flash) available
• A Flash DLL available, which allows using flash functionality in custom applica-
tions
• A Software Developer Kit (SDK) available
• Full integration with the IAR C-SPY® debugger; advanced debugging features
available from IAR C-SPY debugger.
* = Measured with J-Trace, ARM7 @ 50 MHz, 12MHz JTAG speed.

14 CHAPTER 1 Introduction
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
1.2.2 Test environment
JLink.exe has been used for measurement performance. The hardware consisted of:
• PC with 2.6 GHz Pentium 4, running Win2K
• USB 2.0 port
• USB 2.0 hub
•J-Link
• Target with ARM7 running at 50MHz.
Below is a screenshot of JLink.exe after the measurement has been performed.

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
15
1.3 Specifications
1.3.1 Specifications for J-Link
1.3.2 Specifications for J-Trace
Power Supply USB powered <50mA
USB Interface USB 2.0, full speed
Target Interface JTAG 20-pin (14-pin adapter available)
Serial Transfer Rate between J-Link and Tar-
get up to 12 MHz
Supported Target Voltage 1.2 - 3.3 V (5V adapter available)
Target supply voltage 4.5V .. 5V (if powered with 5V on USB)
Target supply current Max. 300mA
Operating Temperature +5°C ... +60°C
Storage Temperature -20°C ... +65 °C
Relative Humidity (non-condensing) <90% rH
Size (without cables) 100mm x 53mm x 27mm
Weight (without cables) 70g
Electromagnetic Compatibility (EMC) EN 55022, EN 55024
Supported OS
Microsoft Windows 2000
Microsoft Windows XP
Microsoft Windows XP x64
Microsoft Windows 2003
Microsoft Windows 2003 x64
Microsoft Windows Vista
Microsoft Windows Vista x64
Table 1.1: J-Link specifications
Power Supply USB powered < 300mA
USB Interface USB 2.0, full speed
Target Interface JTAG 20-pin (14-pin adapter available)
JTAG+Trace: Mictor, 38-pin
Serial Transfer Rate between J-Trace and
Ta r g e t up to 12 MHz
Supported Target Voltage 3.0 - 3.6 V (5V adapter available)
Operating Temperature +5°C ... +40°C
Storage Temperature -20°C ... +65 °C
Relative Humidity (non-condensing) <90% rH
Size (without cables) 123mm x 68mm x 30mm
Weight (without cables) 120g
Electromagnetic Compatibility (EMC) EN 55022, EN 55024
Supported OS
Microsoft Windows 2000
Microsoft Windows XP
Microsoft Windows XP x64
Microsoft Windows 2003
Microsoft Windows 2003 x64
Microsoft Windows Vista
Microsoft Windows Vista x64
Table 1.2: J-Trace specifications

16 CHAPTER 1 Introduction
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
1.3.3 Download speed
The following table lists performance values (Kbytes/s) for writing to memory (RAM):
Note: The actual speed depends on various factors, such as JTAG, clock speed,
host CPU core etc.
Hardware Memory download
via DCC
ARM7
Memory download
ARM9
Memory download
J-Link Rev. 1 — 4 185.0 Kbytes/s
(4MHz JTAG)
150.0 Kbytes/s
(4MHz JTAG)
75.0 Kbytes/s
(4MHz JTAG)
J-Link Rev. 5 800.0 Kbytes/s
(12MHz JTAG)
720.0 Kbytes/s
(12MHz JTAG)
550.0 Kbytes/s
(12MHz JTAG)
J-Trace Rev.1 600.0 Kbytes/s
(12MHz JTAG)
420.0 Kbytes/s
(12MHz JTAG)
280.0 Kbytes/s
(12MHz JTAG)
Table 1.3: Download speed differences between hardware revisions

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
17
1.4 Requirements
Host System
To use J-Link or J-Trace you need a host system running Windows 2000, Windows XP,
Windows 2003, or Windows Vista.
Target System
An ARM7 or ARM9 target system is required. The system should have a standardized
20-pin connector as defined by ARM Ltd. for a simple JTAG connection. The individual
pins are described in section JTAG Connector on page 74. Note that Segger offers an
optional adapter to use J-Link and J-Trace with targets using 14 pin 0.1" mating JTAG
connectors.
To use tracing with J-Trace, you need a 38-pin connector on your target board as
defined by ARM Ltd. and described under JTAG+Trace connector on page 77. The
individual pins are described in section Pinout on page 78.

18 CHAPTER 1 Introduction
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG

J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
19
Chapter 2
Setup
This chapter describes the setup procedure required in order to work with J-Link / J-
Trace. Primarily this includes the installation of the J-Link software and documenta-
tion package, which also includes a kernel mode J-Link USB driver in your host sys-
tem.

20 CHAPTER 2 Setup
J-Link / J-Trace User Guide © 1997 - 2007 SEGGER Microcontroller GmbH & Co. KG
2.1 Installing the J-Link ARM software and documen-
tation pack
J-Link is shipped with a bundle of applications, corresponding manuals and some
sample projects and the kernel mode J-Link USB driver. Some of the applications
require an additional license, free trial licenses are avaliable upon request from
www.segger.com.
Refer to chapter J-Link and J-Trace related software on page 33 for an overview
about the J-Link software and documentation pack.