Sensoray 526 User manual

1
PC/104 Multifunction I/O Board
Hardware Manual
Model 526 | Rev B | February 2009

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Table of Contents
TABLE OF CONTENTS......................................................................................................... 2
LIMITED WARRANTY.......................................................................................................... 4
SPECIAL HANDLING INSTRUCTIONS .................................................................................... 4
INTRODUCTION................................................................................................................. 5
PROGRAMMABLE COUNTERS............................................................................................... 7
Input S gnals................................................................................................................. 7
Captured Events............................................................................................................ 8
Output S gnals .............................................................................................................. 8
Counter Preload ............................................................................................................ 8
Output Reg ster............................................................................................................. 9
Examples of Counter Appl cat ons.................................................................................... 9
One-shot (software tr gger).......................................................................................... 9
One-shot (hardware tr gger)....................................................................................... 10
Pulse W dth Modulat on.............................................................................................. 10
INTERRUPT TIMER........................................................................................................... 11
WATCHDOG TIMER .......................................................................................................... 11
Watchdog enable/d sable ............................................................................................. 12
Sol d-sate relay control................................................................................................. 12
D/A CONVERTER.............................................................................................................. 13
Cal brat on .................................................................................................................. 13
A/D CONVERTER.............................................................................................................. 13
Cal brat on .................................................................................................................. 13
DIGITAL I/O.................................................................................................................... 15
INTERRUPTS ................................................................................................................... 15
CALIBRATION EEPROM..................................................................................................... 16
CONFIGURATION JUMPERS............................................................................................... 17
CONNECTORS.................................................................................................................. 17
Analog connector (J3) .................................................................................................. 17
D g tal connector (J5)................................................................................................... 18
REGISTERS ..................................................................................................................... 19
Reg ster Map............................................................................................................... 19
T mer Control Reg ster ................................................................................................ 20
Watchdog T mer Control Reg ster .................................................................................. 20
DAC Control Reg ster ................................................................................................... 21
ADC Control Reg ster ................................................................................................... 22
DAC/ADC Data Reg ster................................................................................................ 22
D g tal I/O Control Reg ster........................................................................................... 23
Interrupt Enable Reg ster ............................................................................................. 24
Interrupt Status Reg ster .............................................................................................. 24
M scellaneous Reg ster ................................................................................................. 25
Counter Preload/Data Reg ster low word ........................................................................ 25
Counter Preload/Data Reg ster h gh word....................................................................... 25

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Counter Mode Reg ster................................................................................................. 26
Counter Control/Status Reg ster .................................................................................... 27
EEPROM Data Reg ster................................................................................................. 28
EEPROM Command/Status Reg ster ............................................................................... 28
SPECIFICATIONS ............................................................................................................. 29

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Limited warranty
Sensoray Company, Incorporated (Sensoray) warrants the hardware to be free from defects n
mater al and workmansh p and perform to appl cable publ shed Sensoray spec f cat ons for two
years from the date of sh pment to purchaser. Sensoray w ll, at ts opt on, repa r or replace
equ pment that proves to be defect ve dur ng the warranty per od. Th s warranty ncludes parts
and labor.
The warranty prov ded here n does not cover equ pment subjected to abuse, m suse, acc dent,
alterat on, neglect, or unauthor zed repa r or nstallat on. Sensoray shall have the r ght of f nal
determ nat on as to the ex stence and cause of defect.
As for tems repa red or replaced under warranty, the warranty shall cont nue n effect for the
rema nder of the or g nal warranty per od, or for n nety days follow ng date of sh pment by
Sensoray of the repa red or replaced part, wh chever per od s longer.
A Return Mater al Author zat on (RMA) number must be obta ned from the factory and clearly
marked on the outs de of the package before any equ pment w ll be accepted for warranty work.
Sensoray w ll pay the sh pp ng costs of return ng to the owner parts that are covered by
warranty. A restock ng charge of 25% of the product purchase pr ce, or $105, wh chever s less,
w ll be charged for return ng a product to stock.
Sensoray bel eves that the nformat on n th s manual s accurate. The document has been
carefully rev ewed for techn cal accuracy. In the event that techn cal or typograph cal errors ex st,
Sensoray reserves the r ght to make changes to subsequent ed t ons of th s document w thout
pr or not ce to holders of th s ed t on. The reader should consult Sensoray f errors are suspected.
In no event shall Sensoray be l able for any damages ar s ng out of or related to th s document or
the nformat on conta ned n t.
EXCEPT AS SPECIFIED HEREIN, SENSORAY MAKES NO WARRANTIES, EXPRESS
OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S
RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE
PART OF SENSORAY SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID
BY THE CUSTOMER. SENSORAY WILL NOT BE LIABLE FOR DAMAGES
RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR
INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE
POSSIBILITY THEREOF.
Th rd party brands, names and trademarks are the property of the r respect ve owners.
Special handling instructions
The c rcu t board conta ns CMOS c rcu try that s sens t ve to Electrostat c D scharge (ESD).
Spec al care should be taken n handl ng, transport ng, and nstall ng c rcu t board to prevent ESD
damage to the board. In part cular:
•Do not remove the c rcu t board from ts protect ve ant -stat c bag unt l you are ready to
nstall the board nto the enclosure.
•Handle the c rcu t board only at grounded, ESD protected stat ons.
•Remove power from the equ pment before nstall ng or remov ng the c rcu t board.

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Introduction
Model 526 s a PC/104 mult funct onal I/O board w th the follow ng features:
•Four 24-b t programmable counters. Inputs could be dr ven from ncremental encoders ( n
1x, 2x, or 4x modes) or any d g tal s gnal. Inputs accept d fferent al (RS-422) or standard
TTL/CMOS s ngle-ended s gnals. The counters can also count nternal clock (27 or 13.5 MHz).
•E ght d g tal I/O channels conf gurable as nputs or outputs ( n groups of 4) and capable of
generat ng nterrupts.
•4-channel 16-b t D/A converter (±10 V).
•8-channel (mult plexed) d fferent al 16-b t A/D converter (±10 V).
•Programmable nterrupt t mer.
•Watchdog t mer w th conf gurable t meout and output.
•EEPROM for cal brat on data storage.
•Flex ble address and nterrupt l ne conf gurat on.
•Requ res one power supply (+5V).
Model 526 s controlled through a set of 27 reg sters mapped nto I/O space. The base address of
the board s selected w th jumpers from a range of 0x0000 to 0xFFC0. The board s sh pped w th
the base address set to 0x2C0. All reg ster accesses are 16 b t; 1 byte and odd address accesses
are not supported. The total I/O space cla med by the board s 0x40 (64) bytes.
Model 526 can generate nterrupts on var ous programmable cond t ons. The nterrupt l ne used
by the board s selected w th jumpers from the follow ng IRQ values: 3, 4, 5, 6, 7, 9, 10, 11, 12,
14 and 15. The board s sh pped w th the nterrupt set to IRQ3.

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F g.1. Model 526 board outl ne.

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Programmable Counters
Model 526 conta ns 4 dent cal 24-b t up/down counters w th enable and preload. The block
d agram of one of the counters s shown on F g.2.
"1"
ECAP
SOFTWARE LOAD
PRELOAD BUFFER 0
UP/DOWN
POWER-ON RESET
CLKB
INTERNAL
INDEX
INDEX
.
.
.
"1"
CLK
D Q
DATA BUS
CLKA
SOFTWARE RESET
RTGL
"1"
ICAP-
ENABLE
CLK
D Q
CLK
D Q
Q
COUNTER CORE
LOAD
ROLLOVER
LATCH
RTGL
INDEX^
ROLLOVER
CE
CLOCK
RCAP
CLK
D Q
INDEXv
COUT
CLOCK MUX/
QUADRATURE
DETECTOR
PRELOAD BUFFER 1
RESET
INTERNAL/2
CLK
D Q
"1"
ICAP+
ERROR
DATA BUS
F g.2. Counter s mpl f ed block d agram.
See the descr pt on of Counter Mode reg ster and Counter Control/Status reg ster n the
Registers sect on for the mplementat on spec f cs.
Input Signals
The counter accepts the follow ng nput s gnals (connector J5):
•CLKA – phase A of the encoder, or any clock s gnal n normal mode;
•CLKB – phase B of the encoder;
•INDEX – ndex s gnal of the encoder, or any d g tal s gnal;
•CE – external count enable.
S gnals CLKA, CLKB and INDEX could be e ther d fferent al (RS-422), or s ngle-ended. In case of a
s ngle-ended s gnal the “+” nput has to be used.
The clock source can be selected through the software. In quadrature mode the poss ble clock
sources are:
•quadrature x1 (CLKA↑ count ng up, CLKA↓ count ng down);

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•quadrature x2 (both edges of CLKA);
•quadrature x4 (both edges of both CLKA and CLKB);
In normal mode the clock sources are:
•CLKA↑;
•CLKA↓;
•Internal clock (27 MHz);
•Internal clock d v ded by 2 (13.5 MHz).
Count d rect on (up or down) s set through the software (normal mode) or determ ned from
CLKA-CLKB phase relat onsh p (quadrature mode).
Count s enabled e ther through the software, or w th the external s gnal. Poss ble sources of
Count Enable s gnal are:
•CEN;
•INDEX;
•INDEX↑ to INDEX↓ (count does not start unt l the r s ng edge of INDEX s gnal);
•NOT RCAP (see the descr pt on of RCAP s gnal below).
The polar ty of Count Enable s gnal can be nverted through the software.
Captured Events
The counter detects or generates the follow ng “short” events:
•RO – rollover, counter overflow (when count ng up) or underflow (when count ng down);
•INDEX↑ - r s ng edge of INDEX s gnal;
•INDEX↓ - fall ng edge of INDEX s gnal;
•ERROR – llegal quadrature state trans t on.
“Short” events can generate nterrupts, f enabled.
To fac l tate rel able detect on by the software, the “short” events are captured (see F g.2), thus
generat ng correspond ng captured events:
•RCAP – captured RO s gnal;
•ICAP+ - captured r s ng edge of INDEX s gnal;
•ICAP- - captured fall ng edge of INDEX s gnal;
•ECAP – captured ERROR s gnal.
Captured events status can be read and reset through the Control/Status Reg ster.
Add t onally, RO generates RTGL – a s gnal wh ch toggles each t me rollover s generated.
Output Signals
The follow ng s gnals can be routed to the counter output s gnal (COUT):
•RCAP;
•RTGL.
The polar ty of COUT s gnal can be nverted through the software.
Counter Preload
Each counter has 2 preload reg sters access ble nd v dually through the software, PR0 and PR1.
The counter s loaded from a preload reg ster under software control (from PR0), or
automat cally. The preload reg ster from wh ch the counter s loaded n automat c mode s

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determ ned by the state of the RTGL s gnal: PR0 when RTGL s low, PR1 when RTGL s h gh. The
autoload occurs under a programmable comb nat on of the follow ng cond t ons:
•INDEX↑ - r s ng edge of INDEX s gnal;
•INDEX↓ - fall ng edge of INDEX s gnal;
•RO – rollover.
See appl cat on examples below for the explanat on of preload reg sters usage.
The preload reg sters are 24 b ts long, so they can not be wr tten to w th one operat on. In order
to prevent the s tuat on when the counter s loaded w th ncomplete data, an ntermed ate buffer
holds the h gh word of a preload reg ster unt l the data s wr tten to the low word, so that both
h gh and low words are wr tten to the preload reg ster s multaneously. Thus the h gh word has to
be always wr tten f rst.
Output Register
Counter output data (24-b t) requ res 2 read accesses to be read out. To ensure that all b ts of
the read ng correspond to the same nstant each counter has an output reg ster. The data can be
latched nto the output reg ster e ther by a read access to the low word of Counter Data reg ster,
or by a hardware event, depend ng on the state of “Output reg ster latch control” b t of the
Counter Mode reg ster. The hardware event that can latch the counter data s a log cal OR of any
of the follow ng: INDEX r s ng edge, INDEX fall ng edge, nterrupt t mer exp rat on.
Latch ng the data nto the output reg ster does not nterrupt the count. Latch ng on read access
occurs on the access to the low word, so n case “Latch on read” mode s selected the low word
has to be always read f rst.
Examples of Counter Applications
All the follow ng examples assume the use of counter 0. The pseudocode funct on
Reg sterWr te(address, data) has a mean ng of wr t ng a 2-byte word data to I/O address
( base+address ), where base s the base I/O address of the board.
One-shot (software trigger
In th s mode the counter clock source s set to nternal, so the length of the generated pulse
s expressed n un ts of 1/27 MHz ≈ 37 ns. Assum ng the des red pos t ve go ng pulse length s
3 ms the counter has to be loaded w th the value of 3 ms x 27 MHz = 81,000 = 0x13C68.
The Count Enable s set to NOT RCAP, the counter output (COUT) to RCAP w th COUT polar ty
nverted.
Step 1. Load the preload reg ster PR0 w th 0x13C68. F rst, set the Counter Mode reg ster.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0
X PR0 X Soft
count
d rect on
control
Count
d rect on:
down
Clock
source:
nternal
Count
enable:
hardware
NOT
RCAP
Auto load:
d sable
Polar ty:
nverted
Out:
RCAP
// select PR0 as a target for Preload register access
// set operating mode, don’t enable count yet
RegisterWrite (0x16, 0x1D62); //load Counter Mode register

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RegisterWrite (0x14, 0x0001); //load Preload Register high word
RegisterWrite (0x12, 0x3C68); //load Preload Register low word
Step 2. Reset the counter (to clear RTGL), load the counter from Preload Reg ster 0.
RegisterWrite (0x18, 0x8000); //reset the counter
RegisterWrite (0x18, 0x4000); //load the counter from PR0
Step 3. Reset RCAP (f res one-shot).
RegisterWrite (0x18, 0x8);
One-shot (hardware trigger
The follow ng example shows how to f re the one-shot on the pos t ve edge of external
tr gger. The tr gger s gnal s connected to the INDEX nput of the counter.
Step 1. Load both preload reg sters PR0 and PR1 w th 0x13C68. F rst, set the Counter Mode
reg ster.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0
X PR0 X Soft
count
d rect on
control
Count
d rect on:
down
Clock
source:
nternal
Count
enable:
hardware
NOT
RCAP
Auto load and
reset RCAP:
INDEX↑
Polar ty:
nverted
Out:
RCAP
// select PR0 as a target for Preload register access
// do not enable autoload (bit 4) yet
RegisterWrite (0x16, 0x1D62); //load Counter Mode register
RegisterWrite (0x14, 0x0001); //load Preload Register 0 high word
RegisterWrite (0x12, 0x3C68); //load Preload Register 0 low word
// select PR1 as a target for Preload register access
RegisterWrite (0x16, 0x5D62); //load Counter Mode register
RegisterWrite (0x14, 0x0001); //load Preload Register 1 high word
RegisterWrite (0x12, 0x3C68); //load Preload Register 1 low word
Step 2.
// enable autoload
RegisterWrite (0x16, 0x3D72); //load Counter Mode register
Pulse Width Modulation
Let’s assume the follow ng requ rements:
Per od = 10 ms; “h gh” state = 2 ms; “low” state = 8 ms. Then the “h gh” length n per ods of
the 27 MHz clock s 2 ms x 27 MHz = 54000 = 0xD2F0, the “low” length s 8 ms x 27 MHz =
216000 = 0x34BC0.
Step 1. Load Preload Reg ster 0.
// select PR0 as a target for Preload register access, load PR0
RegisterWrite (0x16, 0x1C85); //load Counter Mode register
RegisterWrite (0x14, 0x0003); //load Preload Register 0 high word
RegisterWrite (0x12, 0x4BC0); //load Preload Register 0 low word
Step 2. Load Preload Reg ster 1.
// select PR1 as a target for Preload register access, load PR1
RegisterWrite (0x16, 0x5C85); //load Counter Mode register
RegisterWrite (0x14, 0x0000); //load Preload Register 0 high word
RegisterWrite (0x12, 0xD2F0); //load Preload Register 0 low word

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To change the duty cycle steps 1-2 have to be repeated w th the new preload reg ster values.
Interrupt Timer
The nterrupt t mer prov des a way of generat ng nterrupts at prec se t me ntervals n the range
between approx mately 100 µs and 25.5 ms. The t mer s an 8-b t down counter w th a preload
count ng a 99.852 µs clock. Two operat on modes are ava lable: manual restart and autorestart.
In the manual restart mode the count starts on a software command and stops when the zero
count s reached. In autorestart mode the counter automat cally reloads and restarts after the
zero count s reached.
B t [0] of the Interrupt Status Reg ster s set when the t mer exp res, and an nterrupt s
generated f b t [0] of the Interrupt Enable Reg ster s set to 1.
Interrupt t mer exp rat on event can latch the output data of the counter(s), f th s opt on s
enabled n Counter Control/Status Reg ster(s).
Watchdog Timer
The watchdog t mer has a t meout value programmable n 8 steps between 0.125 s and 16 s. If
enabled, the watchdog t mer t mes out after a selected t me nterval f t s not “tagged”. Read ng
the watchdog t mer reg ster “tags” t (restarts the count).
The watchdog t mer generates a s gnal that controls a set of 2 sol d-state relays (one normally
open, one normally closed) (F g.3). Insert ng a shunt n pos t on 1-2 of jumper J6 selects a
normally open relay, nsert ng t n pos t on 2-3 selects a normally closed relay.
WDT0
CONTROL
POLARITY
1
2
3
J6
WDT1
.
.
.
F g.3. Watchdog t mer output c rcu t.
For add t onal flex b l ty the operat ng mode of the watchdog t mer s controlled by 2 b ts of the
Watchdog T mer Control reg ster and 2 jumpers.

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Watchdog enable/disable
Watchdog enable/d sable s controlled by b t [3] of the Watchdog T mer Control reg ster and
jumper 1 of J4.
Shunt n pos t on 1 of J4 B t [3] of Control Reg ster Watchdog t mer
Not nstalled 0 D sabled
Not nstalled 1 Enabled
Installed 0 Enabled
Installed 1 D sabled
B t [3] s always 0 after power up, so f the watchdog t mer has to be enabled by default, the
shunt has to be nstalled.
Solid-sate relay control
The polar ty of the watchdog t mer output s gnal (CONTROL on F g.3) s controlled by b t [4] of
the Watchdog T mer Control reg ster and jumper 2 of J4. When CONTROL s not act ve, each
sol d-state relay s n ts default (normal) state. When CONTROL becomes act ve, the sol d-state
relays change the r states.
Sol d-state relay control Shunt n pos t on 2 of J4 B t [4] of Control
Reg ster
T med out Not t med out
Not nstalled 0 Act ve Not act ve
Not nstalled 1 Not act ve Act ve
Installed 0 Not act ve Act ve
Installed 1 Act ve Not act ve

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D/A Con erter
Model 526 mplements a 4-channel 16-b t D/A converter. Each channel has an nd v dual preload
buffer. Preload buffers are accessed through a s ngle wr te reg ster (DAC/ADC Data reg ster) and
selected w th 2 b ts of the DAC Control reg ster. Upload to the DAC s performed for all 4
channels from the r correspond ng preload buffers w th a s ngle software command and takes
approx mately 8 µs to complete. A b t n the Interrupt Status reg ster s set when the upload s
complete, and an nterrupt s generated, f enabled n the Interrupt Enable reg ster. See the
descr pt on of DAC Control reg ster n the Registers sect on for the mplementat on spec f cs.
The DAC range s sl ghtly w der than ±10 V wh ch allows for software cal brat on. The code value
of 0 corresponds to the most negat ve output voltage, the code value of 0xFFFF corresponds to
the most pos t ve output voltage.
Calibration
The D/A converter s cal brated at the factory. For each of the 4 channels 2 coeff c ents are
stored n the on-board EEPROM: a and b , such that the d g tal code that has to be loaded to the
DAC n order to obta n output voltage V s equal to
bVaC
+
⋅
=
, where V s n volts. The
constants are stored n the double float ng po nt format (8 bytes per value). See the
Calibration EEPROM sect on for the deta ls.
A/D Con erter
Model 526 mplements an 8-channel mult plexed d fferent al 16-b t A/D converter. The nput
s gnal range s sl ghtly w der than ±10 V wh ch allows for software cal brat on. Mult ple channels
can be d g t zed w th one software command. B ts [14:5] of the ADC Control reg ster allow
select on of any comb nat on of 8 nput channels and 2 reference channels (0 V and +10V). Each
of 10 d g t zed channels has ts own buffer reg ster. The buffer reg sters are accessed through a
s ngle read reg ster (DAC/ADC Data reg ster) and selected w th 4 b ts of the ADC Control reg ster.
A b t n the Interrupt Status reg ster s set when the convers on s complete, and an nterrupt s
generated, f enabled n the Interrupt Enable reg ster. See the descr pt on of ADC Control reg ster
n the Registers sect on for the mplementat on spec f cs.
As long as the ADC nputs are mult plexed, a mult plexor settl ng delay of approx mately 15 µs s
prov ded automat cally before each measurement. A b t n the ADC Control reg ster allows turn ng
th s delay off, wh ch ncreases sampl ng rate n case of the repet t ve measurements from a s ngle
channel.
The output code of the ADC s b nary two’s complement; the most pos t ve nput voltage
produces a code of 0x7FFF, the most negat ve nput voltage produces a code of 0x8000 .
Calibration
The A/D converter s cal brated at the factory. One cal brat on constant s stored n the on-board
EEPROM: the actual value of the on-board 10V reference. In order to obta n accurate read ng of
the nput s gnal a normal zat on procedure has to be performed f rst: values of the on-board
+10V reference and 0V reference have to be measured. (Those values and the nput values could
be measured us ng a s ngle command. See the descr pt on of the A/D Control reg ster for the
deta ls). The actual value of the measured voltage s then obta ned as

14








−
−
⋅=
0
0
CC CC
VV
ref
meas
refmeas
,
where
ref
V - the actual value of the on-board 10V reference (from the EEPROM);
meas
C - ADC read ng correspond ng to the measured voltage;
ref
C - ADC read ng correspond ng to the on-board +10V reference;
0
C
- ADC read ng correspond ng to the on-board 0V reference.
The cal brat on constant s stored n the double float ng po nt format (8 bytes per value). See
the Calibration EEPROM sect on for the deta ls.

15
Digital I/O
D g tal I/O on model 526 cons sts of 8 s gnals, wh ch can be conf gured as nputs or outputs n
groups of 4: DIO group 1 (DIO0-3) and DIO group 2 (DIO4-7). Interrupts can be generated on
r s ng or fall ng edges of DIO s gnals. Interrupt cond t on (r s ng or fall ng edge) can be selected
nd v dually for every s gnal n group 1, and for group 2 as a whole. See D g tal I/O Control
reg ster descr pt on n the Registers sect on for the deta ls.
Interrupts
Interrupts are controlled w th 2 reg sters: Interrupt Enable reg ster (IER) and Interrupt Status
reg ster (ISR). ISR stores the status of var ous events, IER enables or d sables the ab l ty of those
events to generate an nterrupt (F g.4).
.
..
ISR15
.
..
IER0
IER1
.
..
IER2
IER14
ISR1
.
..
ISR2
IER15
IER13
ISR13
IRQ
.
.
.
.
.
.
.
.
..
..........
ISR0
ISR14
.
..
F g.4. S mpl f ed d agram of the nterrupt controller.
When a spec f c nterrupt cond t on s met, a correspond ng b t s set n the ISR. If an nterrupt was
enabled for th s source by sett ng a correspond ng b t of the IER to 1, the s gnal on the board’s
nterrupt p n (selected w th jumpers) goes h gh, generat ng an ISA nterrupt. An nterrupt handler
(software) must mmed ately d sable the nterrupts by wr t ng a value of 0x0000 to the IER, wh ch
results n the s gnal on the board’s nterrupt p n go ng low. Next an nterrupt handler detects the
source of the nterrupt by analyz ng the ISR, and resets the correspond ng b ts. (Note that the ISR
b ts correspond ng to the counters’ nterrupt status are reset by resett ng the correspond ng b ts n
the Counter Control/Status reg sters). When the nterrupt process ng s over, the nterrupt handler
must restore the value of the IER. If a b t of the ISR has been set to 1 wh le the nterrupt handler
was process ng prev ous nterrupt(s), the IRQ s gnal w ll go h gh aga n mmed ately after the IER s
restored, so no nterrupts are lost.

16
Calibration EEPROM
An on-board EEPROM s prov ded for cal brat on data storage. Data from the EEPROM s read by
us ng a set of 2 reg sters: EEPROM Command/Status reg ster and EEPROM data reg ster. The
EEPROM s organ zed as 64 2-byte words, w th addresses from 0x00 to 0x3F. The address map of
the EEPROM s as follow ng:
Address Contents
0x00 DAC channel 0 parameter a (b ts [15:0])
0x01 DAC channel 0 parameter a (b ts [31:16])
0x02 DAC channel 0 parameter a (b ts [47:32])
0x03 DAC channel 0 parameter a (b ts [63:48])
0x04 DAC channel 0 parameter b (b ts [15:0])
0x05 DAC channel 0 parameter b (b ts [31:16])
0x06 DAC channel 0 parameter b (b ts [47:32])
0x07 DAC channel 0 parameter b (b ts [63:48])
0x08 DAC channel 1 parameter a (b ts [15:0])
0x09 DAC channel 1 parameter a (b ts [31:16])
0x0A DAC channel 1 parameter a (b ts [47:32])
0x0B DAC channel 1 parameter a (b ts [63:48])
0x0C DAC channel 1 parameter b (b ts [15:0])
0x0D DAC channel 1 parameter b (b ts [31:16])
0x0E DAC channel 1 parameter b (b ts [47:32])
0x0F DAC channel 1 parameter b (b ts [63:48])
0x10 DAC channel 2 parameter a (b ts [15:0])
0x11 DAC channel 2 parameter a (b ts [31:16])
0x12 DAC channel 2 parameter a (b ts [47:32])
0x13 DAC channel 2 parameter a (b ts [63:48])
0x14 DAC channel 2 parameter b (b ts [15:0])
0x15 DAC channel 2 parameter b (b ts [31:16])
0x16 DAC channel 2 parameter b (b ts [47:32])
0x17 DAC channel 2 parameter b (b ts [63:48])
0x18 DAC channel 3 parameter a (b ts [15:0])
0x19 DAC channel 3 parameter a (b ts [31:16])
0x1A DAC channel 3 parameter a (b ts [47:32])
0x1B DAC channel 3 parameter a (b ts [63:48])
0x1C DAC channel 3 parameter b (b ts [15:0])
0x1D DAC channel 3 parameter b (b ts [31:16])
0x1E DAC channel 3 parameter b (b ts [47:32])
0x1F DAC channel 3 parameter b (b ts [63:48])
0x20 ADC reference value (b ts [15:0])
0x21 ADC reference value (b ts [31:16])
0x22 ADC reference value (b ts [47:32])
0x23 ADC reference value (b ts [63:48])
See A/D and D/A Converter sect ons for the deta ls of the cal brat on procedures.

17
Configuration Jumpers
A set of conf gurat on jumpers (J1) allows select on of board’s base address and nterrupt l ne
(See F g.1).
Jumpers marked ADDR15-6 select the h gher 10 b ts of the board’s base address n I/O space.
Inserted jumper sets the correspond ng b t to 0. The board sh ps w th base address set to 0x2C0.
Jumpers marked IRQ3-0 select the nterrupt l ne used by the board. Inserted jumper means a
correspond ng b t n the 4-d g t b nary representat on of the nterrupt number s set to 0. For
example, nsert ng jumpers 2 and 0 sets the nterrupt l ne used by the board to IRQ10. The board
can use the follow ng nterrupt l nes: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 and 15. All other
comb nat ons are not allowed. The board sh ps w th the nterrupt set to IRQ3.
Jumpers J4 and J6 are used to conf gure the watchdog t mer. See the correspond ng sect on for
the deta ls.
Connectors
Analog connector (J3
Pin Signal Pin Signal
1 Ground 2 Ground
3 Analog nput 0 (-) 4 Analog nput 0 (+)
5 Analog nput 1 (-) 6 Analog nput 1 (+)
7 Analog nput 2 (-) 8 Analog nput 2 (+)
9 Analog nput 3 (-) 10 Analog nput 3 (+)
11 Analog nput 4 (-) 12 Analog nput 4 (+)
13 Analog nput 5 (-) 14 Analog nput 5 (+)
15 Analog nput 6 (-) 16 Analog nput 6 (+)
17 Analog nput 7 (-) 18 Analog nput 7 (+)
19 Ground 20 Ground
21 Ground 22 Ground
23 Analog output 0 24 Feedback 0
25 Return 0 (Ground) 26 Ground
27 Analog output 1 28 Feedback 1
29 Return 1 (Ground) 30 Ground
31 Analog output 2 32 Feedback 2
33 Return 2 (Ground) 34 Ground
35 Analog output 3 36 Feedback 3
37 Return 3 (Ground) 38 Ground
39 Ground 40 Ground
Notes:
1. P ns Return 0-3 are connected to ground on the board.
2. If the feedback for an analog output s prov ded through a Feedback p n of J3, the
correspond ng shunt on jumper J2 has to be removed. Otherw se the shunt has to be
nstalled, and the feedback s taken d rectly from the output of the DAC.

18
Digital connector (J5
Pin Signal Pin Signal
1 Clock A 0 - 2 Clock A 0 +
3 Clock B 0 - 4 Clock B 0 +
5 Index 0 - 6 Index 0 +
7 Count Enable 0 8 Counter Output 0
9 Encoder 0 power (+5V) 10 Ground
11 Clock A 1 - 12 Clock A 1 +
13 Clock B 1 - 14 Clock B 1 +
15 Index 1 - 16 Index 1 +
17 Count Enable 1 18 Counter Output 1
19 Encoder 1 power (+5V) 20 Ground
21 Clock A 2 - 22 Clock A 2 +
23 Clock B 2 - 24 Clock B 2 +
25 Index 2 - 26 Index 2 +
27 Count Enable 2 28 Counter Output 2
29 Encoder 2 power (+5V) 30 Ground
31 Clock A 3 - 32 Clock A 3 +
33 Clock B 3 - 34 Clock B 3 +
35 Index 3 - 36 Index 3 +
37 Count Enable 3 38 Counter Output 3
39 Encoder 3 power (+5V) 40 Ground
41 DIO0 42 DIO1
43 DIO2 44 DIO3
45 DIO4 46 DIO5
47 DIO6 48 DIO7
49 WDT relay 0 50 WDT relay 1
Notes:
1. Clock A, Clock B and Index are d fferent al nputs for the encoders. For s ngle-ended s gnals
the “+” nput has to be used, the “-“ nput has to be left unconnected.
2. Encoder power s prov ded from a +5V source protected by a s ngle resettable fuse rated at
1.1 A.

19
Registers
Register Map
Reg ster addresses are relat ve to the base address selected w th address jumpers (ADDR 15 –
6). All reg ster accesses are 2-byte. S ngle byte and odd address accesses are not supported.
Address
Write Read
0x00 TCR T mer control reg ster
0x02 WDC Watchdog t mer control reg ster
0x04 DAC DAC control
0x06 ADC ADC control
0x08 ADD DAC data ADC data
0x0A DIO D g tal I/O control D g tal I/O data
0x0C IER Interrupt enable reg ster
0x0E ISR Interrupt status reg ster Interrupt status reg ster
0x10 MSC M scellaneous reg ster M scellaneous reg ster
0x12 C0L Counter 0 preload reg ster low word Counter 0 data low word
0x14 C0H Counter 0 preload reg ster h gh word Counter 0 data h gh word
0x16 C0M Counter 0 mode reg ster
0x18 C0C Counter 0 control reg ster Counter 0 status reg ster
0x1A C1L Counter 1 preload reg ster low word Counter 1 data low word
0x1C C1H Counter 1 preload reg ster h gh word Counter 1 data h gh word
0x1E C1M Counter 1 mode reg ster
0x20 C1C Counter 1 control reg ster Counter 1 status reg ster
0x22 C2L Counter 2 preload reg ster low word Counter 2 data low word
0x24 C2H Counter 2 preload reg ster h gh word Counter 2 data h gh word
0x26 C2M Counter 2 mode reg ster
0x28 C2C Counter 2 control reg ster Counter 2 status reg ster
0x2A C3L Counter 3 preload reg ster low word Counter 3 data low word
0x2C C3H Counter 3 preload reg ster h gh word Counter 3 data h gh word
0x2E C3M Counter 3 mode reg ster
0x30 C3C Counter 3 control reg ster Counter 3 status reg ster
0x32 EED EEPROM data EEPROM data
0x34 EEC EEPROM nterface command S gnature
The follow ng s gnal types and default values are used to spec fy reg sters mplementat on:
RW read/wr te;
WO wr te only (data read may not be the same as data wr tten);
RR read/reset (wr t ng a 1 resets the correspond ng b t to 0, wr t ng a 0 has no effect);
RO read only;
UU unused.
0 the value after a hardware reset s 0;
1the value after a hardware reset s 1;
X “don’t care” for wr te, undef ned for read.

20
Timer Control Register
0x00
Bits Type Default Description
[15:8] WO 0x00 T mer preload data n 100 us t cks.
[7:2] UU XXXXXX Reserved
[1] WO 0 T mer mode:
0 – manual restart;
1 – auto restart.
[0] WO 0 Manual restart. Wr t ng a 1 restarts the t mer f [1] s 0. B t [0]
of the Interrupt Status reg ster s set to 1 when t mer exp res.
Watchdog Timer Control Register
0x02
Bits Type Default Description
[15:5] UU X Reserved.
[4] WO 0 Sol d-state relay control s gnal polar ty: 0 – normal (act ve
when t med out), 1 – nverted (act ve when not t med out).
(See Note 2).
[3] WO 0 Watchdog t mer software enable: wr t ng a 1 enables, wr t ng a
0 d sables the watchdog t mer (see Note 3).
[2:0] WO 000 T meout nterval:
000 – 16 sec;
001 – 8 sec;
010 – 4 sec;
011 – 2 sec;
100 – 1 sec;
101 – 0.5 sec;
110 – 0.25 sec;
111 – 0.125 sec.
Notes:
1. Read ng the Watchdog T mer Control reg ster “tags” the watchdog (restarts the count). The
data returned by read access s undef ned.
2. The mean ng of b t [4] corresponds to the case when a shunt n pos t on 2 of jumper J4 s
NOT nstalled. If the shunt s nstalled, the mean ng of b t [4] s reversed: 0 corresponds to
normal, and 1 – to nverted polar ty of the sol d-state relay control s gnal.
3. The mean ng of b t [3] corresponds to the case when a shunt n pos t on 1 of jumper J4 s
NOT nstalled. If the shunt s nstalled, the mean ng of b t [3] s reversed: 0 enables, and 1
d sables the watchdog t mer. Thus nstall ng the shunt enables the watchdog t mer by default
after the power up.