Shiratech Solutions AT-501 Quick setup guide

AT-501
Cortex-A5
System on Module
Integration guide
Revision 1.4

2 | AT-501 HW user manual 1.4
Contents
1 Scope..................................................................................................................................................... 4
1.1 SoM introduction ............................................................................................................................. 4
1.2 SoM models ..................................................................................................................................... 4
2 AT-501 Integration guide ...................................................................................................................... 6
2.1 Power connectivity .......................................................................................................................... 6
2.2 Reset ................................................................................................................................................ 8
2.3 Interfaces ......................................................................................................................................... 9
2.3.1 Ethernet ports ......................................................................................................................... 9
2.3.2 UART and USART ................................................................................................................... 10
2.3.3 USB ........................................................................................................................................ 12
2.3.4 High Speed Multi-Card Interface........................................................................................... 14
2.3.5 LCD and touch screen support .............................................................................................. 14
2.3.6 CAN........................................................................................................................................16
2.3.7 I2C.......................................................................................................................................... 16
2.3.8 SPI.......................................................................................................................................... 16
2.3.9 A to D Convertor ................................................................................................................... 16
2.3.10 JTAG .................................................................................................................................. 17
2.4 Mechanical considerations ............................................................................................................17
2.4.1 SO-DIMM connector .............................................................................................................19
2.5 Pin assignment............................................................................................................................... 19
2.5.1 SO-DIMM 200 Pins assignment............................................................................................. 19
2.5.2 Port A options........................................................................................................................ 26
2.5.3 Port B options........................................................................................................................ 27
2.5.4 Port C options........................................................................................................................ 28
2.5.5 Port D options .......................................................................................................................29
2.5.6 Port E options........................................................................................................................ 30
3 AT-501 System overview..................................................................................................................... 31
3.1 Cortex-A5 Processor ......................................................................................................................31
3.2 Memories.......................................................................................................................................31

3 | AT-501 HW user manual 1.4
Document Revision History
Revision
Date
Description
1.0
12.6.2013
Initial version
1.1
8.5.2014
Add D36, update USART capabilities.
1.2
1.6.2014
Add notes about OTG support; add details
about components height on the print side.
1.3
6.4.2015
Fix debug port pin out
1.4
26.8.2015
Add remarks about VBAT and Resistive touch
interfaces

4 | AT-501 HW user manual 1.4
1Scope
The purpose of this document is to provide a guide for integrating the AT-501 into the target hardware
in an easy and fast way so that the use of SoM will shorten and simplify the development process.
The guide is divided to two parts, the first one help you through the integration process, giving design
samples based on the design of the CB-20(schematics can be provided by Shiratech via
[e-mail] ) while the second part provide more details on the AT-501 system.
In order to simplify the integration process we recommend the following process:
1. Read through the integration guide on the required interfaces.
2. Use Shiratech’s Pin configuration tool to define the solution
3. Use the CB-20 as a reference design to shorten the development process.
For more details if needed review the SAMA5D3 user manual and access Shiratech at
[e-mail]
1.1 SoM introduction
The AT-501 is an industrial embedded System-On-Module (SoM) based on Atmel’s new SAMA5D3
Cortex-A5 system on chip. It offers the optimal balance of the most power efficient Cortex A processor
available to date with a high performance CPU running at 536 MHz and a floating point unit.
The AT-501 includes the processor and its entire environment, as well a 1Gbe physical layer chip. All the
interfaces of the processor are available for the user through a well-known 200 pins SO-DIMM form
factor.
1.2 SoM models
The SOM support the various variations of the SAMA5D3 –different assembly options. In case the SOM
uses the SAMA5D31 the 1Gbe physical interface is not assembled.
See the table below for the supported interface in each variation:

5 | AT-501 HW user manual 1.4
Figure 1 –Interface support on the various SAMA5D3 processors

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2AT-501 Integration guide
The HW integration guide covers all the hardware issues related to the connecting the SoM to the target
device starting from power connectivity, connector details, pin-out options, description of the various
interfaces and provides reference design for most of the interfaces. By using the same design as the
reference board you can shorten the BSP development phase and reduce the option for mistakes. The
reference design is based on the CB-20. Schematics of the CB-20 can be provided by request. For more
details contact [e-mail]
2.1 Power connectivity
The AT-501 uses a single power input of 3.3V from which all the other required voltages are taken. The
3.3V input is only directly used for power the processor I/Os. The Inlet power should be
Rise time: <= 3ms
Input voltage range: 3.3V +/- 5%
Typical power consumption: 0.5W
Figure 2 –AT-501 internal power scheme
The AT-501 support low power modes, it can enter sleep mode by shutting down the main power source
leaving only a very small part active for possible wake up interrupt either internal or external.
For supporting these modes several additional lines are available:
VBAT –battery input for maintaining the RTC unit and Shutdown Controller within the processor. If not
used should be connected to 3.3V.
S
O
-
D
I
M
M
3.3 -> 1.8
3.3 -> 1.2
I/O
DDR
Core
PLL
3.3 V (2-3A)
1.8 -> 1.2
LDO
GE
Battery
Optional
VBAT
Ferrit
3.3 -> 2.5
LDO
FUSE

7 | AT-501 HW user manual 1.4
Important:
VBAT must be high during power up for the processor to start working, so in case VBAT is connected to a
dedicated rechargeable battery or super cap, there must be a mechanism to provide the required
voltage during power up otherwise the processor will not start.
The AT-501 has an optional backup power source for the Real-Time-Clock. It can support an
approximately 1 hour of the RTC operation when the main power fails. The following figure describes
the AT-501 backup power. The backup power device, CBC3105, monitors the main power level and
when it drops below a configurable threshold it switch to its internal power source. During normal
operation the backup chip is recharge to its nominal power. In the basic ordering option the backup chip
is bypassed by a 0 ohm resistor. In this way an external power source can be connected to VBAT e.g.
high energy battery, to support longer backup time. For more details on that option contact
[email protected]m .
WKUP (Input –pin 10 in the SO-DIMM connector) –The Wake Up line is used to wake up the system
using an external trigger, if unused should be left open. An internal pull up is assembled on the SOM.
Level 0 on the WKUP pin triggers the processor to wake up.
SHDN (Output - pin 12 in the SO-DIMM connector) –This pin enable the SW to shut down the power
after entering the SW and processor to sleep mode. A typical application connects the pin SHDN to the
shutdown input of the DC/DC Converter providing the main power supplies of the system.
Level 1 (3.3V) = Enable, Level 0 (0V) = Shutdown.
Note: If this pin is used along with a battery connected to the VBAT signal then the signal should be
pulled up to VBAT and not to regular 3.3V. In that way the signal remain valid even when the main
power is down.
PWR_ENB (Input –pin 30 in the SO-DIMM connector) this pin can be used to shut down the DC2DC chip
on the SOM. Asserting this line during shut down will reduce the system power dissipation
Level 1 (3.3V)= Enable, Level 0 (0V) = disable)
ADVREF - this pin is used for the reference voltage of the A/D pins if not used should be connected to
3.3V.

8 | AT-501 HW user manual 1.4
Figure 3 –AT-501 Backup Power scheme
2.2 Reset
The NRESET signal is an open-drain interface. It generates a reset on POR or on a reset event generated
by the SW. It also can be used as an input to an external reset source like a push-button.
The generated reset signal can be used to reset the system chips. The following figure describes the AT-
501 Reset signal.
Figure 4 - Reset Generation
Atmel
SAMA5D
3.3 -> 1.8
3.3 -> 1.2
I/O
DDR
Core
CBC
3105 VBAT
SO-DIMM 200
3.3V
Shutdown WakeUp
VBAT
Inlet
PLLFilter
SAMA5D
S
O
-
D
I
M
MNRESET
3.3 V
Push-Button
NRESET

9 | AT-501 HW user manual 1.4
2.3 Interfaces
The AT-501 offers a large variety of interfaces over the 200 pins SO-DIMM connector. The following
paragraphs describe the available interfaces along with guidance on how to connect and to use them.
For more information, review the SAMA5D3 data sheet.
2.3.1 Ethernet ports
The AT-501 support 1 Giga Ethernet port and one fast Ethernet port depending on the type of processor
assembled.
Figure 5 - Giga Ethernet & Fast Ethernet Interfaces
2.3.1.1 Giga Ethernet port
The AT-501 includes a build in 1GE interface (including physical layer chip) in all it models except the one
which includes the SAMA5D31 which does not support GE.
The Physical layer chip is connected via MDC/MDIO interface using the default PHY address is 0001 for
both interfaces.
The Giga Ethernet uses an RGMII interface to interconnect to the processor. The figure 5 describes the
Giga Ethernet interface. On the carrier board only the magnetics and connector should be placed. The
Giga Ethernet signals pairs should be routed from the PHY to the magnetic as differential pairs using 100
ohm impedance.
For the GE port the following signals are used as well:
Interrupt - PB-25 of the SAMA5 uses as an interrupt input for the Giga Ethernet PHY.
LEDs - Two led signals from the GE PHY are also connected to the SOM edge connector.
LED1 –Blinking Activity.
LED2- Link, on when there is link.
SAM-A5
Micrel
ksz9031
Ethernet 0
RGMII
4 x TX
4 x RX
Controls
125 Mhz
25M
Int.
SO-DIMM 200
NReset
LEDS RJ45
MAG
LEDS
GE Analog
FE
PHY
RMII 2 x TX
2 x RX
50 MHz
25M
MODULE A
RMII Analog
Control
Ethernet 1

10 | AT-501 HW user manual 1.4
The led are connected to the GE PHY through a 470 ohm serial resistor.
Note: In case of the SAMA5D31, the pins used for GE should be left unconnected.
Figure 6 - Giga Ethernet schematics
2.3.1.2 Ethernet port
The Fast Ethernet interface is available for the D36, D35 and SAMA5D31 only. For the fast Ethernet port
there is no internal physical layer chip so it should be placed on the carrier board. The processor can be
connected to the physical layer using the RMII interface of the processor. The RMII runs on 50 MHz clock
that need to be provided to the processor by an external source.
The RMII signals should be connected directly to the CPU i.e. no serial resistors. Routing these signals to
the FE PHY should be done according to the RMII standard for proper operation.
2.3.1.3 MDC/MDIO
The Giga Ethernet MDC/MDIO signals are NOT available on the edge connector since the physical layer
chip is built in. The Fast Ethernet MDC/MDIO signals are available, MDIO (PC9) on pin 174, MDC (PC8) on
pin 175.
The MDC frequency is derived from the system clock and should not exceed 2.5MHz.
2.3.2 UART and USART
There are up to four USART and two UART interfaces dependent on PIO utilization and processor type.
The following paragraph describes the various options.

11 | AT-501 HW user manual 1.4
2.3.2.1 USARTs
The USART interface includes 5 signals RxD, TxD, CTS, RTS and SCK if synchronous operation is required.
Since the USART are multiplexed with other functions there are some limitations on the use of USART:
USART
Problem
Possible solution
USART 0
SD0 card detect is on
the same pin as TXD,
SD1 CD is on the RXD
This signals can be connected to other
GPIO and require a SW change,
alternatively, the SD can work without
that signal, can be detected via SDIO
bus
Multiplexed with CAN 0, SPI0 CS 1-3
USART 1
SCK uses the same pin
as the 1G interrupt pin
If GE is not assembled (D31), then all
pins are available otherwise require a
HW change on the SOM
USART 2
1 wire devices uses the
same pin as RXD
Can be ordered without the 1 wire –
special ordering item
USART 3
SCK not available
If required –connect Shiratech for
possible solutions
The USART main features are:
Programmable Baud Rate Generator
5-bit to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
o1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
oParity Generation and Error Detection
oBy-8 or by-16 Over-sampling Receiver Frequency
oOptional Hardware Handshaking RTS-CTS
RS485 with Driver Control Signal
IrDA Modulation and Demodulation
Note: the USART can be used as SPI interface if required.

12 | AT-501 HW user manual 1.4
Figure 7 –UART –RS232 interface schematics
2.3.2.2 UART
The UART are available only on the D31, D35 and D36 only. If one of these chips is used then the UART
can be used under the following constrains:
UART 0 - Available only if the ISI interface is not used.
UART 1 –Available only if I2C0 is not used and if the ISI interface is not used.
The UART main features are:
Two-pin UART
Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Interrupt Generation
2.3.2.3 Debug Interface
The processor has an additional dedicated UART port for debug and control connected to the internal
debug controller (PB 30 and 31, Pins 117 and 118 in the SO-DIMM connector).
2.3.3 USB
The SAMA5D3 support 3 USB ports:
Port-A support USB 2.0 Host/Device OTG interface.
oThis port can be programmed as Host or Device.
oIt can also be programmed as an OTG interface.
oBy monitoring the VUSB signal it can determine if it is connected to a Host or a device.
Note: For automatic detecting of the external device connected it is recommended to use the ID pin of
the USB interface and to connect it to a GPIO of the processor.
oThis port should be used for connecting by the Atmel SAM-BA tool.

13 | AT-501 HW user manual 1.4
Port-B supports USB 2.0 Host interface.
Port-C supports USB 2.0 Host interface.
The SAMA5D3 integrates the USB PHY so there is no need for external devices. To be compatible with
the AT-501 SW the following I/O need to be connected when using the USB interfaces:
•PD25 enable power for port A (pin 83).
•PD26 enable power for port B (pin 84)
•PD27 enable power for port C (pin 85).
•PD28 over current sense from all ports (pin 187).
•PD29 VUSB sense - power sense for port A (pin 186).
The USB ports can be extended to support additional USB ports, using an external USB hub. See figure
for an example of the USB connectivity used in the CB-20
Figure 8 –USB implantation example from the CB-20
Type
A/B
Type
A
Current
Limiter
0.5A
SO-DIMM 200
USB A
USB B
5V USB
5V/0.5A
5V/0.5A
EN_A
EN_B
Over Current
VUSB Sense
USB
HUB
MODULE A MODULE B
Type
A
Current
Limiter
0.5A
EN
USB C
5V USB
5V/0.5A

14 | AT-501 HW user manual 1.4
2.3.4 High Speed Multi-Card Interface
The SAMA5D supports up to 3 HSMCI interfaces. All three interfaces are available on the edge
connector. The availability of the interfaces is dependent on the I/O configuration.
The HSMCI main features are:
MCI0 support up to 8 data bits (Only 4 bits are available on the edge connector).
MCI1 and MCI2 support up to 4 data bits.
Supports MMC, eMMC and SD cards.
Up to 50 MHZ clock.
Note –The Micro-SD card can be used as a booting memory. It has the highest priority on all other
nonvolatile memories.
The MCI interfaces can be used under the following constrains:
MCI 0 –Available, used for a bootable SD card.
oWhen used PD17(pin 80 on the connector) is used as card detect
MCI 1 - Available, cannot be used as a bootable SD source.
oWhen used PD18(pin 79 on the connector) is used as card detect
MCI 2 –Available if the RGB interface (24 bits mode) is not used.
Note: These pins are the ones currently supported by the CB-20 software, but they are not hardcoded
and any other GPIO can be used for these functions.
The following schematics show an implementation of a 4-bits Micro SD card. It is connected to the
SAMA5D3 MCI0 through the edge connector. The Micro-SD powered by a 3.3V power supply.
Figure 1 –Micro SD card implementation on the CB-20
2.3.5 LCD and touch screen support
The SAMA5D3 support an internal LCD controller with build in support for resistive touch screen.

15 | AT-501 HW user manual 1.4
2.3.5.1 LCD support
The SAMA5D3 has a build in LCD controller which can be connected directly to an external LCD using
RGB. The LCD has one display input buffer per overlay that fetches pixels through the dual AHB master
interface and a lookup table to allow palletized display configurations. The LCD controller is
programmable on a per overlay basis, and supports different LCD resolutions, window sizes, image
formats and pixel depths.
The LCD can be connected using either 16 bits RGB interface or 24 bits RGB interface.
In case 16 bits RGB
oLCD data (15:0) is available on PA(15-0)
oLCD control on PA(29-24).
For 24 bits RGB
oUse PC(15-10) and PE (28-27) for SW computability
In the CB-20 the LCD in connected via LVDS interface using an RGB to LVDS converter. Schematics are
available via [e-mail]
2.3.5.2 Resistive Touch screen
The SAMA5D3 has an ADC controller, which includes a Resistive Touchscreen Controller. It supports 4-
wire and 5-wire technologies with the following support:
Position and Pressure Measurement for 4-wire screens
Position Measurement for 5-wire screens
Average of up to 8 measures for noise filtering
The touch interface is using AD(0-4) which are available over pins 181-185 in the SO-DIMM connector.
See below touch screen connectivity sample for the CB-20
Figure 10 –Touch screen connectivity example
Note: if these pins are not used, they are set to inputs with internal pull up.

16 | AT-501 HW user manual 1.4
2.3.6 CAN
The AT-501 supports up to two CAN interfaces depending on the processor type (available only on the
D34 and D35). The CAN interfaces are available under the following constrains:
CAN 0 - If USART 0 CTS, SCK are used or if SPI0-CS(1-2) then CAN 0 cannot be used.
CAN 1 - no limitations.
2.3.7 I2C
There are up to three I2C interfaces available on the SAMA5D3. All three interfaces are available on the
edge connector. The availability of the I2C interfaces is dependent on the I/O configuration. The I2C
interface requires pull ups on both lines, the pull ups should be placed on the carrier board.
The I2C main features are:
One, Two or Three Bytes for Slave Address
Sequential Read-write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbits
General Call Supported in Slave mode
MBUS Quick Command Supported in Master Mode
Connection to DMA Controller (DMA) Channel Capabilities Optimizes Data Transfers
The I2C ports are available under the following conditions:
I2C 0 –Available only when UART 1 is not used and the ISI interface is not used.
I2C 1 - Available only if SPI 1 CS 1 and 2 are not used.
I2C 2 –Available only if the ISI interface is not used.
2.3.8 SPI
There are up to two SPI interfaces dependent on PIO utilization. Both interfaces are available on the SO-
DIMM 200 connector.
The SPI main features are:
Programmable as Master or Slave.
Up to 25 MHz clock.
Up to 4 chips select signal that can be configure as discreet or as a 4 bits logical combination.
It is recommended to put a serial resistor on the clock signal close the SO-DIMM connector. No need to
put pull-up resistors on the data signals.
2.3.9 A to D Convertor
The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. It also
integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog
lines. The conversions extend from 0V to the voltage carried on pin ADVREF (up to 3.3V).
The ADC converter supports the following features:
o12-bit Resolution

17 | AT-501 HW user manual 1.4
o1 MHz Conversion Rate
oWide Range Power Supply Operation
oSelectable Single Ended or Differential Input Voltage
oProgrammable Gain For Maximum Full Scale Input Range 0 –VDD
oIntegrated Multiplexer Offering Up to 12 Independent Analog Inputs
oIndividual Enable and Disable of Each Channel
oHardware or Software Trigger
oExternal Trigger Pin
ADVREF (Pin 190) is the Reference voltage input for the ADC function
2.3.10 JTAG
The AT-501 has a JTAG interface that can be used either for JTAG testing or for connecting an ICE. The
selection between the two modes is done using setting JTAGSEL pin 8 in the SO-DIMM connector to the
right mode.
The JTAG connector is a 20 pins connector enables JTAG card testing or ICE emulation(you should use
the same pin-out for supporting J-link emulator).
JTAGSEL is used for selecting the right mode, for normal mode or ICE –open, ‘1’ for JTAG test
Figure 11 –JTAG emulator interface
2.4 Mechanical considerations
The AT-501 SoM is 47.5x67.6mm module. It is connected to the carrier board using a SO-DIMM
connector and it has two holes for additional mechanical support (see dimensions below).

18 | AT-501 HW user manual 1.4
Figure 12 –AT-501 CS view
-The height of devices in the PS is up to 1mm with the exception of U22 which is 1.4mm.
Figure 13 –AT-501 PS view
-The supporting holes diameter is 3mm.
U22

19 | AT-501 HW user manual 1.4
2.4.1 SO-DIMM connector
The AT-501 uses an SO-DIMM interface for connecting the SOM. The carrier board should use a 1.8V
DDR2 SO-DIMM connector. The connector comes in different heights according the need.
In the CB-20 the SO-DIMM connector is 1473005-4 from TE connectivity. Any other compatible
connector can be used.
2.5 Pin assignment
The SO-DIMM connector offers 200 pins which are used for:
Power
GPIOs which can be used either as GPIOs or as various interfaces
Fixed interfaces like GE and USB
RFU - un used pins reserved for future use.
The following table shows the pin assignment of the connector. The following tables will show the
options for each GPIO. The SAMA5D3 processor offers 5 banks of GPIOs each contain 32 bits, PA, PB,
PC, PD and PE. The following tables will show the options for each bank. Note that not all options are
possible.
Note: Shiratech offers a pin configuration tool (available at Shiratech web site) which offers an easy
way to configure the pin assignment of the module according to the functions need. The tool also
provide additional information on the pin out and multiplexing options.
2.5.1 SO-DIMM 200 Pins assignment
-Gray power and ground lines.
-Red dedicated I/Os
-Green un used pins should be left open
-Blue GPIOs
Pin
Card
pinout
Dedicated
Functionality
Type
Description
1
3.3V
Power
2
3.3V
Power
3
3.3V
Power
4
3.3V
Power
5
GND
Ground
6
VBAT
Power
Should be connected to external
battery or to 3.3 power source if
battery is not used
7
USB-C DP
USB-C
8
JTAGSEL
JTAG
input
JTAG Selection, select between
JTAG and ICE. When open normal
mode or J-link emulator. '0' for JTAG

20 | AT-501 HW user manual 1.4
test
9
USB-C DN
USB-C
10
WKUP
power control
Input
The wake-up input (WKUP0)
connect to any push-buttons or
signal that wake up the processor.(if
using VBAT then is should be
connected to VBAT and not to
regular VCC)
11
GND
Ground
12
SHDN
power control
Output
Used for shut down the system
external peripherals , internal pull up
on the SOM(This signal use VBAT,
do not connect to regular VCC)
13
USB-B DP
USB-B
14
RFU
Not used
15
USB-B DN
USB-B
16
NRST
Reset
Reset pin, can be used for reset the
processor or as a reset signal to the
carrier board
17
GND
Ground
18
NTRST
JTAG
Input
JTAG Test Reset Signal
19
DIBP
Soft modem
Soft Modem Signal
20
TDI
JTAG
JTAG - Test Data In
21
DIBN
Soft modem
Soft Modem Signal
22
TCK
JTAG
Input
JTAG Test clock Signal
23
GND
Ground
24
TMS
JTAG
Input
JTAG test mode select
25
USB-A DP
USB-A
26
TDO
JTAG
Output
JTAG Test Data Out
27
USB-A DN
USB-A
28
RTCK
JTAG
Output
JTAG Returned Test Clock
29
GND
Ground
30
PWR_EN
power control
input
Enable the DC2DC on the SOM
card, Integrated pull up on the SoM if
not required leave open
31
RFU
Not used
32
RFU
Not used
33
RFU
Not used
34
RFU
Not used
35
PE16
GPIO
36
PE17
GPIO
37
PE18
GPIO
38
PE19
GPIO
39
PE20
GPIO