Sinclair Research ZX Spectrum User manual

SERVICINGMANUAL
FOR
ZXSPECTRUM®
•LISTOFCONTENTS
INTRODUCTION
SECTION1 SYSTEMDESCRIPTION
SECTION2 DISASSEMBLY/ASSEMBLY
SECTION3 SETTINGUPANDSYSTEMTEST
SECTION4 FAULTDIAGNOSISANDREPAIR
SECTION5 PARTSLISTS
iLISTOFILLUSTRATIONSi
FigNo.
ZXSpectrumBlockDiagram1.1
ExpansionRAMRAS/CASTiming(ReadCycleshown)1.2
KeyboardMatrixInterconnections1.3
ZXSpectrum(Issue2)CircuitDiagram1.4
ZXSpectrum(Issue3)CircuitDiagram1.5
KeyboardFormat4.1
SpeakerLoadInputWaveforms4.2
ExpansionMemory1CLocations4.3
Issue3 Linksvs1CManufacturerandType4.4
PrintedCircuitBoard(Issue2)ComponentLayout5.1
PrintedCircuitBoard(Issue3)ComponentLayout5.2
PrintedCircuitBoard(Issue3B)ComponentLayout5.3
Prepared by THORN (EMI) DATATECH LTD
forSINCLAIRRESEARCHLTDMARCH1984
©SinclairResearchLtd.
(i)

-INTRODUCTION
This manual isforuseby authorised SINCLAIR
dealers,engineersandrepresentativesasa guide
to rectifying faults onthe SINCLAIR ZX SPECTRUM
personalcomputer.
ThemanualrefersprincipallytotheIssue2 and
Issue3 Spectrumsbutprovidesa backgroundtothe
Issue1 versioninthesectiondealingwith
modificationhistory.
Basic knowledge ofZX SPECTRUM operating
proceduresisassumedasisknowledgeofcurrent
workshoppracticerelatingtomicrocomputers.
NOTE: Essentialmodifications are required
onsomeIssue2 Spectrums.Referto
ModificationHistory(Section4)and
implementasnecessary.

-SAFETYMEASURES•
Thisinstructionmanualcontainscertain
—WARNING— andCAUTION-
noticeswhichMUSTbe-followedbytheuserto
ensureSAFEoperationandtoretainthe
equipmentina SAFEcondition.
Anyadjustment,maintenanceandrepairofthe
openedapparatusundervoltageshallbe
carriedcutonlybya skilledpersonwhois
AWAREOFTHEHAZARDINVOLVED.

SECTION1
SYSTEMDESCRIPTION
Sub-SectionLISTOFCONTENTSPageNo.
1Introduction1.1
2Architecture1.1
3Z80ACPU1.2
4MemoryOrganisation1.4
Read/WriteOperations1.4
5Input/Output1.6
TVPictureGeneration1.6
KeyboardScanning1.8
TapeInterface1.10
6PowerSupplies1.11
CircuitDiagrams
ZXSpectrum,Issue2 Fig.1.4
ZXSpectrum,Issue3 Fig.1.5
1.INTRODUCTION
1.1A blockdiagramofthecompleteZXSPECTRUMmicro-computerisgivenin
Figure1.1.Itisvalidforallbuildstandards,fittedwitheither
16kor48kbytesofdynamicRAMmemory.Althoughfunctionally
identical,detailedcircuitchangeshavebeenintroducedtoimprove
reliabilityandtoassistwithmanufacture.Theprintedcircuitboard
layouthasalsobeenmodified.Detailsofthesechangesare
highlightedwherenecessaryinthefollowingparagraphs,andinlater
sectionsreferringtofaultdiagnosisandrepair.
2.ARCHITECTURE
2.1The architecture ofthe Spectrum shown in Figure 1.1is typical of
many microcomputersystems in that it comprises a single
microprocessorboard (in this instance a Z80A oru 780 CPU), a read
only memory (ROM), an expandable RAM memory andan input/output
sectionhandlingthekeyboard,tapeandTVdisplayfunctions.The
latterisrecognisableasthelogicgatearray(ULA)andthethree
functionalblocks shown inthe right ofthe diagram.
2.2The computer is built ona single printed circuit boardwhich also
includesa regulatedpowersupplyfedfromanexternal9Vpowerpack.
Thekeyboardmatrixispartoftheuppercaseassemblyandis
connectedtotheboardviatworibboncablesKB1andKB2.A
descriptionofeachsectionfollows.
1.1

3.Z80ACPU
3.1The Z80A isan 8-bit single-IC central processing unit (CPU). Itis
clocked at 14.0 MHz from an externalsourcecontrolled bythe logic
gatearray(ULA)andhasa standardthreebusinput/output
arrangement.ThesebusesaretheDataBus,AddressBusandControl
Busrespectively.
3.2 Data Bus. D7-D10 constitutes an 8-bit bi-directional data bus with
active high, tri-state input/outputs. Itis used for data exchanges
withthememoryandwiththeULA.
3.3 Address Bus. A15-AO constitutes a 16-bit address bus with active
high,tri-stateoutputs.Theaddressbusprovidestheaddressfor
memory(upto64kbytes)dataexchangesandfordataexchangeswith
theULA.Itisalsousedduringtheinterruptroutine(seebelow)
whenscanningthekeyboardmatrix.
3.4ControlBus.Thecontrolbusisa collectionofindividualsignals
whichgenerallyorganisetheflowofdataontheaddressanddata
buses.Theblockdiagramonlyshowsfiveofthesesignalsalthough
othersofminorimportancearemadeavailableattheexpansionport
(seeFigures1.4and1.5fordetails).
3.5 Starting with memory reguest fMREQ), this signal is active low
indicating when the address bus holds a valid address fora memory
read or memory writeoperation.Input/Outputreguest (IORQ) is also
active lowbut indicates when the lowerhalf ofthe address bus holds
avalidI/OaddressfortheULAduringI/Oread/writeoperations.
3.6Thereadandwritesignals(RDandWR)areactivelow,andoneor
otherisactiveindicatingthattheCPUwantstoreadorwritedatato
a memory location orI/O device. Allthe control signals discussed so
farareactivelow,tri-stateoutputs.
Thecontrolsignaldescribedhereistheinterrupt
3.7 last maskable
(INT). This input is active lowandis generated bytheULA once
every20ms.EachtimeitisreceivedtheCPU'calls'the'maskable
interrupt'routineduringwhichthereal-timeisincrementedandthe
keyboardisscanned.
3.8CPU Clock.Returning totheCPU clock mentioned earlier in this
section,theULAisabletoinhibitthisinputbringingtheCPUtoa
temporary halt. This mechanism gives theULA absolute priority,
allowingittoaccessthestandard16kRAMwithoutinterferencefrom
theCPU(seeRAMdescription).SwitchingtransistorTR3ensuresthat
theclockamplitudeis+5VratherthansomearbitraryTTLlevel.This
isessentialiftheCPUistooperateeffectivelywhileexecutingfast
machinecodeprogramsofthe'spaceinvader'^'
1.2

3.9 Dynamic Memory Refresh. TheCPU incorporates built-in dynamic RAM
refreshcircuitry.AspartoftheinstructionOPcodefetchcycle,
theCPU performs a memory requestafter first placing the refresh
addressonthelowereightbitsoftheaddressbus.Attheendofthe
cycletheaddressisincrementedsothatover255fetchcycles,each
rowofthedynamicRAMisrefreshed.Thismechanismonlyappliesto
theoptional32kexpansionRAMinthe48kSpectrum.Analternative
refreshmethodisadaptedforthestandard16KRAM.
4.MEMORYORGANISATION
4.1Inthe standard 16k Spectrum there are32k bytes of addressable memory
equallydividedbetweenROMandRAM.
4.2The lower 16k bytes of memory (addresses 0000 - 3FFF) are implemented
ina singleROM(IC5)whichholdsthemonitorprogram.Thisprogram
isa complexZ80machinecodeprogramdividedbroadlyintothreeparts
one eachcovering the input/outputroutines, the BASIC interpreter and
expressionhandling.Detailsoftheprogramcontent,althoughoutside
the scope of this manual, are referred toas necessary.
4.3The upper 16 bytes of memory (addresses 4000 - 7FFF) are implemented
using eight 16kbit dynamic RAMs (IC6-IC13). Approximatelyhalf of
this space is available tothe user for writing BASIC or machine code
programs.Theremainderisusedtoholdthesystemvariables
including6kbytesreservedforthememorymappeddisplayarea.
4.4Inthe48kSpectrumanadditional32kbytesofRAMareprovided
(addresses 8000 - FFFF) which are implementedusing eight 32kbit
dynamic RAMs (IC15-IC32). The RAM,providing extra memory space for
theuser,isnormallyfittedduringmanufacturebutmaybeadded
retrospectively using the RAM expander kit. In addition tothe RAMs,
thekitincludestheaddressmultiplexerandread/writecontrolICs
IC23-IC26. Board space andthe necessary discrete components are
alreadyprovidedontheboard.
4.5Read/WriteOperations
4.5.1Thefollowingdescriptionshouldbereadinconjunctionwiththe
circuitdiagramsgiveninFigures1.4and1.5.
4.5.2ReadOnlyMemory(ICS).TheCPUaddressestheROMdirectlyduring
memoryreadcyclesusingtheaddressbusA13-AO.MREQandRDenable
theROMandtheROMoutputsrespectively.A thirdinput(CS)derived
bytheULA'ROMCS)selectstheROM,providedthehigherorderaddress
bitsA14andA15arebothlow.Thesearereservedforaccessingthe
RAMmemorywhichstartswithaddress4000(i.e.addressA14set).An
externalROM1Cselectinput,suppliedviatheexpansionportonpin
25A,selectivelydisablestheon-boardROMbypullingtheselectinput
high.ByvirtueofR33placedontheULAsideoftheROMtheULA
ROMCSoutputiseffectivelyinhibited.Interface1 usesthis
1.4

mechanismallowingtheCPUtoreadtheextensionROMintheinterface
formicrodriveandRS232applications.
4.5.3 Links H andN, shown directly above IC5, allow a second source ROMto
be fitted. The Hitachi (H)andNEC(N) ROMs use differentpins for
the enable and select inputs(i.e.pins 20and 27). The links allow
theinputstobereversedaccordingly.
4.5.4Standard16kRAM(IC6-IC13).Theeight16kRAMICsmakingupthe
standard16kx 8 bitRAMmemoryareorganisedasa matrixof128rows
x128columns.Thus,separate7-bitrowandcolumnaddressesare
reguiredtoaccessanyoneofthelocations.Theseaddressesare
suppliedbytheCPUonaddressbusA13-AOviaanaddressmultiplexer
IC3/IC4. Thelow orderaddress bits A6-AO give therow address and
are selected atthe beginning ofthe memory accesscycle when
initially theRAS output from theULAis high.Later, astherow
address is latched, RAS goes low selecting the highorderaddress bits
A13-A7givingthecolumnaddress.
4.5.5TheRAS/CASoutputsfromtheULAaregeneratedinseguenceinresponse
to MREQ andA14 from_the CPU. The DRAMWE output,also from theULAis
a decode ofthe RD/WR waveforms telling theRAMto expect either a
readora writecycle.
4.5.6 Itis alsoapparent from the circuit diagram that theULAcan access
RAMbygeneratinga setofaddressesindependentofthosegeneratedby
theCPU.TheaddressportfortheRAMisthereforedualledbythe
insertion of smallvalue resistors (R17-R23) onthe address
multiplexersideoftheRAM.Thisensuresthatwherethereislikely
tobeconflictbetweentheULAandCPU,theULAaddresshaspriority.
Priority is assigned onthe basis that theULA must access the memory
mappeddisplayareaintheRAMatsetintervalsinordertobuildup
thevideofortheTVdisplay.IftheULAisabouttoaccesstheRAM
anditdetectseitherA14orA15(i.e.theCPUisalsoabouttoaccess
theRAM)theULAinhibitstheCPUclocktemporarilyhaltingtheCPU
memory transaction until itsown transaction is completed.
4.5.7Resistors RltoR8,in series with the data bus lines, perform a
similar function tothe addressportplr£sistorsdescribedabove. They
ensurethattheULAdoesnot'see'CPUwritedatawhiletheULAis
accessingtheRAM.
4.5.8Refreshforthestandard16kdynamicRAMisaccomplishedduringnormal
readcycles,i.e.mostrowsarerefreshedeachtimetheULAaccesses
the memory mapped displayareaduring picture compilation; the
remaining rows are refreshed asa result of otherread cycles also
known to occur at regular intervals within the refreshperiod.
1.5

4.5.9 32k Expansion RAM (IC15-IC32). The eight 32kICs making upthe32kx
8bitexpansionRAMareinfact64kICswitheitherroworcolumn
drop-outrenderingonehalfofthememorynon-functional.Inorderto
accommodate the Texas Instruments RAM (Type TMS 4532) orthe optional
OKIRAM (Type MSM3732) a setof links are provided, visible onthe
circuit diagram above the address multiplexer IC25/IC26. These links
notonlycaterforthedifferentmanufacturer(Issue3 Spectrumsonly)
butalsoallow,inbothinstances,oneoftwo1Cversionstobe
selecteddependingonwhichhalfoftheRAM(top,bottom,leftor
right)isfunctional.ThelinksarerespectivelyTIandOKI
(manufacturer- Issue3 Spectrumsonly),-3/-4(TIversion)and-H/-L
(OKIversion- Issue3 Spectrumsonly).
NOTE: Itis essential when replacing ICsin this area that all RAMs
carry the same manufacturers part number and that the links
areselectedaccordingly.
4.5.10TheexpansionRAMisorganisedasa matrixof128rowsx 256columns
(TI RAMs) or256 rows x 128 (OKI RAMs). Thus, separate 7/8bitrow
andcolumnaddressesarerequiredtoaccessanyoneofthese
locations.TheseaddressesaresuppliedbytheCPUonaddressbus
A14-AOviaanaddressmultiplexerIC25/IC26.Forexample,when
accessingtheTIRAMtheloworderaddressbitsA6toAOgivetherow
address;ARisheldlowonthe-3versionselectingthetophalfof
the memory and high onthe-4 version selecting the bottom half. The
column address is given bythe highorderaddress bits A14-A7.
4.5.11 Row/column address selection and RAS/CAS timing forthe RAM is decoded
in IC23/IC24 from inputs supplied bythe CPU,i.e.address line A15
selecting addresses 8000 upwards, and MREQ heralding a memory read or
writecycle. A theoretical timingdiagram illustrating the RAS/CAS
waveformsisgiveninFigure1.2.
5.INPUT/OUTPUT
5.1Theinput/outputsectionoftheSpectrumiscenteredroundtheULA
(IC1).ThefunctionsperformedwithinthedeviceincludeTVvideo
compilation,keyboardscanningandtapeinput/output.Italsoderives
and controls theCPU clock (<j>CPU) using an external 14MHz crystal XI,
and drives the loudspeaker when a 'BEEP' instruction is being
executed. Each of these sections andthe supporting circuits are
describedbelow.
5.2TVPictureGeneration
5.2.1ThevideocompilationsectionoftheULAoperatesinconjunctionwith
the memory mapped picture displayarea inthe standard 16k RAM, the
colour(chrominance)modulator(IC14)andtheUHFmodulator.This
combinationproducesa highresolution,24linex 32character,eight
colourTVdisplay.
1.6

FIG1.2EXPANSIONRAMRAS/CASTIMING(READCYCLESHOWN)
1.7

5.2.2 Using the14MHz clock theULA derives line and fieldtiming
compatiblewiththeexternalTVreceiver.Videoisderivedby
accessingthememorymappeddisplayareaintheRAMina setseguence
atsettimesthroughoutthepictureframe.Theaddressesare
necessarilyindependentoftheCPUandappearontheULAaddresslines
A6 through AOastwo separatebytestimed bythe RAS/CAS row/column
addressselectlines.
5.2.3 Thenet result is three separatevideo waveforms outputs from theULA
onpins15,16and17.ThesecarrytheluminancesignalY,
incorporatingthelineandfieldsync,andtwounmodulatedcolour-
differencesignalsU andY makingtheSpectrumcompatiblewithboth
colourandmonochromereceivers.
5.2.4 From theULAthe colourdifference signals are applied tothe colour
modulatorIC14viatwolevelshiftingnetworks.ThesematchtheULA
outputlevelswiththosereguiredattheB-YandR-Yinputstothe
modulator.IntheIssue2 Spectrumthelevelshiftingnetworkis
passive,incorporatingtwopotentiometersVR1,VR2.Theseare
reguired to set-up the chroma bias level on IC14 pin3 such that the
voltagedifferencemeasuredbetweenpin3 andthecolourdifference
signals on pins 2 and3 respectively is nominally 0V d.c. Inthe
Issue3 SpectrumtwoactivenetworksincorporatingIRSandTR9
eliminatethepotentiometers,greatlyimprovingcolourstability.
5.2.5Thelevelshiftedcolourdifferencesignals,inputtoIC14,arethen
encoded,byguadraturemodulatingtwo4.43MHzchromasub-carriers.
Thesub-carriersaregeneratedwiththeassistanceofanexternal
crystalX2anda CRlead/lagnetworkintroducinga 90°phaseshift
betweenpins1 and18.(AfurtherdifferencebetweentheIssue2 and
3 Spectrums lies inthe bias oscillator. The early issues incorporate
atrimmerTC2allowingthechromasub-carrierfreguencytobe
adjusted; onthe later issues the freguency is fixed). The resultant
modulatedcolourdifferencesignalsarefinallymixedproducinga
compositechromasub-carrieratIC14pin13.
5.2.6 At this point the chroma signal is a.c.coupled tothe base ofTR2and
addedtotheinvertedluminencesignalonTR1collector.The
resultantcompositevideoisthenbufferedandappliedtoan
encapsulatedUHFmodulatoroperatingonEuropeanstandardchannel36.
5.3KeyboardScanning
5.3.1Every20ms(i.e.oncepermaskableinterrupt),theCPUsystematically
scansthekeyboardrecordingwhich'keys'(ifany)havebeenpressed.
ThescanningmethodisdescribedbelowwiththeaidofFigure1.3.As
the figure clearly illustrates the keyboard consists ofan8 x 5
matrix,theinter-sectionofeachrowandcolumnbridgedbya normally
openswitchcontact.Therow'outputs'andcolumn'inputs'areshown
connectedbyseparateribboncablesKB1andKB2,onetotheULAand
the other tothe highorderaddress lines A15-A8. Pull-up resistors
R64 through R68 ensure that when the address busisinthe high Z
state, or none ofthe key-switches is closed, row outputs KBOtoKB4
remainhigh.

5.3.2 When the keyboard scanningroutines are entered theCPU performs
successive I/O readcycles setting the IOREQ andRD lines tothe IJLA,
low.Atthesametime,theI/Oportaddressesplacedontheupper
halfoftheaddressbusaremodifiedwitheachcyclesuchthateachof
theaddresslinesA15throughA8issetlowinturn,theotherlines
remaininghigh.
5.3.3TheseguencestartswithI/OportaddressFEdrivingaddresslineA8
low. The keyboard matrix also sees this potential on column 6 applied
viaD6andtheribboncableKB2.Thus,whenanyoftheswitcheson
theinter-sectionwithcolumn6 ispressed,thecorrespondingrow
outputsupplying theULAviathe second ribbon cable (KB1), is pulled
low.Therowsignal(s)issubseguentlyinvertedbytheULAandplaced
ononeofthe five low orderdata bus lines. For example, ifthe CAPS
SHIFT keyis pressed rowone output drives data busDO high andsoon.
TheseguenceendswithI/Oaddress7Fwhencolumn8 isaddressed.In
this instance,operation ofthe SPACE key drives DO high.Clearly,
the keyboard scanningroutines make the distinction between the CAPS
SHIFT and SPACE keyby knowing which address line is beingdriven.
5.4TapeInterface
5.4.1 WhenLOADing or SAVEing programs using a cassette recorder, theULA
transfersinformationbetweentheMICandEARsocketsandthedata
bus, performing A/DandD/A conversions as reguired.Since the LOAD
and SAVE functions are mutuallyexclusive, a single pinontheULA
(i.e.pin28)isusedbothforinputandoutput.SeparateI/O
read/writecyclestoportaddress254configurethepinaccordingly.
During the LOAD operation theCPU executessuccessive I/O readcycles,
reading theEAR input off data bus6. When performing a SAVE
operation,theCPUexecutessuccessiveI/Owritecycles,thistime
writingdatatotheMICoutputviadatabus3.
5.4.2 To ensure that I/O cycles are correctly implemented, the IOREQ line
supplying theULAis gatedwithaddress line AOvia TR6. Thus, ifany
memorytransactionsoccurwhereAOishigh(i.e.notportaddress254)
then the IOREQ input is forced high inhibiting any attempt to perform
anI/Ocycle.
5.4.3 Loudspeaker (BEEP) Operation. It should be noted that while SAVEing,
theleveloftheMICoutputisbarelysufficienttodrivethe
loudspeakerviaD9andTR7(D10).However,duringtheexecutionofa
BEEP instruction theCPU writesinstead to port 254on data bus4.
ThiseffectivelybooststheMICoutput,drivingtheloudspeakerso
that the BEEP tone canbe easily heard. During the execution of such
aninstructionthecassetterecorderisnotrunningsothereisno
conflict atthe MIC/EAR sockets.
1.10

6.POWERSUPPLIES
6.1The on-board power supply unit receives a 9V unregulatedsupply from
theexternalSinclairZXpowerpackandderivesthefollowinginternal
supply rails:
(a)regulated+5Vforthe1Clogiccircuits,theULAandtheUHF
modulator,
(b)-5Vand+12Vforthestandard16kdynamicRAM,
(c)+12Vforthecolourmodulatorcircuits.
6.2Theexternalpowerpackincorporatesa mainstransformer,fullwave
rectifierandcapacitivesmoothing.A thermalfuseisfittedatthe
transformerinput.
6.3The on-board power supply unit incorporates a 7805 regulator, deriving
the+5V power rail, andan inverter stage TR4/TR5. The latter raises
thelevelofthe+9Vunregulatedsupplytoinexcessof+12V.The
resultantsguarewaveatthejunctionofTR4collectorandthe
inverter coil is subseguently rectified and smoothed by D5/C44
producingthe+12VoutputfortheRAM.Additionalsmoothing,imparted
by R62/C45, produces the +12Vsupply fortheTV circuits free from
noisegeneratedbytheRAM.ThesguarewaveatTR4collectoralso
supplies the Zener/rectifier diodecombination D16/D12 generating -5V
fortheRAM,andisavailableattheexpansionportforuseby
peripherals.The+12V,+5Vand-5Varealsomadeavailable.