Radio Shack 26-3501 User manual

TRS-80 Pocket Computer and Cassette Interface
Catalog Number: fJJJOJ

TABLE OF CONTENTS
1. SPECIFICATIONS l
2. BLOCK DIAGRAM 3
3. LSI SIGNAL DESCRIPTIONS jq
A. BEFORE SERVICING ]4
5. CASSETTE TAPE &INTERFACE 14
6. CASSETTE OPERATION I5
7CHFCK PROGRAM 22
8. CIRCUIT DIAGRAM PARTS 4SIGNALS POSITION 28
Operation circuit diagram 23
Operation P.C.B 24
Key i<i I „.
Key P.C. B^
26-3503 uicoil <iiagi<un 27
26-3503 P.C.B g?
9. PARTS LISr FOR 26-3501 28
10. PARTS USr FOR 76-.1501 gg

1. SPECIFICATIONS
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Display
•Display tube: LI-80I7JI.
•Display method 5» "dot matrix liquid crystal
•Display capacity: 24 columm (alphanumeric; and tymboh)
Basic functions
Computational rapid ty
Comptiia:ional method:
Capacities:
12dt^ifsof mantissa ind 2 digits of exponent.
According lo maiheirntiral formula (with priority consideration arid judge function)
Buffers:
M24 steps, max
Fixed memory
20 nxmoilei
Flexible memory ^commonly usable »it!i ire prog
178 memories, max
I£ktniti. as ttepc, miv
SO steps
8stages
l-'uncliona) buffer. 16 stages (but 15 napes fur parenthesis)
Subroutine buffer; 4stages
"FOR NLXT" statement buffer: 4stages
1'iogram memory;
Data memory;
W^pw program;
Inpui buffer:
Data buffer.
mi iiinnot y
Arithmetic functions
Acd (*). Subtract [-% Multiply (+), Divide (,<). Power raising (A)
Tngonometric functions:
Inverse trigonometric fur.ctlonr
Logarithmic fuactom:
hxponenial tunciom:
Ar&uiar transformations:
S-quotO r..'! ;\tr.i ,1 ni.
Slgniim fnnrtlnn:
Absolut evalue:
Integration:
SIN (sine). COS (cosine). TAN (tangent)
ASN (line '). ACS (cosine'1). AT\ (tangent '
)
LOG (common logarithm). LN (natural logarr.hni |ln|
)
\i\? (exponential)
DMS (decimal notation to sexagesimal notation).
DEG (lexageMiinl notation tu decimal nuiation)
J
SCN
rVBS(|X0
INT
Kxccoticn of arithmetic operation is commanded by ilie ENTKR key.
Editorial functions
Cursor shift:
lmetlinn:
Deletion:
Line control:
(right). <(left)
INS
DEL
I(down). T(up)

Programming language
BASIC (Beginner's All p«pose Symbolic Initruction Code)
Power source
Battery; Four MR44 <m«rcury ba«eri*s)
Ra<t*ry liiV J00 hours
Power conJump ion: 0.01 1
W
Automaitc powei shutofl: About 6rainules
Miscellaneous
Data protection: Program memory, dau mcmaiy. re$er*e program memory
Peripheral unit: Audio OMMtte unit (recording/Tending (if rfi* prrgram Trmory. dali mentnry and MMf*t
program memory)
Optional 26-3503 (audio cauei ic interface)
PhyMcal iimenaora: 17S(W) x70(D) x44(11) mm <6.8<W) x 2.7(D) x1.7(H) inches)
Weight: Afprox. I70g(0.37 lbs) ... 26-3501
Aceiox. 240b (0.5J lbO (with batUri**) _. 2G-3S03
For torapttfr frttili of optratna ttw TRS-80 Pockt Computer, rrfii to fh« Qwntr't Minunt.

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System configuration (see the s/stem block diagram)
The system consists of (he following components:
1. CPUI(SC43I77)« I
2. CPUU(SC43l7S)x I
3. 4K-bltRAM(rOM4)*x3)
4. Display chip (SC43I23 «3. with Duilt-in RAN)
5. 2ANDga(e<TC4011UrJP*l)
6. 2AMJ20H(K4yivUCx I)
7. lnvwter(TC4069BPx I)
S. Quard Analog Switch Miiltiplover (TCdOAtBP)
o. ITD(34-di8it FhMdot LCD)
10. Key
11. Crystal (CSB2560)
Brief overview of CPU Iand CPU II
The CPUs are provided with internal ROM.and the CPUs have ihe following assignments
CPU I
Key input rostine
Acknowledgement of the remaining
program
One instruction to one program step
additional incoiporatton
Interpreter:
Pio&aiii execute italciiuul
CdSSCtlt tuillfol MdUlUClil
Cummand ilateimnt
Pointer control (leserved)
v-irii'i lit mrinutl opentnn
Piw.resumt control
Clouk Hup centred
CPU
Display proceHing routine
Input buffer
Cunipuiaiional result
trr'T
Ai >Uim>tit H'jlirc
Character geritiatoi
(arctic routine
Print tontine
Qj,uei
Rprngnitlor: nf printer (reserved)
I'oiver "t I
Clojk nop
•The CPU Iiu.ii;;i, ia read key-ii data ur read (tie instruction to be execute*] fiom the RAM, and decides what is to be
don* (or Iho loiuitl of aritlunebco': operation* (i.e., control of arithmetic sequence, memorieingof arithmetical Jots, and its
-i I '.or interpret the cyntnx of the BASIC instruction for deciding what is to be executed, or determine* and prepare*
the information lo be displayed, but CPU" Idoei not perfiwm any execution By itself. Il only arranges ihedata and inlorma-
tlon in proper sequence and acts to provide instruction codelo the fPL II via the buffer. On Uteothet hind. CPU Dconstant-
ly receives execution instructions from CPU Ivia the transfer buffer and executes operations pei each infraction or ex-
changes data, depending on the situation. Although it shares eA«.uiio>! fum-lions and tieifoiai* some auxiliary CPU rolcs.it
does net perform any decision by itself.
Eg- Actions of CPUIand tPU Uat the lime of key data entry.
irt
kvv u
For ni ui'. il operation of ihe Pocket Computet, the uislructlon code (key code) awritten (mo the RAM in the display chip
(Input buffer) after Information is put through the kcybwitd and converted into the instruction code by CPU I, then this inst-
ruction code (display! is transferred to thoCPt-111 vis the transfer butler. As CPU Disceivei this inctmciion. CPU II ther decodes
this imtmction <display) and executes dlisplay processing Upon the completion of this processing, it notitlei CPU I, and CPU I
confirms the completion of the vak hy ihe CPU 11 before lermimtirg their function!.

Overview of RAM
Three C-MOS RAMs (I —3 chips. 4K bin each) plus RAM Incorporated In the display chip aie used in ihii Pticket Computet, ai
described below:
•Mapol4K-bf. RAM
103OD/ie>
Rtnnn orostor*
Prog'am
tipihlpmowflfv
001
IMfi
1«7?
Fined mmonei <¥Y -£i
b*oume
HiKli
^04 Aithojgrt RAM aiea is mainly shar*d by ihe prog-air., daia and reserve program
FOR KEXT
q-.-k. isgg memories. i( is also usee I'm the subroutine sack. FOR NhXT staiemert slack and
fixed memories (W. X. Y.Z).

Map of the KAK1 incorporated xi Ihc Jispluy chip
Tl.cic are lincc IK-Ii.t KAMs (12S bytes each) incorporated in each display chip (SC431 25). willi the following condguio-
t.cns:
DISPLAY CHIP 1
IJOIJ
two
(MS
I2S
8-digil display buffet
Trarufci btffc:
fiO-step input buffe
DISPLAY (HIP 3
8-digit display buffer
Fixed memories
(A—K. 1 1 memories]
DISPLAY CHIP 3
Sdijui display buffet
Fixed memories
(L— V. 1 1 memories''
8-digtt display buffer
4€ byln of 8-digt display buffer is used as Jdisplay data buffer during displaying and also used as abuffet iretrwry for
arithmetical result, during arithmetical operations.
Fixed memory
The loial memory of 176 bvies (fiorr the display chip 2and 31 is used asa fixed memories. A—V (22 memories).
1r-iemcy
•I '
IfefllH
Itanster buffer
oliyies (I memory equivalent ior f>spl;ty Chip 1is used as atransfer buffer for transactions of instruction*, let ween CPU I
and CPU B.
Input buffer
Remlining HO Syt>s (1(1 me-iioi-ipt e-yiivilent) nf Display Chip Ikuserl I'm the inroil buffet as follow*:
IAny information tnlered through the keyboard is stored in this buffet, allowing up to HO steps.
2. Be dispJayconieiis are stored by CPU 1. and CPU Dselecii data.
3. When an arithmetical instruction is emered. its piocedute is stored in ibis suffer by CPU I. and CPU II performs open*
lions according to the procedure.
4
.
When aprogram or reserve program is to be recorded or read out during the execution nf the tassctlc control nstruction.
action tikes place through this input buffer.

Overview of Display
The coniems til fhr itaptoy AS indicated by CPU Iis reoeiwd by CPU II via ih* input buffer ind are ccnvericd into respective
cliaric*«l etides. ihey arc transferred to the display buffer in the Diiplay (hip lluuugh the adjiess data bus.
*Designation of 'he display i-n
IJie rolkwitigsiru.'tureii observed in the display buffer mthe Display Chip.
*/
A« K? WA*
1
\
F
1
1
1
F
1
(1 1 II
)
p
Aifcli e>i
JfCOCPt \
Tlu-.c arc 8*40 *320 bill (40 tyies) of area in the display
buffer in Ifce Display Chip.
hg: tiitiplay numerical "4"
il- 114 ii> tit 113 'VI 111
XOI) 1
xI
I.0
III
HiidPiV bat*—
|in n[ i) rm
loijniog |i
SI "' nnnin
ss "'DOilD
»»Din«n
M+ BDD1D
"'
Sll "SDDDID
SI7 H7Qaa«D
sis SI S2 S3 S4 S5
'S33
•-'
T
IHOI
11104 1)102 MO* 1H02
A5- A5-0
The numeral "4" (to be displayed by CPU II) is cotiTcrtcd into He lele.am character code and earned (hrouah on the address
data bus. hirst, the segnwni Si isvkned with the address A8-AI "OOOOOOCO" to store iheday DNM-DIOI '1000" in the
display butler (see above illustration). To store the second 4biis of thedaia. only A5 in the address in turned *l "in mike ihe
addieis "OUQJOUOO" io store daia "tOOT. In ihe same manner, address "OOOOtXlOl" is sefected for storing the Prst 4-bit data
"Oioo" for icgmcm 52 and ihe second 4-bttdaia 'OOQi"issioted with the addies "1X101001)1".

Timing Signal* for Displaying "4'
MSP
HA
HI
H2
H3
114
Hi
116
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HA: Ucek frequency for me counter. mis signal It counted and decoded to perToim iynchiorUzation wliJi UK common
Mgndl.Hl-HV.geneiaicdliom CPU D.
DSIP: Wiih high level wf lhi» itgnal.pioc*siinft of display operation ii indicated (RAM data designated by HI ~-118 is »*m out on
Sl~S40).
The dam MOtcd in the displa) buffet beamed through Si ~S40 (illustrated ibuve)tobc fed to the LCD. (lb indicate "4" un
thf <!i*pl*y. IW and lit »rr cnpgfH tor Si .lllitivl Wfor S?. etc ,tlm.ugh Rn -S40.)