Radio Shack 26-3501 User manual

TRS-80 Pocket Computer and Cassette Interface
Catalog Number: fJJJOJ

TABLE OF CONTENTS
1. SPECIFICATIONS l
2. BLOCK DIAGRAM 3
3. LSI SIGNAL DESCRIPTIONS jq
A. BEFORE SERVICING ]4
5. CASSETTE TAPE &INTERFACE 14
6. CASSETTE OPERATION I5
7CHFCK PROGRAM 22
8. CIRCUIT DIAGRAM PARTS 4SIGNALS POSITION 28
Operation circuit diagram 23
Operation P.C.B 24
Key i<i I „.
Key P.C. B^
26-3503 uicoil <iiagi<un 27
26-3503 P.C.B g?
9. PARTS LISr FOR 26-3501 28
10. PARTS USr FOR 76-.1501 gg

1. SPECIFICATIONS
ca ®l;J E3 Ld CEl 3ssl
hm[f] [vi rj (i Loj >
iee ra SGH 11I . 5
l«J L*J ta LX3 Xi JLI [-_ 6pc fNUH i
KMMVWIt ->YS <
7m m m ia
I4"i ss' *: «^
(T ej ce 3E
ra cr i«j is e
Display
•Display tube: LI-80I7JI.
•Display method 5» "dot matrix liquid crystal
•Display capacity: 24 columm (alphanumeric; and tymboh)
Basic functions
Computational rapid ty
Comptiia:ional method:
Capacities:
12dt^ifsof mantissa ind 2 digits of exponent.
According lo maiheirntiral formula (with priority consideration arid judge function)
Buffers:
M24 steps, max
Fixed memory
20 nxmoilei
Flexible memory ^commonly usable »it!i ire prog
178 memories, max
I£ktniti. as ttepc, miv
SO steps
8stages
l-'uncliona) buffer. 16 stages (but 15 napes fur parenthesis)
Subroutine buffer; 4stages
"FOR NLXT" statement buffer: 4stages
1'iogram memory;
Data memory;
W^pw program;
Inpui buffer:
Data buffer.
mi iiinnot y
Arithmetic functions
Acd (*). Subtract [-% Multiply (+), Divide (,<). Power raising (A)
Tngonometric functions:
Inverse trigonometric fur.ctlonr
Logarithmic fuactom:
hxponenial tunciom:
Ar&uiar transformations:
S-quotO r..'! ;\tr.i ,1 ni.
Slgniim fnnrtlnn:
Absolut evalue:
Integration:
SIN (sine). COS (cosine). TAN (tangent)
ASN (line '). ACS (cosine'1). AT\ (tangent '
)
LOG (common logarithm). LN (natural logarr.hni |ln|
)
\i\? (exponential)
DMS (decimal notation to sexagesimal notation).
DEG (lexageMiinl notation tu decimal nuiation)
J
SCN
rVBS(|X0
INT
Kxccoticn of arithmetic operation is commanded by ilie ENTKR key.
Editorial functions
Cursor shift:
lmetlinn:
Deletion:
Line control:
(right). <(left)
INS
DEL
I(down). T(up)

Programming language
BASIC (Beginner's All p«pose Symbolic Initruction Code)
Power source
Battery; Four MR44 <m«rcury ba«eri*s)
Ra<t*ry liiV J00 hours
Power conJump ion: 0.01 1
W
Automaitc powei shutofl: About 6rainules
Miscellaneous
Data protection: Program memory, dau mcmaiy. re$er*e program memory
Peripheral unit: Audio OMMtte unit (recording/Tending (if rfi* prrgram Trmory. dali mentnry and MMf*t
program memory)
Optional 26-3503 (audio cauei ic interface)
PhyMcal iimenaora: 17S(W) x70(D) x44(11) mm <6.8<W) x 2.7(D) x1.7(H) inches)
Weight: Afprox. I70g(0.37 lbs) ... 26-3501
Aceiox. 240b (0.5J lbO (with batUri**) _. 2G-3S03
For torapttfr frttili of optratna ttw TRS-80 Pockt Computer, rrfii to fh« Qwntr't Minunt.

s
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iit
ao£
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KtHI-iniU
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B*ae
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System configuration (see the s/stem block diagram)
The system consists of (he following components:
1. CPUI(SC43I77)« I
2. CPUU(SC43l7S)x I
3. 4K-bltRAM(rOM4)*x3)
4. Display chip (SC43I23 «3. with Duilt-in RAN)
5. 2ANDga(e<TC4011UrJP*l)
6. 2AMJ20H(K4yivUCx I)
7. lnvwter(TC4069BPx I)
S. Quard Analog Switch Miiltiplover (TCdOAtBP)
o. ITD(34-di8it FhMdot LCD)
10. Key
11. Crystal (CSB2560)
Brief overview of CPU Iand CPU II
The CPUs are provided with internal ROM.and the CPUs have ihe following assignments
CPU I
Key input rostine
Acknowledgement of the remaining
program
One instruction to one program step
additional incoiporatton
Interpreter:
Pio&aiii execute italciiuul
CdSSCtlt tuillfol MdUlUClil
Cummand ilateimnt
Pointer control (leserved)
v-irii'i lit mrinutl opentnn
Piw.resumt control
Clouk Hup centred
CPU
Display proceHing routine
Input buffer
Cunipuiaiional result
trr'T
Ai >Uim>tit H'jlirc
Character geritiatoi
(arctic routine
Print tontine
Qj,uei
Rprngnitlor: nf printer (reserved)
I'oiver "t I
Clojk nop
•The CPU Iiu.ii;;i, ia read key-ii data ur read (tie instruction to be execute*] fiom the RAM, and decides what is to be
don* (or Iho loiuitl of aritlunebco': operation* (i.e., control of arithmetic sequence, memorieingof arithmetical Jots, and its
-i I '.or interpret the cyntnx of the BASIC instruction for deciding what is to be executed, or determine* and prepare*
the information lo be displayed, but CPU" Idoei not perfiwm any execution By itself. Il only arranges ihedata and inlorma-
tlon in proper sequence and acts to provide instruction codelo the fPL II via the buffer. On Uteothet hind. CPU Dconstant-
ly receives execution instructions from CPU Ivia the transfer buffer and executes operations pei each infraction or ex-
changes data, depending on the situation. Although it shares eA«.uiio>! fum-lions and tieifoiai* some auxiliary CPU rolcs.it
does net perform any decision by itself.
Eg- Actions of CPUIand tPU Uat the lime of key data entry.
irt
kvv u
For ni ui'. il operation of ihe Pocket Computet, the uislructlon code (key code) awritten (mo the RAM in the display chip
(Input buffer) after Information is put through the kcybwitd and converted into the instruction code by CPU I, then this inst-
ruction code (display! is transferred to thoCPt-111 vis the transfer butler. As CPU Disceivei this inctmciion. CPU II ther decodes
this imtmction <display) and executes dlisplay processing Upon the completion of this processing, it notitlei CPU I, and CPU I
confirms the completion of the vak hy ihe CPU 11 before lermimtirg their function!.

Overview of RAM
Three C-MOS RAMs (I —3 chips. 4K bin each) plus RAM Incorporated In the display chip aie used in ihii Pticket Computet, ai
described below:
•Mapol4K-bf. RAM
103OD/ie>
Rtnnn orostor*
Prog'am
tipihlpmowflfv
001
IMfi
1«7?
Fined mmonei <¥Y -£i
b*oume
HiKli
^04 Aithojgrt RAM aiea is mainly shar*d by ihe prog-air., daia and reserve program
FOR KEXT
q-.-k. isgg memories. i( is also usee I'm the subroutine sack. FOR NhXT staiemert slack and
fixed memories (W. X. Y.Z).

Map of the KAK1 incorporated xi Ihc Jispluy chip
Tl.cic are lincc IK-Ii.t KAMs (12S bytes each) incorporated in each display chip (SC431 25). willi the following condguio-
t.cns:
DISPLAY CHIP 1
IJOIJ
two
(MS
I2S
8-digil display buffet
Trarufci btffc:
fiO-step input buffe
DISPLAY (HIP 3
8-digit display buffer
Fixed memories
(A—K. 1 1 memories]
DISPLAY CHIP 3
Sdijui display buffet
Fixed memories
(L— V. 1 1 memories''
8-digtt display buffer
4€ byln of 8-digt display buffer is used as Jdisplay data buffer during displaying and also used as abuffet iretrwry for
arithmetical result, during arithmetical operations.
Fixed memory
The loial memory of 176 bvies (fiorr the display chip 2and 31 is used asa fixed memories. A—V (22 memories).
1r-iemcy
•I '
IfefllH
Itanster buffer
oliyies (I memory equivalent ior f>spl;ty Chip 1is used as atransfer buffer for transactions of instruction*, let ween CPU I
and CPU B.
Input buffer
Remlining HO Syt>s (1(1 me-iioi-ipt e-yiivilent) nf Display Chip Ikuserl I'm the inroil buffet as follow*:
IAny information tnlered through the keyboard is stored in this buffet, allowing up to HO steps.
2. Be dispJayconieiis are stored by CPU 1. and CPU Dselecii data.
3. When an arithmetical instruction is emered. its piocedute is stored in ibis suffer by CPU I. and CPU II performs open*
lions according to the procedure.
4
.
When aprogram or reserve program is to be recorded or read out during the execution nf the tassctlc control nstruction.
action tikes place through this input buffer.

Overview of Display
The coniems til fhr itaptoy AS indicated by CPU Iis reoeiwd by CPU II via ih* input buffer ind are ccnvericd into respective
cliaric*«l etides. ihey arc transferred to the display buffer in the Diiplay (hip lluuugh the adjiess data bus.
*Designation of 'he display i-n
IJie rolkwitigsiru.'tureii observed in the display buffer mthe Display Chip.
*/
A« K? WA*
1
\
F
1
1
1
F
1
(1 1 II
)
p
Aifcli e>i
JfCOCPt \
Tlu-.c arc 8*40 *320 bill (40 tyies) of area in the display
buffer in Ifce Display Chip.
hg: tiitiplay numerical "4"
il- 114 ii> tit 113 'VI 111
XOI) 1
xI
I.0
III
HiidPiV bat*—
|in n[ i) rm
loijniog |i
SI "' nnnin
ss "'DOilD
»»Din«n
M+ BDD1D
"'
Sll "SDDDID
SI7 H7Qaa«D
sis SI S2 S3 S4 S5
'S33
•-'
T
IHOI
11104 1)102 MO* 1H02
A5- A5-0
The numeral "4" (to be displayed by CPU II) is cotiTcrtcd into He lele.am character code and earned (hrouah on the address
data bus. hirst, the segnwni Si isvkned with the address A8-AI "OOOOOOCO" to store iheday DNM-DIOI '1000" in the
display butler (see above illustration). To store the second 4biis of thedaia. only A5 in the address in turned *l "in mike ihe
addieis "OUQJOUOO" io store daia "tOOT. In ihe same manner, address "OOOOtXlOl" is sefected for storing the Prst 4-bit data
"Oioo" for icgmcm 52 and ihe second 4-bttdaia 'OOQi"issioted with the addies "1X101001)1".

Timing Signal* for Displaying "4'
MSP
HA
HI
H2
H3
114
Hi
116
H?
imi-
ruiJiruuinjinjinjiiiJinjinj
jt_zz£:
~u m—ar
—i_n
—
i-l
l,M'
"VIHU*
U
LT n
JT_r
_TLr
_r
SI XMWA. v//$/r
*^-^* ^r^r
HA: Ucek frequency for me counter. mis signal It counted and decoded to perToim iynchiorUzation wliJi UK common
Mgndl.Hl-HV.geneiaicdliom CPU D.
DSIP: Wiih high level wf lhi» itgnal.pioc*siinft of display operation ii indicated (RAM data designated by HI ~-118 is »*m out on
Sl~S40).
The dam MOtcd in the displa) buffet beamed through Si ~S40 (illustrated ibuve)tobc fed to the LCD. (lb indicate "4" un
thf <!i*pl*y. IW and lit »rr cnpgfH tor Si .lllitivl Wfor S?. etc ,tlm.ugh Rn -S40.)

Overview of Power supply
l}i>;i
MHHX*
%.1
'iX
cpun
GNU
ovpisp
RtlitonMiwr i«np«»iLue*iiO VOISP
*0' -V
The liquid crystal reference voltage VDISP is generated by the above circuity lo avoid bluncd ehaiaden cr contrast varia-
tion* that might cegnde display performance (which would be caused by aslight voltage variation hthe liquid crystal
referencevollaff- VDISP}.
a. VDD is generated mCPU II. referenced to VGG.
b. The gate voltage of MOS FET i& controlled by the 230K!2 put 10 regular the vullage foi VDISP. The FhorniMur \i provided
to compensate foi lemptvawre variaiion.
C. Ref*ren« voltage VDlSPit aiviicc by resistor combinations to provide VA, VM and VB-
VIlKPr In<u vnliag* fcw Rmnmnn tignaUtH' —117) fiv II'D
VA: llim vuli age for segment signals(SI-S40t
VM: Inlerrrediilevollage fur common and *gment signals
VB: Law voltage lor segment signals.
NOTE: VA, VM and VBbejune pulses, with jii amplitude of several TOllS, due to the influence nf the LSI.
Adjustment ot relerence voltage VDISP
VDISP had been precisely adjusted to -3,74V at an ambient temperature of 2GrOand -4.29V
al If it is necessary lo rcacjusi the voltage after servicing rhc LCD or changing some
components, he sure to look it ihe Display from a30sangle (from vertical) while adjusting
1he pot.
VA
VM
v»
VDISP
Hyo poiiiion

3. LSI SIGNAL DESCRIPTIONS
SC43177 (CPU I)
Pin No. Signal name IntOui De&flptftM
i
3
4
F4a
F3a
Fla
Oul
Out
Out
Out
Chip Enable signal (RAM3 Mlect signal
)
Chip Enable signal (RAM2 *•!«« signal)
Chip Enable signal (RAMI select signal)
Chip tnable signal (Display chip 1select ligrial
usage)
During display: Low **
Dining icad-iu: turns moiiicntaiily high
.lor input buffer and Irmsfer buffer
bVr.f; In Source voltage 1""voliage of baiteivl
7v,l( .In
8Xin In Basic clock (pulse signal, 256kH? 1
9
10
TESTI
test: Connected it. GND
11 RESET In All Reset Switch input
Normally high but turns low when the All Kesri Switch bpreyed.
12 RjWa Oui RAM Data Read/Wiitc signal
During disptoy* High
Pickings key causes it to morr*.«nlari}y 5.1 low -^
13
14
15
16
DIOl
DI02
DI03
DI03
In'Oul
In- Out
In' Out
In.' Out
l>ila HtR Ifor address detignation of the input buffer am
Ditnlav Phio 1 ,
1irmsfer buffer mRAM and
During dismay: High \\\\\ \\
During read-in Low •» \_\_\_V_i_\_\_
17
18
19
20
2)
22
23
24
D7a
B6a
B3a
Ma
B3a
B2a
Bla
Out
Out
Out
Oui
Oui
Oul
Out
Oui
Addtess Bus (for address designation of the input buffer ind r
and Display Chip 1).
fanslet buffer in RAM
Morient arv erncrationOnling display __ _
Dining icad-m 'Trnuini
1L
rnrn-
30 GND In Source voltage (0V)
40 51 Ga Oui Busy signal to CPU ll (High during execution in CPU t)
During display: Low
During toad in: tutiu itiuiticnliiiily lugli
41
42 Sn
Si
Out
On Kay Strobe signal. RAM Addrcts signal Key Stfrtbo signal. RAM Address signal
10

HdNo. Signal pjiw In' Out Description
43 SI 3Out Key Strobe -LiM.il
44 SI 2Out
4S SI 1Out Dining display High
46 SIO Out Pressing akey causes it to momentarily go low
47 59 Out
48 58 Out
49 S7 Out
SO 56 Oul
51 S5 Out
52 S4 Out
53 S3 Out
54 S2 Out
55 kil In Key input signal
56 Ki2 In
57 K13 In Owing display: Low
58 KM In Pressing akey causes nto momentarily go high
5<) SI 6b
(KiS)
In Busy signal of CPU 11 (high during execution t>f CPU H>
During dijpUy: Low J*
SC43178(CPUII)
Pin No. Siinal Ini'Out Description
1P4 Out Bu/.«i signal —
^
C25rni f^_
Whert tha buzicr it off: Low 1I-""1[~
~
".Tier ih* bWBW iv on High '1I—
J
2
4
F3
F2
Fl
Oul
Out
Out
Chip fcnible signal 1Display chip 3 select sienall
ChipEmble signal) Display chip 2select signal I
Chip Enable signal (Display chip 1aelecl signal)
During display: Low ___.-- -_
Duung tend-in Tmm tikiniciilai ily h-gh
5
6
7
Vc,c.
V,;r.
Out
In
In
Foi liquid crystal drive vullige preparation i.Vdd *Vc;c>
Source wluge(**-" voltage of Ihe battery)
eXin In Basic click (Pulse signal. 256kHz)
li RESEr In All Reset Switch input
12 WW Oul RAM Data Read/Write signal
During display High
Dining read-in- Turn* iiiuiiicitiailly luw **
1

nnNo 1Signal name In/Oiu DwtfjpttWi
14
lb
men
DI03
OIOZ
DIOt
In/Out
In/Out
In/Out
In/Out
l>.ita Bus (for data transaction between RAM and display ehipl
Dunne iea.Hn. Turns low -_^_^ \\\\\\\\
I?
IE
19
20
21
22
23
24
B8b
B7b
B6b
BSb
D4t
B3b
B2b
Bib
Out
Out
On!
Oui
Out
Oui
Out
Oil!
Address Bus (for address designaiion of the display chip!
Duringdisplay Blb» high. B2b Mow, B3b=bw. B4b-lov. BSb=high B6b =hieh.
B7b«low. BSb=low
l>urtng read-In: Turns momentarily high
25 HA Oui Display sijna'(fommiui signal couniiug pulser
Generated during display
*i 05m r
26 MSP Oui Display command signal
Dining display- High
During execution: Low
27
IB
29
VM
VA
GND
In
In
In
LCD display vnhagff (Intermediate voltage of the segmeni lignal)
LCD display voltage (High voltage of the segment signal)
Supply voltage (OVl
30
^1
32
33
34
35
36
144
H?
Hi
Ht>
H2
115
HI
Out
Oui
Oui
Out
Out
Out
OU!
LCD common signals (backplate)
3?
38
Vmsp
Vb
In
In
LCD display voltage ILow vrltage of ihe common signal)
LCD display voltage (Low vdiage of ihe segment signal)
39 510 Out Busy signal to the CIV 1(Ilijh during execution in CPU II)
During display: Low _^**^
40
41 S15
SI b
Out
Out
RcuoiJ signal tw the cassette tape and prinl idala.
Remote signal to the MT.
42 SI 3 Otit RiKy tibial i" r*inier.
43 ., Out Expansion signal
During display: Low ^^—-*"
12

PinNu Signa name In 'Out Description
49 S6 Out Fot DEF symbol display (engaged" low, aoi engaged: lilgfi)
54 SI Out Fnrtymhnl display (SHIFT DFC., KaUCVAD, P.FSFKVF, PKO RUN)
Same waveform as the segment signal
.
55 Kit
(SI 6a)
In CPU 1BusysfgnaHHighuuiingexecutiujiinCPUl)
56 Ki? In F.ipantion signal
To b* cimrwcifd to SI 2(CPU 11).
57 H3 in Primer Busy signal
LuW A'litll lIlC i^lilllCI i> IIVH opcuttil
58 Ki4 In Puntei connection identifying iignal.
Low when ihe pimtei is not connected.
59
60
hi 5
Ki6
In
In
(asset to recall signal
OM key input signal.
IC Pin-out
ic-toiiuBr
HJu*t i-«npui p-tsmvo NASI* iwlr )
|< in ip
1lltS mvn id )
'""14 13 18 II ID JK
nnnnnnn
lay k^J
,fPl„r^1„,
uul1iljul!ju
I*A'CM)
',('' 14 HI? tl io >
nnnnnnn
c>
:
UUUUlJUU(iNI'
n:*umn'
'Quiii AMD-Oft Klcti wit >
THOBflBP
(tfiwi </il«lridl »*ilili >
zS>^~
IN '«n °"1in
l%*qui *» in
MbUt™ 'I.N
c,„
13

4. BEFORE SERVICING
Disassembly procedure
1
.
Remove 2screws (i) and Iscrews (b).
1From (he sere* sule. leparate the upper cabinet item
the lower cabinet (they are latched togeihei at ihiee
points, A, Band C).
Repot ring procodure
].The bii'-i' of lK« at jihiwetic ftintod board will be
exposed after the removal of the lower cabinet. You
can check the arithmetic printed board from the back.
2. Replacement ol the CPU 11 is possible.
3. If the key primed board is to be checked, the arith-
metic piiiilcd buaid lies to be bent at aright angle
alter removing the screws )d) anc (el. Inspection ol
the CPU 1bpossible if the bizzrr Is removed after
lemming sciew(c).
4. The hey printed bontd can be dismounted by removing 9gcrrws (f> and 1screws <$> Tale care as you remove rtie printed
board, so y«.iilonl *plll iIn* he/ lops.
LkcI
Replacement of the LSI
1
.
Only «very fine soldering pencil should be used tot replacing the LSI.
2. Be sure to first remove the key primed board fiotn the uppei cabinet. If the LSI on the key primed boird is to be removed,
if the LSI sremoved while the key ptlnted board Is on the upper cibinci. there is apoistbUity of deforming the key
rubber with Ute heal of the wittering pencil.
?. Bcsurc tocut each pinof the defeciive K. a-
Measuring current consumption
tVwer source volnge 4.72V
Cuitem consumption:
After pressing the (IN key Under ftSQuA
After pressing the OFF key: Under 12(iA
5. CASSETTE TAPE &INTERFACE
For details of operation and connection, refer to -Jie Owner's Manual for the TRS-80 Pocket Computer
.
Notes on suitable recorders
While Radio Slack's CTK-SOA is the intended cassette Recorder, oiheri can b* used The following totes
1. Cassettes oi upciMecl tjpci can te used.
2. Mic input jack must lia« an oipui impedance of IK or leas, wiih asensitivity level ofat least -tmV.
3. Eaiphone output must Hjvb an output impedance of IOK or less and an outpu: level nf 1volt or more.
4. Allowable distortion is -1 %%. *ith frequency response from ?to 4k H?
wy Im> hclpl'ii
14

Recording
Recording method
6. CASSETTE OPERATION
cm
Recording formal of pi opam or reserve program
/
Data memory recording formal
1=Check sum code (after every ssteps or one data memory. I
2"8 steps of program or reserve program
3~fcnd code of recording.
4Tim gap. composed of all "Is", is inserted ai each line to (ill up Hie lull 80 steps, during which time the next SO steps of
data to be Input is peered in ll<c input buffet.
5-All *' Is" sre recorded for aperiod of about 6wCondf in order lo avoid non-record able area located at the beginning of the
tap« lit alto ii uwd for cuing of the recording head.
6=Program or reserve program nam* is frwlfcaied
7= File name
R=Data memory is mriicaied with r-iK rorle
9Area for one data memory.
Kecording method
Data "0" ind "1" are identified by changing The. frequency of the recording signal (F4"»
pata »_r :kiic
PATA JIkM/
lbi
15

Recording Mgrul IF4" )^ncralion circuit
f.- 4" »to CfliMiM Ininlacc utwttc mafclmon cucun
SlJ
HA
F4
jULfiiLTLriJiJirLrLrirLnnr
juuuifiniuui JUUUUUUUl
Reco.d.9^.."uinjijiriiijui^^
(F**>
Signal waveform at the tin* of recording
Whan awording *leml"r*k 1« h# recorded. SI 5kvet low and «8n»i F4 (clock pulse of -4kH/lis .iiiiput du-ini thai period.
When arecording ligral "0" is in be recorded. SIS is set high and K4 output is inhibited during that peiiod Uwhich time the
reverse sinnal of HA (clock pulse .»:' =2kHz) is carried on lite recording signal |
.
This signilh supplied to the MIC jack of !he tape recorder via the modulation circuit oJ the Cassette Interface.
Reproduction
Output signal from the EAR jack of the tape recorder is amplified and shaped mthe Schmitt circuit, to be input to CPU II
through Ki5 terminal ot CPU II.
CPU II
MS wwv-
h^>
Jl! M'U C»CV>T Arvpli'icr circuit
16

Remote control
The Cassette Inletfate will coltrci the RKMOTE Jack automatically (or record, playback and verify commands.
O.M7pF .V7«Ki«
rl
KIMOTI- O
(SU)
*feG
(iMI>
1'ne U'-452XPisa mono-siablemultmbraUHHo perform tiiggei and resel fraction! from the sirgle chip).
"A" outputs apulse which KitepenrifM rtn thp limp ointtaiH OfCR a' the tailing edge of the mput ctgnil, and "ti" outputs a
pulw which udependent on the tine constant of CR at the ruing edge of ihe input signal- The relay operates ON and OH-
accut ding to the curie nt flow 10 ihe coil, and bauivatfil when "A" bactive and deactivated when "B*' KtCUW.
Startup ol >,< .,.,-tt- .r"---"
su
/—
Tmmtoolion ul ihc c<»cirt jj-rdin.i
QA
\Activa'ian of the relay
i:«ictt* to itort runnng)
QR "LT
\Oeaetivacior ot the telev
(cassette to nopruonir-q)
17

Testing the Cassette Interface
1Writing. '«t data into the Pocket Computor
Firn enter tesi flats 10 check tlu Interfact,
No. Read in Display Remarks
^^^^"^
1ImodeHmodeI ^RESERVE Dhplcy RF-SF.RVF m.ide
2NEW NEW_ RESERVE
3ENTER >RESERVE
41shftI 2Z; _RESERVE
5P. »LSHFTJ?A» SHFT ;A<204> Z:P. tf»AT;A(204t RESERVE
6ir>Tl-K| Z; PRINT *TAT ;A(204) RfcSCRVE
71SHFTI XX. RESERVE —
8L#|SHFTi?AT|SHFT| ;A(204> X: 1. 3TAT; A(204)_ RESERVE
9int(k) X: INPUT =?AT;A(204) RESERVE
10 Sill 11|SK |RESERVE
I] AI204) :A(204| RESERVE
12 bNItK :A(204)
13 MODFJ ::.(->
14 MODEl >KlIN
15 SHFTl ISPi! =100 A(?041=lflO_ RUM
16 ENTER IKlIN 1U0
2. Checking the Cassette Interface
Amuires ihat iiep Ihut already been executed.
No. Read in Di iploy Remarks
1OFF
**
•Connect tiicCwseUc
Interface to the lape
recorder
3Connect the Pocket
Computer In the
Cassette Inurface.
4[TUT] 5* RUN Mako suic that RL'N »un
th# dKphy (u«fMfH»F|
ke/) '
5>RL'N Pimtijn Tjuc coiieciy.
16