Singer System ten User manual

SYSl1!M

lB'I

BY

SltlG~

CPU INSTRUCTIONS

MACHINE

REFERENCE

MANUAL

TABLE OF

CONTENTS

1

...

.INTROOUCTION

2

....

AOO

3

....

BRANCH

4

....

COMPARE

S

....

OIVIOE

6

....

EOIT

7

....

EXCHANGE

8

....

FORM NUMERIC

9

....

MOVE CHARACTER

IO

...

MOVE NUMERIC

11

...

MULTIPLY

12

...

READ

13

...

SUBTRACT

14

...

WRITE

Read

Write

Add

Subtract

Multiply

Divide

Move

Character

Move Numer

ic

Exchange

Edit

Form

Numeric

Compare

Branch

524

-

700504

-

M6

COPYRIGHT

C

1970

FRIDION

D,V,SION.

THIO

SINGER

COMPANY

INTRODUCTION TO CPU INSTRUCTIONS

INSTRUCTION FORMAT

1·1

Each

system

Ten

instruction

is

ten

characters

in

length.

Each

instruction

must

be

positioned

so

that

the

address

of

the

leftmost

character

is

a

multiple

of

10

(e.g.,

0,

10,

20,

30

....

etc.).

The

first

few

characters

of

an

instruction

as

they

appear

in

memory

have

the

following

format:

CHARACTER

2 3

[F3

LA

I

F2

A3

IFl

A2

BIT

7 5 4 3 2 1 7 5 4 3 2 7 5 4 3 2

Figure

Gl·l

Instruction Format . Sequential

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIDEN

O'VISIDN

THE

SINGER

COMPANY

INTRODUCTION TO CPU INSTRUCTIONS

Operation Code

Address Fields

1-2

A

more

useful

representation

of

instruction

format

is

achieved

by

giving

a

vertical

orientation

to

the

bits

of

a

character

as

is

done

below.

CHARACTER

l) 0 2 3 4 5 6 7 8 9

BIT

<:>

7

5

4

LA

A3

A2

A1

AO

LB

B3

B2

B1

BO

3

2

Figure G

1-2

Instruction Format -Parallel Blocking

In

this

representation

functionally

such

as

'F3

-

FO

also

have

a

close

spatial

relationship.

The

operation

code

of

an

instruction

is

specified

by

the

four

bit

binary

number

F =

F3F2F1FO,

e.g.,

an

ADD

instruction

is

indicated

when

F =

0100

and

a

COMPARE

when

F-1110.

Each

instruction

contains

two

These

are

generally

used

to

two

operands

which

participate

by

F.

Each

address

is

a

four

0000

and

9999

inclusive.

address

fields

A

and

B.

specify

the

addresses

of

the

in

the

operation

specified

digit

decimal

number

between

The

A-address

is

given

by

A3A2A1AO,

the

numeric

portion

(bits'

thru

4)

of

characters

1

thru

4.

The

8-address

is

given

by

83828180,

the

numeric

portion

of

characters

6

thru

9.

524

-

700504

-

Me

COPYRIGHT

C

11170

FRIIJE.N

D'VISIO

....

THE

SI~GER

COMPANY

INTRODUCTION

TO

CPU

INSTRUCTIONS

Addressing Mode

Indexing

1·3

An

instruction

address

may

refer

to

a

location

in

COMMON

or

in

partition.

AC

= 1

Means

the

A

address

refers

to

a

location

in

COMMON.

.

AC

=0

Means

the

A

address

refers

to

a

location

in

partition.

BC

= 1

Means

the

B

address

refers

to

a

location

in

COMMON.

BC

= 0

Means

the

B

address

refers

to

a

location

in

partition.

In

most

instructions

both

the

A

and

B

address

may

be

indexed.

Index

register

selection

for

the

A

address

is

determined

by

lA,

and

for

the

B

address

by

IB,

according

to

the

table

below:

IAl

lAO

IBl

IBO

0 0

0 1

1 0

1 1

Table

Gl-l

NO

INDEXING

INDEX

REGISTER

ONE

INDEX

REGISTER

TWO

INDEX

REGISTER

THREE

Index Addresses

524

-

700504

-

M6

COPYRIGHT

C

1970

FRIDEN

D'VISION

"THE

SINGER

COMPANY

INTRODUCTION TO CPU INSTRUCTIONS

Operand Lengths

1·4

Operand

lengths

are

explicitly

defined

using

LA

and

LB,

the

numeric

portion

of

characters

0

and

5

respectively.

Certain

instructions

use

LA

and

LB

differently

as

will

be

discussed

later.

LA--length,

in

number

of

characters

of

the

Operand-A.

LB--length,

in

number

of

characters

of

the

Operand-B.

524

-700504

-

M6

COPYRIGHT

C

1!l70

FRIDEN

D,V,SION

THE

SINGER

COMPANY

ADD INSTRUCTION

INSTRUCTION

FIELDS

The

Add

instruction

adds

the

operands

algebraically.

The

.operand

and

leaves

the

first

fields

do

not

overlap.

numeric

portions

sum

replaces

the

operand

unchanged

of

two

second

if

the

Machine Operation

Code

I

F---Binary

0100

(4).

Address Specification

I

A---Address

of

the

leftmost

position

of

Operand-A.

B---Address

of

the

leftmost

position

of

Operand-B.

Indexing Specification

IA--Index

register

for

determining

effective

address

of

Operand-A.

IB--Index

register

for

determining

effective

address

of

Operand-B.

Common Partition Specification

AC--If

AC

is

0,

A

is

address

in

controlling

partition.

If

AC

is

1 , A

is

address

in

Common.

BC--If

BC

is

0,

B

is

address

in

controlling

partition.

If

BC

is

1 , B

is

address

in

Common.

Length Specification

LA--Length

of

Operand-A.

LB--Length

of

Operand-B.

2

..

1

ADD INSTRUCTION

OPERAND FIELDS

Operand-A Address

Operand-B Address

Operand Lengths

OPERATION

General Description

2·2

If

IA

is

0,

then

A

is

the

effective

address.

If

IA

is

1,

2,

or

3,

the

corresponding

index

register

is

added

to

A

to

determine

the

effective

address

of

Operand-A.

If

AC

is

1,

the

effective

address

lies

in

Common.

If

IB

is

0,

then

B

is

the

effective

address.

If

IB

is

1,

2,

or

3,

the

corresponding

index

register

is

added

to

B

to

determine

the

effective

address

of

Operand-B.

If

BC

is

1,

the

effective

address

lies

in

Common.

If

LA

is

0,

the

length

of

Operand-A

is

10

characters.

If

LA

is

1

thru

9,

the

length

of

Operand-A

is

1

thru

9

characters.

If

LB

is

0,

the

length

of

Operand-B

is

10

characters.

If

LB

is

1

thru

9,

the

length

of

Operand-B

is

1

thru

9

characters.

The

add

operation

proceeds

from

right

to

left

starting

with

the

rightmost

characters

of

Operand-A

and

Operand-B.

Character

by

character,

the

algebraic

sum

is

developed

in

Operand-B.

If

Operand-A

is

shorter

than

Operand-B,

the

operation

proceeds

normally

until

Operand-A

is

exhausted.

After

that,

the

process

continues

in

similar

fashion

except

that

a

zero

character

is

automatically

substituted

every

time

the

adding

logic

calls

for

a

character

from

Operand-A.

In

effect,

Operand-A

is

given

enough

preceding

zeros

to

make

it

the

same

length

as

Operand-B.

If

Operand-A

is

longer

than

Operand-B,

addition

stops

after

the

leftmost

position

in

Operand-B

has

been

added.

The

remaining

positions

in

Operand-A

are

ignored,

and

do

not

affect

the

sum

or

the

Condition

Code.

524

-

700504

-

M6

COPYRIGHT

©

1970

ADD

INSTRUCTION

Condition Codes

The

algebraic

sign

of

the

sum

is

placed

in

bit-7

of

the

rightmost

position

of

Operand-B,

and

bit-5

is

turned

ON.

Except

for

the

rightmost

character,

the

other

zone

bits

of

Operand-B

are

unchanged.

Operand-A

is

unchanged

by

the

add

operation.

If

the

sum

exceeds

the

capacity

of

Operand-B,

a

carry-to-

the-left

from

the

leftmost

position

does

not

occur.

Condition

Code

4

is

set

to

indicate

the

overflow.

After

completion

of

the

Add

instruction.

1

==

Negati

ve,

non-zero

sum.

2

==

Zero

sum.

3

==

Positive,

non-zero

sum.

4 =

Overflow.

Execution Time (T) in Microseconds

T =

42.2

+

3.3

(LA) +

10.0

(LB)

+ TIX + TOO,

if

LA

is

equal

to

or

less

than

LB.

T =

42.2

+

11

(LA) +

12.

2

(LB)

+ TIX + TOO,

if

LA

is

greater

than

LB.

Key:

TIX

=

0.0,·

if

IA

and

IB

are

both

zero.

TIX

=

58.9,

if

IA

and

IB

are

both

non-zero.

TIX

=31.1,

if

IA

~

IB

is

non-zero.

TOO

=

0.0,

if

an

overdraft

does

not

occur.

TOO

=

10.0

(LB),

if

an

overdraft-OCcurs.

An

overdraft

will

always

occur

when

the

absolute

value

of

Operand-A

exceeds

the

absolute

value

of

Operand-B

~

they

have

~like

signs.

PROGRAMMING HINTS

O~erlapped

Operands

In

case

of

overlapped

operands,

the

result

is

unspecified.

2·3

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIOEN

D'VISION.

THE

SINGER

COMPANY

BRANCH INSTRUCTION

The

Branch

instruction

permits

departure

from

the

sequential

path

by

which

instructions

are

normally

executed.

Branching

can

be

unconditional,

it

can

depend

upon

the

current

status

of

the

Condition

Code,

or

it

can

depend

upon

signals

from

Input/Output

devices

requesting

service

from

the

CPU. A

variant

of

the

Branch

instruction

passes

control

to

a

subroutine

after

first

setting

the

return

address

at

which

the

main

program

will

be

resumed.

Execution

of

the

Branch

instruction

does

not

alter

the

Condition

Code.

INSTRUCTION

FIELDS

Machine Operation Code

I

F---Binary

1011

(11).

Address Specification

I

A---Address-A

B---Address-B

Indexing Specification

I

IA--Ignored.

IB--Ignored.

Branch

instructions

are

not

indexed.

Branch

instructions

are

not

indexed.

Common Partition Specification

Variant Specification

3·1

AC--If

AC

is

0,

If

AC

is

1 ,

BC--If

BC

is

0,

If

BC

is

1,

I

LA--A

digit

0-9.

LB--A

digit

0-6,

A

B

is

an

address

in

controlling

partition;

is

an

address

in

Common.

is

an

address

in

controlling

partition.

is

an

address

in

Common.

8,

9.

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIOlN

a'VISION

THE

SINGER

COMPANY

BRANCH INSTRUCTION

OPERATION

Order

of

Presentation

The

Branch

instruction

consists

of

several

variants.

The

LA

and

LB

instruction

fields

determine

which

variant

is

executed.

"Link"

(variant

6)

and

"Branch

on

Service

Request"

(variant

7)

require

that

the

entire

instruction

be

decoded.

These

variants

are

discussed

later

under

separate

headings.

The

other

variants

are

decoded

and

executed

a

half

instruction

at

a

time

and

are

most

conveniently

discussed

as

a

group

in

the

Variants

0,

1,

2,

3, 4,

5,

8,

9

3·2

The

first

five

characters

of

the

instruction

are

fetched.

LA

is

examined.

If

a

branch

is

required,

control

passes

to

Address-A,

and

the

right

half

of

the

instruction

is

ignored.

If

a

branch

is

not

required

in

the

left

half

of

the

instruction,

the

right

half

is

fetched.

LB

is

examined.

If

a

branch

is

required,

control

passes

to

Address-B.

If

a

branch

is

not

required,

execution

continues

with

the

instruction.

The

following

table

shows

the

values

which

LA

and

LB

may

assume.

Beside

each

variant

number

is

the

meaning

applied

by

the

ACU.

Variant

6

and

variant

7

are

purposely

omitted.

They

are

discussed

under

"Link"

and

"Branch

on

Service

Request".

Variant

0---00

not

branch

("no

operation").

Variant

1---Branch

if

Condition

Code

is

1.

Variant

2---Branch

if

Condition

Code

is

2.

Variant

3---Branch

if

Condition

Code

is

3.

Variant

4---Branch

if

Condition

Code

is

4.

Variant

5---Branch,

unconditionally.

Variant

8---Branch

and

switch

partitions,

unconditionally.

Variant

9---00

not

branch

("no

operation").

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIOEN

DIVISlON.

"THE

SINGER

COMPANY

BRANCH INSTRUCTION

Partition Switching

If

a

Branch

instruction

does

not

require

execution

simply

continues

with

the

a

branch,

sequential

If

the

host

partition

has

been

in

continuous

control

for

more

than

37.5

milliseconds

when

a

branch

is

required,

the

branch

is

taken

but

the

execution

of

the

instruction

at

the

branch

address

is

postponed

and

control

passes

to

the

When

control

returns,

execution

resumes

at

the

branch

address.

If

the

branch

is

caused

by

variant

8

("Branch

and

switch,

unconditionally"),

the

branch

is

taken

but

the

execution

of

the

instruction

at

the

branch

address

is

postponed

and

control

passes

to

the

even

though

37.5

milliseconds

have

not

elapsed.

LINK

-BRANCH VARIANT 6

LA--Must

be

6.

LB--May

be

0

thru

5,

8,

or

9.

If

LB

is

0

or

9,

no

link

occurs;

control

simply

passes

to

the

If

LB

is

1-Q,

the

corresponding

Condition

Code

is

tested.

If

the

specified

Condition

Code

is

ON,

the

link

operation

is

performed.

Otherwise,

control

simply

passes

to

the

If

LB

is

5

or

8,

the

link

operation

is

performed,

unconditionally.

Return Address/Start Address

The

address

of

the

(return

address)

is

inserted

into

the

numerical

portion

of

the

four

position

field

starting

at

Address-A.

The

zone

portions

of

the

three

left

character

positions

are

unchanged.

Bit-5

of

the

rightmost

position

is

set

to

1.

Bit-7

is

set

to

1

if

the

return

address

is

in

common;

it

is

set

to

0

if

the

return

address

is

in

partition.

Control

then

passes

to

Address-B

(start

address).

BRANCH

ON

SERVICE

REQUEST

-BRANCH VARIANT 7

3·3

I

LA--Must

be

7.

LB--Must

be

0

or

9.

COPYRIGHT

C 110170

524

-

700504

-

M6

FRIOEN

01

VI

SION'

THE

SINGER

COMPANY

I

UCTION

CC

:?

I;,..'''.'

T=.7.·.

-

..

_._

...

:._-

...•

:

··~X~'

~DD

MINUS

ZERO

PLUS

OVERFLOW

~RANCH

/QOND

ITlONAl

---

(gOMPARE A

IS

LESS

EQUAL

A IS

GREATER

A

NOT

LESS

(Q]IVIDE

MINUS

ZERO

PLUS

OVERFLOW

~DIT

MINUS

ZERO

PLUS

---

E~CHANGE

---

2

ALWAYS

SET

---

fE)ORM

~UMERIC

FIELD

MINUS

ZERO

PLUS

OVERFLOW

~OVE

(gHARACTER

---

2

ALWAYS

SET

---

~OVE

~UMERIC

---

2

ALWAYS

SET

--- ---

~Ul

TlPlY

MINUS

ZERO

PLUS

---

~EAD

ERROR

NORMAL

FLAG

FAULT

~UBTRACT

MINUS

ZERO

PLUS

OVERFLOW

~RITE

ERROR

NORMAL

FLAG

FAULT

Table G3·1 Condition

Code

Settings

524

-

700504

-

Me

BRANCH INSTRUCTION

Operation . Storing Device Number

Condition Codes

Each

IOC

continually

polls

the

input/output

devices

attached

to

it

to

see

if

a

device

has

signalled

a

request

for

service.

If

the

IOC

encounters

such

a

signal,

further

polling

for

service

requests

is

temporarily

discontinued,

and

the

device

number

is

held

in

a

counter

until

the

CPU

executes

"Branch

on

Service

Request".

"Branch

on

Service

Request"

causes

the

counter

to

be

stored

in

the

numeric

portion

of

the

character

position

pOinted

to

by

Address-A.

Control

then

passes

to

Address-B.

Polling

resumes

with

the

device

number

(or

0,

if

the

requesting

device

was

9

>.

If

the

IOC

is

holding

no

such

request

for

service,

"Branch

on

Service

Request"

has

no

effect.

Execution

continues

with

the

instruction.

I

Condition

Codes

are

unchanged

by

the

Branch

instruction.

Execution Time (T)

in

Microseconds

T

=37.8

for

no

branch.

T =

27.8

for

branch

to

Address-A.

T=44.4

for

branch

to

Address-B

(except

variants

6,7)

•

T=75.5

for

"Link"

(variant

6)

.

T=51.1

for

"Branch

on

Service

Request"

(variant

7).

PROGRAMMING

HINTS

3-4

I

Since

each

instruction

(with

the

exception

of

Branch)

sets

the

condition

code,

it

is

necessary

to

test

the

condition

code

immediately

after

the

performance

of

an

operation.

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIOE.N

DIVISION

"THE

SINGER

COMPANY

COMPARE INSTRUCTION

I

The

Compare

instruction

compares

two

fields

and

sets

Condition

Code

to

indicate

the

relation

between

them.

the

INSTRUCTION

FIELDS

Machine Operation

Code

F---Binary

1110

(14).

Address Specification

I

A---Address

of

the

leftmost

position

of

Operand-A.

B---Address

of

the

leftmost

position

of

Operand-B.

Indexing Specification

IA--Index

register

for.

determining

effective

address

of

Operand-A.

IB--Index

register

for

determining

effective

address

of

Operand-B.

Common Partition Specification

Length Specification

4-1

AC--If

AC

is

0,

A

is

address

in

controlling

partition.

If

AC

is

1 ; A

is

address

in

Common.

BC--If

BC

is

0,

B

is

address

in

controlling

partition.

If

BC

is

1 , B

is

address

in

Common.

LA--Tens

position

of

length

of

both

Operand-A

and

Operand-

B.

LB--Units

position

of

length

of

both

Operand-A

and

Operand-

B.

524

-700504

-

M6

COPYRI

GHT

©

1970

FRIOEN

0,

VI

SION

THE

SINGER

COMPANY

COMPARE INSTRUCTION

OPERAND FIELDS

Operand-A Address

Operand-B Address

Operand Lengths

OPERATION

General Description

4-2

If

IA

is

0,

then

A

is

the

effective

address.

If

IA

is

1,

2,

or

3,

the

corresponding

index

register

is

added

to

A

to

determine

the

effective

address

of

Operand-A.

If

AC

is

1,

the

effective

address

lies

in

Common.

If

IB

is

0,

then

B

is

the

effective

address.

If

IB

is

1,

2,

or

3,

then

corresponding

index

register

is

added

to

B

to

determine

the

effective

address

of

Operand-B.

If

BC

is

1,

the

effective

address

lies

in

Common.

Operand-A

and

Operand-B

are

equal

in

length.

10LA +

LB

=

Lengths

of

operands

for

the

Compare

instruction.

If

10LA +

LB=OO,

100

is

the

length

of

the

operands.

The

compare

operation

proceeds

from

left

to

right

starting

with

the

leftmost

character

of

Operand-A

and

Operand-B.

Character

by

character,

the

values

of

Operand-A

and

Operand-B

are

compared

until

a

difference

is

found

or

the

rightmost

position

has

been

compared.

When

the

characters

differ,

Condition

Code

1,

or

3

and

4

is

set

ON

(indicating

that

Operand-A

is

smaller

or-larger

than

Operand-B),

and

the

operation

is

complete.

If

the

characters

are

identical,

and

there

are

more

positions

to

be

compared,

the

comparison

is

repeated

for

the

on

the

right.

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIDEN

DIVISION

THE

SINGER

COMPANY

COMPARE INSTRUCTION

Condition Codes:

When

the

characters

are

identical

and

there

are

no

more

positions

to

be

compared,

Condition

Codes

2

and

4

are

set

ON.

Operand-A

and

Operand-B

are

unchanged

by

the

operation.

compare

When

Condition

Code

3

or

2

is

set

ON,

Condition

4

is

also

set

ON.

1

1,

if

Operand-A

is

less

than

Operand-B.

2

and

4,

if

Operand-A

and

Operand-B

are

identical.

3

and

4,

if

Operand-A

is

greater

than

Operand-B.

Execution Time (T)

is

Microseconds

T =

40.0

+

7.78

(10LA

+ LB)

.+

TIX,

if

the

operands

are

identical.

T=

48.9

+

7.78

(y)

+

TIX,

if

the

operands

differ.

Key:

Y =

the

number

of

equal

compar

isons.

TIX =

0.0,

if

IA

and

IB

are

both

zero.

TIX

=58.9,

if

IA

and

IB

are

both

non-zero.

TIX

=31.1,

if

IA

or

IB

is

non-zero.

PROGRAMMING HINTS

Character Values

Sorting

4·3

The

reader

is

referred

to

the

Table

G4-1

entitled

"Characters

Arranged

in

Sequence

of

Value."

In

the

first

column

under

"Character

Code"

are

the

internal

codes

of

each

character

used

in

the

Model

20

Processor.

In

the

second

column

under

"Character"

are

the

corresponding

characters.

The

table

can

be

used

to

resolve

uncertainties

as

to

which

of

two

characters

the

Compare

instruction

considers

to

be

the

larger.

A

character

is

considered

greater

than

the

other

characters

which

precede

it

in

the

table.

It

is

less

than

those

which

follow

it.

A

prinCipal

use

of

the

Compare

instruction

is

in

sorting

data.

The

programmer

is

reminded

that

the

units

position

of

a

negative

numeric

field

is

coded

with

zone

bit-7

ON.

(If

the

digit

were

positive,

bit-7

would

be

OFF.)

Thus,

in

a

compare

operation,

a

negative

digit

is

of

greater

value

than

any

positive

digit.

524

-

700504

-

M6

COPYRI

G'" ©

1970

FRIOEN

01

VI

SION

THE

SINGER

COMf"ANY

b7

0

I

1

I

1

Table

G4·1

Uldrd(.ter

Lode

b~

u4

u)

Uz

0 0 0 0

0 0 0 I

0 0 I 0

0 0 I I

0 0 1 I

0 I 0 0

0 I 0 I

0 I I 0

0 I I I

0 1 1 I

1 0 0 0

I 0 0 1

1 0 0 1

1 0 1 0

I 0 I 0

I 0 1 I

I 0 I I

I I 0 0

I I 0 I

I 1 0 1

I I I 0

I I 1 0

I I I I

0 0 0 0

0 0 0 I

0 0 I 0

0 0 I I

0 I 0 0

0 I 0 I

0 I I 0

0 I I I

I 0 0 0

1 0 0 1

I 0 0 1

1 0 I 0

1 0 1 0

I 0 1 I

1 0 I 1

1 1 0 0

I 1 0 0

1 1 0 1

1 I 1 0

1 1 I 0

I 1 1 1

1 1 1 1

ul

0

I

U

I

0

I

0

I

0

I

0

I

0

I

0

1

0

I

0

1

0

1

0

I

0

I

0

1

0

I

0

I

0

I

0

I

0

I

0

I

0

I

0

I

0

I

0

I

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Chdrdder

SP

!

,

$

%

&

(

)

.

+

I

0

1

2

)

4

5

6

7

8

9

;

?

@

A

B

C

D

[

F

G

H

I

J

K

L

H

N

0

P

Q

R

S

T

U

V

W

X

y

Z

I

\

}

.-

CH~RACTE

RS

ARRANr.r

0

I~

\f()IJ(NCE

or

VALUE

Sp.!ce

Exclamation

Point

Quota t i on

Ha

rk

NuRiJer

Si

gn

llo11ar

~ign

Pen:ent

Aqlersand

Prime.

Apos t

rophe

Left

Parenthes

is

Right

Parenthes

is

Asterisk

Plus

Sign

Comna

Hi

nus

Sign.

Hyphen

Period,'

Decimal

Point

Slash

Zero

One

Two

Three

Four

Five

Six

Seven

Eight

Nine

Colon

Semicolon

Less-than

Sign

[qual

Sign

Greater-than

Sign

Question

Hark

At

Sign

Openi

n9

Bracket

Reverse

S

hnt

ClosIng

Brac~et

Ci

rculllflex

Onderl

ine

Characters

Arranged

in

Sequence

of

Value

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIDEN

D,V'SION

THE

SINGLRCOMPANY

DIVIDE INSTRUCTION

I

The

Divide

instruction

computes

the

algebraic

quotient

(and

remainder)

of

two

operands.

INSTRUCTION

FIELDS

Machine Operation Code

Address

Specification

Indexing Specification

F---Binary

0101

(5).

A---Address

of

the

leftmost

position

of

Operand-A.

B---Address

of

the

leftmost

position

of

Operand-B

(dividend)

Address

of

the

quotient.

IA--Index

register

for

determining

effective

address

of

Ol>erand-A.

IB--Index

register

for

determining

effective

address

of

Operand-B.

Common Partition Specification

AC--If

AC

is

0,

A

is

an

address

in

controlling

partition.

If

AC

is

1 , A

is

an

address

in

Common.

BC--If

BC

is

0,

B

is

an

address

in

controlling

partition.

If

BC

is

1 , B

is

an

address

in

Common.

Length Specification

LA--Length

of

Operand-A

(divisor).

LB--Length

of

the

quotient.

LA

+

LB--Length

of

Operand-B

(dividend).

5·1

524

-

700504

-

M6

COPYRIGHT

C

1970

FRtOEN

01

VI

SION.

·THE

SINGER

COMPANY

DIVIDE INSTRUCTION

OPERAND FIELDS

Operand-A Address

Operand-B Address

Operand Lengths

OPERATION

General Description

5-2

If

IA

is

0,

then

A

is

the

effective

address_

If

IA

is

1,

2,

or

3,

the

corresponding

index

register

is

added

to

A

to

determine,

the

effective

a4dress

of

Operand-A.

If

AC

is

1,

the

effective

address

lies

in

Common.

If

IB

is

0,

then

B

is

the

effective

address.

If

IB

is

1,

2,

or

3,

the

corresponding

index

register

is

added

to

B

to

determine

the

effective

address

of

Operand-B.

If

BC

is

1,

the

effective

address

lies

in

Common.

If

LA

is

0,

the

length

of

Operand-A

is

10

characters.

If

LA

is

1

thru

9,

the

length

of

Operand-A

is

1

thru

9

characters.

If

LB

is

0,

the

length

of

Quotient

is

10

characters.

If

LB

is

1

thru

9,

the

length

of

Quotient

is

1

thru

9

characters.

LA

+

LB

is

the

length

of

Operand-B

(dividend).

Operand-A

is

the

divisor.

The

dividend

begins

at

the

B

address

and

contains

LB

+

LA

positions.

At

the

end

of

the

operation,

the

quotient

occupies

the

leftmost

LB

positions

of

the

dividend

field,

and

the

remainder

occupies

the

rightmost

LA

positions

of

the

dividend

field.

If

the

divisor

and

the

dividend

differ

in

sign,

bit-7

of

the

quotient

is

turned

ON

to

indicate

a

negative

quotient.

If

the

signs

are"

alike,

bit-7

is

turned

OFF

to

indicate

a

positive

quotient.

Bit-5

is

turned

ON

for

all

positions

of

the

quotient;

bit-7

is

turned

OFF

for

all

positions

except

the

rightmost.

524

-

700504

-

M6

COPYRIGHT

©

1970

FRIOEN

01

VI

SION

THE

SINGER

COMPANY

Singer SYSTEM TEN User manual

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