Singer SYSTEM TEN User manual

SYSl1!M lB'I BY SltlG~
CPU INSTRUCTIONS
MACHINE
REFERENCE MANUAL

TABLE OF CONTENTS
1 ... .INTROOUCTION
2 .... AOO
3 .... BRANCH
4 .... COMPARE
S .... OIVIOE
6 .... EOIT
7 .... EXCHANGE
8 .... FORM NUMERIC
9 .... MOVE CHARACTER
IO ... MOVE NUMERIC
11 ... MULTIPLY
12 ... READ
13 ... SUBTRACT
14 ... WRITE
Read
Write
Add
Subtract
Multiply
Divide
Move Character
Move Numer ic
Exchange
Edit
Form Numeric
Compare
Branch
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COPYRIGHT C 1970 FRIDION D,V,SION. THIO SINGER COMPANY

INTRODUCTION TO CPU INSTRUCTIONS
INSTRUCTION FORMAT
1·1
Each system Ten instruction is ten characters in length.
Each instruction must be positioned so that the address of
the leftmost character is a multiple of 10 (e.g., 0, 10,
20, 30 .... etc.). The first few characters of an
instruction as they appear in memory have the following
format:
CHARACTER
2 3
[F3
LA
I F2
A3
IFl
A2
BIT
7 5 4 3 2 1 7 5 4 3 2 7 5 4 3 2
Figure Gl·l
Instruction Format . Sequential
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COPYRIGHT © 1970 FRIDEN O'VISIDN THE SINGER COMPANY

INTRODUCTION TO CPU INSTRUCTIONS
Operation Code
Address Fields
1-2
A more useful representation of instruction format is
achieved by giving a vertical orientation to the bits of a
character as is done below.
CHARACTER l) 0 2 3 4 5 6 7 8 9 BIT
<:>
7
5
4
LA
A3
A2
A1
AO LB B3 B2 B1
BO
3
2
Figure G 1-2 Instruction Format -Parallel Blocking
In this representation functionally related bits such as 'F3
-
FO also have a close spatial relationship.
The operation code of an instruction is specified by the
four bit binary number F = F3F2F1FO, e.g., an ADD
instruction is indicated when F = 0100 and a COMPARE when
F-1110.
Each instruction contains two
These are generally used to
two operands which participate
by F. Each address is a four
0000 and 9999 inclusive.
address fields A and B.
specify the addresses of the
in the operation specified
digit decimal number between
The A-address is given by A3A2A1AO, the numeric portion
(bits' thru 4) of characters 1 thru 4.
The 8-address is given by 83828180, the numeric portion of
characters 6 thru 9.
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COPYRIGHT C 11170
FRIIJE.N D'VISIO .... THE SI~GER COMPANY

INTRODUCTION TO CPU INSTRUCTIONS
Addressing Mode
Indexing
1·3
An instruction address may refer to a location in COMMON or
in partition.
AC = 1 Means
the
A
address
refers to
a location
in COMMON.
. AC =0
Means
the
A address
refers to
a location
in
partition.
BC = 1
Means
the
B address
refers to a location
in COMMON.
BC = 0
Means
the
B address
refers to a location
in
partition.
In most instructions both the A and B address may be
indexed. Index register selection for the A address is
determined by lA, and for the B address by IB, according to
the table below:
IAl lAO
IBl
IBO
0 0
0 1
1 0
1 1
Table Gl-l
NO INDEXING
INDEX REGISTER ONE
INDEX REGISTER TWO
INDEX REGISTER THREE
Index Addresses
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COPYRIGHT C 1970 FRIDEN D'VISION "THE SINGER COMPANY

INTRODUCTION TO CPU INSTRUCTIONS
Operand Lengths
1·4
Operand lengths are explicitly defined using LA and LB, the
numeric portion of characters 0 and 5 respectively.
Certain instructions use LA and LB differently as will be
discussed later.
LA--length, in number of characters of the Operand-A.
LB--length, in number of characters of the Operand-B.
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COPYRIGHT C 1!l70 FRIDEN D,V,SION THE SINGER COMPANY

ADD INSTRUCTION
ADD INSTRUCTION
INSTRUCTION
FIELDS
The Add instruction adds the
operands algebraically. The
.operand and leaves the first
fields do not overlap.
numeric portions
sum replaces the
operand unchanged
of two
second
if the
Machine Operation Code
I F---Binary 0100 (4).
Address Specification
I
A---Address of the leftmost position of Operand-A.
B---Address of the leftmost position of Operand-B.
Indexing Specification
IA--Index register for determining effective address of
Operand-A.
IB--Index register for determining effective address of
Operand-B.
Common Partition Specification
AC--If
AC is
0, A is
address in
controlling
partition.
If AC
is
1 , A
is
address
in
Common.
BC--If BC
is 0, B
is
address
in
controlling
partition.
If BC
is
1 , B
is
address
in
Common.
Length Specification
LA--Length of Operand-A.
LB--Length of Operand-B.
2 .. 1

ADD INSTRUCTION
OPERAND FIELDS
Operand-A Address
Operand-B Address
Operand Lengths
OPERATION
General Description
2·2
If IA is 0, then A is the effective address.
If IA is 1, 2, or 3, the corresponding index register is
added to A to determine the effective address of Operand-A.
If AC is 1, the effective address lies in Common.
If IB is 0, then B is the effective address.
If IB is 1, 2, or 3, the corresponding index register is
added to B to determine the effective address of Operand-B.
If BC is 1, the effective address lies in Common.
If LA is 0, the length of Operand-A is 10 characters.
If LA is 1 thru 9, the length of Operand-A is 1 thru 9
characters.
If LB is 0, the length of Operand-B is 10 characters.
If LB is 1 thru 9, the length of Operand-B is 1 thru 9
characters.
The add operation proceeds from right to left starting with
the rightmost characters of Operand-A and Operand-B.
Character by character, the algebraic sum is developed in
Operand-B.
If Operand-A is shorter than Operand-B, the operation
proceeds normally until Operand-A is exhausted. After
that, the process continues in similar fashion except that
a zero character is automatically substituted every time
the adding logic calls for a character from Operand-A. In
effect, Operand-A is given enough preceding zeros to make
it the same length as Operand-B.
If Operand-A is longer than Operand-B, addition stops after
the leftmost position in Operand-B has been added. The
remaining positions in Operand-A are ignored, and do not
affect the sum or the Condition Code.
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COPYRIGHT © 1970

ADD INSTRUCTION
Condition Codes
The algebraic sign of the sum is placed in bit-7 of the
rightmost position of Operand-B, and bit-5 is turned ON.
Except for the rightmost character, the other zone bits of
Operand-B are unchanged. Operand-A is unchanged by the add
operation.
If the sum exceeds the capacity of Operand-B, a carry-to-
the-left from the leftmost position does not occur.
Condition Code 4 is set to indicate the overflow.
After completion of the Add instruction.
1 == Negati ve, non-zero sum.
2 == Zero sum.
3 == Positive, non-zero sum.
4 = Overflow.
Execution Time (T) in Microseconds
T = 42.2 + 3.3 (LA) + 10.0 (LB) + TIX + TOO, if LA is equal
to or less than LB.
T =
42.2 + 11 (LA) + 12. 2 (LB) + TIX + TOO, if LA is
greater than LB.
Key:
TIX = 0.0,· if IA and IB are both zero.
TIX = 58.9, if IA and IB are both non-zero.
TIX =31.1, if IA ~ IB is non-zero.
TOO = 0.0, if an overdraft does not occur.
TOO = 10.0 (LB), if an overdraft-OCcurs.
An overdraft will always occur when the absolute
value of Operand-A exceeds the absolute value of
Operand-B ~ they have ~like signs.
PROGRAMMING HINTS
O~erlapped Operands
In case of overlapped operands, the result is
unspecified.
2·3
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COPYRIGHT © 1970 FRIOEN D'VISION. THE SINGER COMPANY

BRANCH INSTRUCTION
BRANCH INSTRUCTION
The Branch instruction permits departure from the
sequential path by which instructions are normally
executed. Branching can be unconditional, it can depend
upon the current status of the Condition Code, or it can
depend upon signals from Input/Output devices requesting
service from the CPU. A variant of the Branch instruction
passes control to a subroutine after first setting the
return address at which the main program will be resumed.
Execution of the Branch instruction does not alter the
Condition Code.
INSTRUCTION FIELDS
Machine Operation Code
I F---Binary 1011 (11).
Address Specification
I
A---Address-A
B---Address-B
Indexing Specification
I
IA--Ignored.
IB--Ignored.
Branch instructions are not indexed.
Branch instructions are not indexed.
Common Partition Specification
Variant Specification
3·1
AC--If
AC is
0,
If AC
is 1 ,
BC--If
BC is
0,
If
BC
is
1,
I
LA--A digit 0-9.
LB--A digit 0-6,
A
A
B
B
is an address in
controlling
partition;
is an address in
Common.
is an address in
controlling partition.
is an address in
Common.
8, 9.
524 - 700504 - M6
COPYRIGHT © 1970 FRIOlN a'VISION THE SINGER COMPANY