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Sony ICX418AKL User manual

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– 1 – E01503B41
Sony reserves the right to change products and specifications without prior notice.This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX418AKL
20 pin DIP (Cer-DIP)
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX418AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX038DNA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX038DNA and has the same drive conditions.
Features
•High sensitivity (+6.0dB compared with the ICX038DNA)
•Low smear (–5.0dB compared with the ICX038DNA)
•High D range (+2.0dB compared with the ICX038DNA)
•High S/N
•High resolution and low dark current
•Excellent antiblooming characteristics
•Ye, Cy, Mg, and G complementary color mosaic filters on chip
•Continuous variable-speed shutter
•Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)
•Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
•Horizontal register: 5V drive
Device Structure
•Interline CCD image sensor
•Optical size: Diagonal 8mm (Type 1/2)
•Number of effective pixels: 768 (H) ×494 (V) approx. 380K pixels
•Total number of pixels: 811 (H) ×508 (V) approx. 410K pixels
•Chip size: 7.40mm (H) ×5.95mm (V)
•Unit cell size: 8.4µm (H) ×9.8µm (V)
•Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
•Substrate material: Silicon
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 11 40
3
– 2 –
ICX418AKL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products.You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor.You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
•The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
•You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products.You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
•Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
•Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
Export Control
•If the Products are controlled items under the export control laws or regulations of various countries, approval
may be required for the export of the Products under the said laws or regulations.You should be responsible
for compliance with the said laws or regulations.
No License Implied
•The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise. Sony
will not assume responsibility for any problems in connection with your use of such information or for any
infringement of third-party rights due to the same.It is therefore your sole legal and financial responsibility to
resolve any such problems and infringement.
Governing Law
•This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this
Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first
instance.
Other ApplicableTerms and Conditions
•The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.
– 3 –
ICX418AKL
Block Diagram and Pin Configuration
(Top View)
11 12 13 14 15 16 17 18 19 20
Note) : Photo sensor
NC
VDSUB
NC
GND
GND
RD
φRG
NC
Hφ1
Hφ2
10 9 8 7 6 5 4 3 2 1
VOUT
VDD
GND
VL
Vφ1
GND
φSUB
Vφ2
Vφ3
Vφ4
Note)
Horizontal Register
Vertical Register
Cy
Cy
Mg
G
Cy
Mg
Cy
Cy
Mg
G
Cy
Mg
Ye
Ye
G
Mg
Ye
G
Ye
Ye
G
Mg
Ye
G
Pin Description
Pin No. Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol Description
Vφ4
Vφ3
Vφ2
φSUB
GND
Vφ1
VL
GND
VDD
VOUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
GND
Vertical register transfer clock
Protective transistor bias
GND
Output circuit supply voltage
Signal output
Symbol Description
NC
VDSUB
NC
GND
GND
RD
φRG
NC
Hφ1
Hφ2
Substrate bias circuit supply voltage
GND
GND
Reset drain bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
– 4 –
ICX418AKL
Absolute Maximum Ratings
Item
Substrate clock φSUB – GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2– Vφ4
φRG – GND
φRG – φSUB
VL– φSUB
Pins other than GND and φSUB – VL
Storage temperature
Operating temperature
–0.3 to +50
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
Ratings Unit Remarks
∗1+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
VDD, VRD, VDSUB, VOUT – GND
VDD, VRD, VDSUB, VOUT – φSUB
Vφ1, Vφ2, Vφ3, Vφ4– GND
Vφ1, Vφ2, Vφ3, Vφ4– φSUB
– 5 –
ICX418AKL
DC Characteristics
Output circuit supply current
Item IDD
Symbol 5.0
Min. Unit RemarksTyp. Max. mA10.0
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
∗1VLsetting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item VDD
VRD
VL
VDSUB
φSUB
Symbol 15.0
15.0
∗1
15.0
∗2
Min. V
V
V
Unit RemarksTyp. Max.
14.55
14.55
14.55
15.45
15.45
15.45
VRD = VDD
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
∗3VLsetting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗4Connect to GND or leave open.
∗5The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a
special code.When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage.The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
VSUB code — one character indication
Code and optimal setting correspond to each other as follows.
Item VDD
VRD
VL
VDSUB
VSUB
∆VSUB
Symbol 15.0
15.0
∗3
∗4
Min. V
V
V
%
Unit RemarksTyp. Max.
14.55
14.55
6.0
–3
15.45
15.45
14.0
+3
VRD = VDD
∗5
∗5
<Example> "L" →VSUB = 9.0V
VSUB code
Optimal setting
f
6.5
G
7.0
h
7.5
J
8.0
K
8.5
L
9.0
m
9.5
N
10.0
P
10.5
Q
11.0
S
12.0
U
13.0
V
13.5
W
14.0
R
11.5
T
12.5
E
6.0
– 6 –
ICX418AKL
Clock Voltage Conditions
∗1Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage∗1
Substrate clock voltage
Item
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
| VVH1 – VVH2 |
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VRGL
VφRG
VRGLH – VRGLL
VφSUB
Symbol
14.55
–0.05
–0.2
–9.6
8.3
–0.25
–0.25
4.75
–0.05
4.5
23.0
Min.
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Remarks
Reset gate clock
voltage
Item
VRGL
VφRG
Symbol
4
4
Waveform
diagram Remarks
15.0
0
0
–9.0
9.0
5.0
0
∗1
5.0
24.0
Typ.
15.45
0.05
0.05
–8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
Max. Unit
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
–0.2
8.5
Min.
0
9.0
Typ.
0.2
9.5
Max. Unit
V
Vp-p
– 7 –
ICX418AKL
Horizontal transfer clock equivalent circuitVertical transfer clock equivalent circuit
Hφ1Hφ2
CφH1 CφH2
CφHH
Vφ
1
Cφ
V12
Vφ
2
Vφ
4
Vφ
3
Cφ
V34
Cφ
V23
Cφ
V41
Cφ
V1
Cφ
V2
Cφ
V4
Cφ
V3
R
GND
R
4
R
1
R
3
R
2
Clock Equivalent Circuit Constant
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφH1
CφH2
CφHH
CφRG
CφSUB
R1, R3
R2, R4
RGND
Symbol
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Item Min. 2700
2700
820
330
100
91
47
11
680
91
100
68
Typ. Max. pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Unit Remarks
– 8 –
ICX418AKL
Drive ClockWaveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn – VVLn (n = 1 to 4)
100%
90%
10%
0% tr tf 0V
twh
φM
2
φM
V
VT
VVH1 VVHH
VVHL
VVH
VVLH
VVL1
VVLL
VVHL
VVHH
VVL
VVHH VVH
VVLH
VVLL
VVL
VVHL
VVL3
VVHL
VVH3
VVHH
VVH2
VVHH
VVHH
VVHL VVHL
VVH
VVLH
VVL2
VVLL
VVL
VVH
VVL
VVHL
VVLH
VVLL
VVHL
VVH4
VVHH VVHH
VVL4
Vφ1Vφ3
Vφ2Vφ4
– 9 –
ICX418AKL
(3) Horizontal transfer clock waveform
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the period twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
10%
0%
VSUB tr tftwh
φM
2
φM
VφSUB
tr twh tf
90%
10%
twl
Vφ
H
V
HL
Point A
twl
VφRG
VRGH
VRGL
VRGLH
RG waveform
VRGLL
Hφ1waveform
twhtr tf
+2.5V
VRGLm
VRGL + 0.5V
– 10 –
ICX418AKL
Clock Switching Characteristics
∗1When vertical transfer clock driver CXD1267AN is used.
∗2tf ≥tr – 2ns.
∗3The overlap period for twh and twl of horizontal transfer clocks Hφ1and Hφ2is two.
Min. two
Typ. Max.
16 20
Unit
ns
RemarksItem
Horizontal transfer clock
Symbol
Hφ1, Hφ2∗3
Min. twh
Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
twl tr tf
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
Unit
µs
ns
ns
µs
ns
µs
Remarks
During readout
∗1
∗2
When draining
charge
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1, Vφ2,
Vφ3, Vφ4
Hφ
Hφ1
Hφ2
φRG
φSUB
Horizontal
transfer clock
0.5
During
imaging
During
parallel-serial
conversion