Sony ICX418AKL User manual

– 1 – E01503B41
Sony reserves the right to change products and specifications without prior notice.This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX418AKL
20 pin DIP (Cer-DIP)
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX418AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX038DNA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX038DNA and has the same drive conditions.
Features
•High sensitivity (+6.0dB compared with the ICX038DNA)
•Low smear (–5.0dB compared with the ICX038DNA)
•High D range (+2.0dB compared with the ICX038DNA)
•High S/N
•High resolution and low dark current
•Excellent antiblooming characteristics
•Ye, Cy, Mg, and G complementary color mosaic filters on chip
•Continuous variable-speed shutter
•Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)
•Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
•Horizontal register: 5V drive
Device Structure
•Interline CCD image sensor
•Optical size: Diagonal 8mm (Type 1/2)
•Number of effective pixels: 768 (H) ×494 (V) approx. 380K pixels
•Total number of pixels: 811 (H) ×508 (V) approx. 410K pixels
•Chip size: 7.40mm (H) ×5.95mm (V)
•Unit cell size: 8.4µm (H) ×9.8µm (V)
•Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
•Substrate material: Silicon
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 11 40
3

– 2 –
ICX418AKL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products.You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor.You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
•The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
•You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products.You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
•Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
•Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
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•If the Products are controlled items under the export control laws or regulations of various countries, approval
may be required for the export of the Products under the said laws or regulations.You should be responsible
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No License Implied
•The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
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will not assume responsibility for any problems in connection with your use of such information or for any
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•This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this
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instance.
Other ApplicableTerms and Conditions
•The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.

– 3 –
ICX418AKL
Block Diagram and Pin Configuration
(Top View)
11 12 13 14 15 16 17 18 19 20
Note) : Photo sensor
NC
VDSUB
NC
GND GND
RD
φRG
NC
Hφ1 Hφ2
10 9 8 7 6 5 4 3 2 1
VOUT VDD GND VL Vφ1 GND φSUB Vφ2 Vφ3 Vφ4
Note)
Horizontal Register
Vertical Register
Cy
Cy
Mg
G
Cy
Mg
Cy
Cy
Mg
G
Cy
Mg
Ye
Ye
G
Mg
Ye
G
Ye
Ye
G
Mg
Ye
G
Pin Description
Pin No. Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol Description
Vφ4
Vφ3
Vφ2
φSUB
GND
Vφ1
VL
GND
VDD
VOUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
GND
Vertical register transfer clock
Protective transistor bias
GND
Output circuit supply voltage
Signal output
Symbol Description
NC
VDSUB
NC
GND
GND
RD
φRG
NC
Hφ1
Hφ2
Substrate bias circuit supply voltage
GND
GND
Reset drain bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock

– 4 –
ICX418AKL
Absolute Maximum Ratings
Item
Substrate clock φSUB – GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2– Vφ4
φRG – GND
φRG – φSUB
VL– φSUB
Pins other than GND and φSUB – VL
Storage temperature
Operating temperature
–0.3 to +50
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +30
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
Ratings Unit Remarks
∗1+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
VDD, VRD, VDSUB, VOUT – GND
VDD, VRD, VDSUB, VOUT – φSUB
Vφ1, Vφ2, Vφ3, Vφ4– GND
Vφ1, Vφ2, Vφ3, Vφ4– φSUB

– 5 –
ICX418AKL
DC Characteristics
Output circuit supply current
Item IDD Symbol 5.0 Min. Unit RemarksTyp. Max. mA10.0
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
∗1VLsetting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item VDD
VRD
VL
VDSUB
φSUB
Symbol 15.0
15.0
∗1
15.0
∗2
Min. V
V
V
Unit RemarksTyp. Max.
14.55
14.55
14.55
15.45
15.45
15.45
VRD = VDD
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
∗3VLsetting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗4Connect to GND or leave open.
∗5The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a
special code.When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage.The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
VSUB code — one character indication
Code and optimal setting correspond to each other as follows.
Item VDD
VRD
VL
VDSUB
VSUB
∆VSUB
Symbol 15.0
15.0
∗3
∗4
Min. V
V
V
%
Unit RemarksTyp. Max.
14.55
14.55
6.0
–3
15.45
15.45
14.0
+3
VRD = VDD
∗5
∗5
<Example> "L" →VSUB = 9.0V
VSUB code
Optimal setting
f
6.5
G
7.0
h
7.5
J
8.0
K
8.5
L
9.0
m
9.5
N
10.0
P
10.5
Q
11.0
S
12.0
U
13.0
V
13.5
W
14.0
R
11.5
T
12.5
E
6.0

– 6 –
ICX418AKL
Clock Voltage Conditions
∗1Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage∗1
Substrate clock voltage
Item
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
| VVH1 – VVH2 |
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VRGL
VφRG
VRGLH – VRGLL
VφSUB
Symbol
14.55
–0.05
–0.2
–9.6
8.3
–0.25
–0.25
4.75
–0.05
4.5
23.0
Min.
1
2
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Low-level coupling
Remarks
Reset gate clock
voltage
Item
VRGL
VφRG
Symbol
4
4
Waveform
diagram Remarks
15.0
0
0
–9.0
9.0
5.0
0
∗1
5.0
24.0
Typ.
15.45
0.05
0.05
–8.5
9.65
0.1
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
25.0
Max. Unit
V
V
V
V
Vp-p
V
V
V
V
V
V
V
Vp-p
V
V
Vp-p
V
Vp-p
–0.2
8.5
Min.
0
9.0
Typ.
0.2
9.5
Max. Unit
V
Vp-p

– 7 –
ICX418AKL
Horizontal transfer clock equivalent circuitVertical transfer clock equivalent circuit
Hφ1Hφ2
CφH1 CφH2
CφHH
Vφ 1
Cφ V12
Vφ 2
Vφ 4
Vφ 3
Cφ V34
Cφ V23 Cφ V41
Cφ V1
Cφ V2
Cφ V4
Cφ V3
R GND
R 4
R 1
R 3
R 2
Clock Equivalent Circuit Constant
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφH1
CφH2
CφHH
CφRG
CφSUB
R1, R3
R2, R4
RGND
Symbol
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Item Min. 2700
2700
820
330
100
91
47
11
680
91
100
68
Typ. Max. pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Unit Remarks

– 8 –
ICX418AKL
Drive ClockWaveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn – VVLn (n = 1 to 4)
100%
90%
10%
0% tr tf 0V
twh
φM
2
φM
V VT
VVH1 VVHH
VVHL
VVH
VVLH
VVL1
VVLL
VVHL
VVHH
VVL
VVHH VVH
VVLH
VVLL
VVL
VVHL
VVL3
VVHL
VVH3
VVHH
VVH2
VVHH
VVHH
VVHL VVHL
VVH
VVLH
VVL2
VVLL
VVL
VVH
VVL
VVHL
VVLH
VVLL
VVHL
VVH4
VVHH VVHH
VVL4
Vφ1Vφ3
Vφ2Vφ4

– 9 –
ICX418AKL
(3) Horizontal transfer clock waveform
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the period twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
10%
0%
VSUB tr tftwh
φM
2
φM
VφSUB
tr twh tf
90%
10%
twl
Vφ
H
V HL
Point A
twl
VφRG
VRGH
VRGL
VRGLH
RG waveform
VRGLL
Hφ1waveform
twhtr tf
+2.5V
VRGLm
VRGL + 0.5V

– 10 –
ICX418AKL
Clock Switching Characteristics
∗1When vertical transfer clock driver CXD1267AN is used.
∗2tf ≥tr – 2ns.
∗3The overlap period for twh and twl of horizontal transfer clocks Hφ1and Hφ2is two.
Min. two Typ. Max.
16 20
Unit
ns
RemarksItem
Horizontal transfer clock
Symbol
Hφ1, Hφ2∗3
Min. twh Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
twl tr tf
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
Unit
µs
ns
ns
µs
ns
µs
Remarks
During readout
∗1
∗2
When draining
charge
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1, Vφ2,
Vφ3, Vφ4
Hφ
Hφ1
Hφ2
φRG
φSUB
Horizontal transfer clock
0.5
During
imaging
During
parallel-serial
conversion

– 11 –
ICX418AKL
Image Sensor Characteristics
Item
Sensitivity
Saturation signal
Smear
Video signal shading
Uniformity between
video signal channels
Dark signal
Dark signal shading
Flicker Y
Flicker R-Y
Flicker B-Y
Line crawl R
Line crawl G
Line crawl B
Line crawl W
Lag
Symbol
S
Ysat
Sm
SHy
∆Sr
∆Sb
Ydt
∆Ydt
Fy
Fcr
Fcb
Lcr
Lcg
Lcb
Lcw
Lag
Min.
1040
1000
Typ.
1300
–115
Max.
–105
20
25
10
10
2
1
2
5
5
3
3
3
3
0.5
Unit
mV
mV
dB
%
%
%
%
mV
mV
%
%
%
%
%
%
%
%
Measurement
method
1
2
3
4
4
5
5
6
7
8
8
8
9
9
9
9
10
Remarks
Ta = 60°C
Zone 0 and I
Zone 0 to II'
Ta = 60°C
Ta = 60°C
Zone Definition of Video Signal Shading
Measurement System
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.
14
V
10
14
12
10
Ignored region
Effective pixel region
Zone 0, I
Zone II, II'
V
10
H
8H 8
768 (H)
494 (V)
CCD C.D.S
LPF1
AMP
CCD signal output Y signal output
Chroma signal output
(3dB down 6.3MHz)
(3dB down 1MHz)
[∗C]
S/H
S/H LPF2
[∗Y]
[∗A]
(Ta = 25°C)

– 12 –
ICX418AKL
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value ofY signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
As shown in the left figure, fields are read out.The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg +Ye), (G + Cy), and (Mg + Ye).
These signals are processed to form the Y signal and chroma (color difference) signal.The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} ×1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} ×1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R –Y and – (B – Y)
in alternation.This is also true for the B field.
Cy Ye Cy Ye
GMgGMg
Cy Ye Cy Ye
Mg G Mg G
B
A1
A2
Hreg
Color Coding Diagram

– 13 –
ICX418AKL
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject.(Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6.The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter.The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys ×[mV]
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of theY signal output, 200mV, measure the minimum value of theY signal.
3. Smear
Set to standard imaging condition II.With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.
Sm = 20 ×log
4. Video signal shading
Set to standard imaging condition II.With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 ×100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of theY signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.
∆Sr = | (Crmax – Crmin)/200 | ×100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | ×100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
250
60
1
10
1
500
YSm
200 ××[dB] (1/10V method conversion value)

– 14 –
ICX418AKL
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Ydt =Ydmax –Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of theY signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.
Fy = (∆Yf/200) ×100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of theY signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.
Fci = (∆Ci/CAi) ×100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of theY signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) ×100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200) ×100 [%]
Light
Y signal output 200mV Ylag (lag)
FLD
V1
Strobe light
timing
Output

– 15 –
ICX418AKL
Drive Circuit 1 (substrate bias internal generation mode)
22/16V
0.01
–9V
3.3/16V
3.3/20V 0.01
1/35V 1
100
Hφ
1
Hφ
2
NC
φ
RG
RD
GND
GND
NC
V
DSUB
NC
22/20V
CCD OUT
[∗A]
15V
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
Hφ
2
Hφ 1
RG
100k
0.01
CXD1267AN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
3.9k
Vφ
4
Vφ
3
Vφ
2
φ
SUB
GND
V
L
GND
V
DD
V
OUT
Vφ
1
ICX418
(BOTTOM VIEW)
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
1M

– 16 –
ICX418AKL
Drive Circuit 2 (substrate bias external adjustment mode)
22/16V
0.01
–9V
3.3/16V
3.3/20V 0.01
1/35V 0.1
100
Hφ
1
Hφ
2
NC
φ
RG
RD
GND
GND
NC
V
DSUB
NC
22/20V
CCD OUT
[∗A]
15V
XSUB
XV2
XV1
XSG1
XV3
XSG2
XV4
Hφ
2
Hφ 1
RG
27k
0.01
CXD1267AN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
3.9k
0.1 39k 15k
47k
15k
270k
100k
1/35V 1/35V
0.1
Vφ
4
Vφ
3
Vφ
2
φ
SUB
GND
V
L
GND
V
DD
V
OUT
Vφ
1
ICX418
(BOTTOM VIEW)
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
1M
56k

– 17 –
ICX418AKL
Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)
Sensor Readout ClockTiming Chart
Unit: µs
Odd Field
Even Field
V1
V2
V3
V4
V1
V2
V3
V4
2.5
2.5 2.5 2.5
33.5 1.6
0.2
1.0
0.8
0.6
0.4
0.2
0400 450 500
Cy Ye
Mg
G
550
Wave Length [nm]
Relative Response
600 650 700

– 18 –
ICX418AKL
DriveTiming Chart (Vertical Sync)
520
525
1
2
3
4
5
10
15
20
493
494
260
265
270
275
280
494
493 2
14 36 52
14 36 5
FLD
VD
BLK
HD
V1
V2
V3
V4
CCD
OUT 135
246 135
246

– 19 –
ICX418AKL
Drive Timing Chart (Horizontal Sync)
760
768
1
2
3
5
10
20
30
40
1
2
3
5
10
20
22
1
2
3
1
2
3
10
20
HD
BLK
H1
H2
RG
V1
V2
V3
V4
SUB

– 20 –
ICX418AKL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment.When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d)Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
39N
Lower ceramic
Upper ceramic
Compressive strength
Low melting
point glass
29N
Shearing strength
29N
Tensile strength
0.9Nm
Torsional strength