
Pin No. Pin Name I/O Pin Description
78 CLK SEL [1] I Clock select 1 input (Fixed at “H” in this set)
79 CLK SEL [2] I Clock select 2 input (Fixed at “H” in this set)
80 VSS — Ground
81 CLK SEL [3] I Clock select 3 input (Fixed at “L” in this set)
82 VDD3 — Power supply pin (+3.3 V)
83 CLK SEL [4] O Clock select 4 output (Fixed at “L” in this set)
84 CLK SEL [5] O Clock select 5 output (Fixed at “L” in this set)
85 AGND PLL — Ground (for PLL system)
86 DA XCK I Main reference clock signal (16.9344 MHz=384 fs) from CXD3027R (IC601).
87 AVDD PLL — Power supply pin (+3.3 V) (for PLL system)
88 PGIO4 I/O Connect to VSS in this set.
89 PGIO5 I/O Connect to VSS in this set.
90 PGIO6 I/O Connect to VSS in this set.
91 PGIO0 I/O Not used in this set. (Open)
92 PGIO8 I/O Connect to VSS in this set.
93 PGIO2/VSYNC/CSYNC O Vertical synchronized signal output (Not used in this set)
94 AVDD PLL — Power supply pin (+3.3 V) (for PLL system)
95 NC O Not used. (Fixed at “L” in this set)
96, 97 NC O Not used. (Open)
98 AGND PLL — Ground (for PLL system)
99 VSS — Ground
100 NC O Not used. (Open)
101 PGIO3/HSYNC I/O Not used in this set. (Open)
102 VDD3 — Power supply pin (+3.3 V)
103 PGIO1/VCK-OUT I/O Not used in this set. (Open)
104 VSS — Ground
105 GCK I Connect to VSS in this set.
106 VCK IN I Main clock for video signal processor input from Buffer (27 MHz) (IC904).
107 DA-EMP O Not used. (Open)
108 DA-LRCK O Digital audio L/R sampling clock signal (44.1 kHz) output to CXD3027R (IC601).
109 VDDMAX OUT O Fix the maximum output voltage (+5 V) certain output
110 DA-DATA O Digital audio data output to CXD3027R (IC601).
111 DA-BCK O Digital audio bit clock signal (2.8224 MHz) output to CXD3027R (IC601).
112 HD-OUT O Serial data output to TMP87PM41U (IC902).
113 HRDY O Ready signal output to TMP87PM41U (IC902)
114 HINT O Interrupt request signal output to TMP87PM41U (IC902).
115 CDG-SCK I/O CD graphics serial clock input/output (Fixed at “L” in this set)
116 VSS — Ground
117 HCK I Serial data transfer clock signal input from TMP87PM41U (IC902).
118 VDD3 — Power supply pin (+3.3 V)
119 HD-IN I Serial data input from TMP87PM41U (IC902).
120 VDD3 — Power supply pin (+3.3 V)
121 HSEL I Command selection signal input from TMP87PM41U (IC902).
122 CDG-SDATA I CD graphics serial data input (Fixed at “L” in this set)
123 CDG-VFSY I CD graphics VFSY input (Fixed at “L” in this set)
124 CDG-SOS1 I CD graphics SOS1 input (Fixed at “L” in this set)
125 – 128 NC O Not used. (Open)
– 15 – – 16 –
• IC906 CL680T-D1 (AUDIO/VIDEO MPEG DECODER)
Pin No. Pin Name I/O Pin Description
1 NC O Not used. (Open)
2 VSS — Ground
3 CD BCK I CD decode bit clock signal (2.8224 MHz) input from the CXD3027R (IC601).
4 CD DATA I CD decode data input from the CXD3027R (IC601).
5 CD LRCK I CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3027R (IC601).
6 CD C2PO I CD decode C2 error data input from the CXD3027R (IC601).
7 – 9 NC O Not used. (Open)
10 – 15 MD0 – 5 I/O Two-way data bus with the program ROM (IC903) and DRAM (IC905).
16 VSS — Ground
17 MD6 I/O Two-way data bus with the program ROM (IC903) and DRAM (IC905).
18 VDD3 — Power supply pin (+3.3 V)
19 MD7 I/O Two-way data bus with the program ROM (IC903) and DRAM (IC905).
20 VSS — Ground
21 MD8 I/O Two-way data bus with the program ROM (IC903) and DRAM (IC905).
22 VDD3 — Power supply pin (+3.3 V)
23 – 28 MD9 – 14 I/O Two-way data bus with the program ROM (IC903) and DRAM (IC905).
29 MD15 I/O Two-way data bus with the program ROM (IC903).
30 – 36 NC O Not used. (Open)
37 MCE O Chip enable signal output to the program ROM (IC903).
38 MWE O Write enable signal output to the DRAM (IC905).
39 VSS — Ground
40 CAS O Column address strobe signal output to the DRAM (IC905).
41 VDD3 — Power supply pin (+3.3 V)
42 RAS0 O Row address strobe signal output to the DRAM (IC905).
43 RAS1 O Row address strobe signal output (Not used in this set)
44, 45 MA10, 9 O Address signal output to the program ROM (IC903).
46 MA8 O Address signal output to the program ROM (IC903) and DRAM (IC905).
47 VSS — Ground
48 MA7 O Address signal output to the program ROM (IC903) and DRAM (IC905).
49 VDD3 — Power supply pin (+3.3 V)
50 – 52 MA6 – 4 O Address signal output to the program ROM (IC903) and DRAM (IC905).
53 VSS — Ground
54 MA3 O Address signal output to the program ROM (IC903) and DRAM (IC905).
55 VDD3 — Power supply pin (+3.3 V)
56 – 58 MA2 – 0 O Address signal output to the program ROM (IC903) and DRAM (IC905).
59 PGIO7 I/O Connect to VSS in this set.
60 RESET I Reset signal input from TMP87PM41U (IC902). (“L”: Reset)
61 VDDMAX IN I Fix the maximum input voltage each input pin and input/output pin.
62 – 64 NC O Not used. (Open)
65 AGND DAC — Ground (for D/A converter)
66 AVDD DAC — Power supply pin (+3.3 V) (for D/A converter)
67 COMPOS OUT O Composite video signal output
68 AGND DAC — Ground (for D/A converter)
69 Y-OUT O Luminance video signal output (Not used in this set)
70 AVDD DAC — Power supply pin (+3.3 V) (for D/A converter)
71 AGND DAC — Ground (for D/A converter)
72 RREF I Fix the video signal output level control.
73 VREF O Reference voltage (+1.235 V) output
74 AVDD DAC — Power supply pin (+3.3 V) (for D/A converter)
75 C-OUT O Chrominance video signal output (Not used in this set)
76 AGND DAC — Ground (for D/A converter)
77 CLK SEL [0] I Clock select 0 input (Fixed at “H” in this set)
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com