SpinCore Technologies DDS-I-300 User manual

PulseBlasterDDS™
Model DDS-I-300
(USB Board Version SP7)
Owner’s Manual
SpinCore Technologies, Inc.
htt ://www.s incore.com

PulseBlasterDDS-I-300
Congratulations and thank you for choosing a design from S inCore
Technologies, Inc.
We a reciate your business!
At S inCore we try to fully su ort the needs of our customers. If you are in
need of assistance, lease contact us and we will strive to rovide the
necessary su ort.
© 2007 - 2017 SpinCore Technologies, Inc. All rights reserved.
SpinCore Technologies, Inc. reserves the right to make changes to the prod ct(s) or information herein witho t notice.
P lseBlasterDDS™, P lseBlaster™, SpinCore, and the SpinCore Technologies, Inc. logos are trademarks of SpinCore Technologies, Inc. All other
trademarks are the property of their respective owners.
SpinCore Technologies, Inc. makes every effort to verify the correct operation of the eq ipment. This eq ipment version is not intended for se in a
system in which the fail re of a SpinCore device will threaten the safety of eq ipment or person(s).
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PulseBlasterDDS-I-300
Table of Contents
Table of Contents ................................................................................................................................... 3
I. Introduction ......................................................................................................................................... 4
Product Overview ....................................................................................................................................................... 4
Board Architecture ...................................................................................................................................................... 4
Block Diagram ....................................................................................................................................................... 4
Product S ecifications ................................................................................................................................................ 6
RF Out ut Level ........................................................................................................................................................... 7
II. Installation .......................................................................................................................................... 8
Installing the PulseBlasterDDS-I-300 ......................................................................................................................... 8
Testing the PulseBlasterDDS-I-300 ............................................................................................................................. 9
III. Using the PulseBlasterDDS-I-300 ................................................................................................. 11
Controlling the PulseBlasterDDS-I-300 with S inAPI .............................................................................................. 11
Frequency and Phase Registers ............................................................................................................................... 11
Sample Output ..................................................................................................................................................... 12
Sha e and Am litude Registers (AWG) ................................................................................................................... 14
Sample Output ..................................................................................................................................................... 14
Pulse Programs .......................................................................................................................................................... 16
Control lines ......................................................................................................................................................... 17
Triggering ................................................................................................................................................................... 18
Clock out ut on BNC0 ............................................................................................................................................... 18
Clock In ut Signal Standard ..................................................................................................................................... 19
IV. PCI Connection - Connecting to the PulseBlasterDDS-I-300-PCI boards ................................ 20
Connector Information .............................................................................................................................................. 20
BNC Connectors .................................................................................................................................................. 20
Long IDC Hea ers ............................................................................................................................................... 20
HWTrig/Reset Hea er .......................................................................................................................................... 21
V. USB Connection - Connecting to the PulseBlasterDDS-I-300-USB boards .............................. 22
Power Requirements ................................................................................................................................................. 22
Power Connectors .................................................................................................................................................... 22
Digital Out ut Connectors ....................................................................................................................................... 23
Header JP302 ............................................................................................................................................................ 25
Connector Locations ................................................................................................................................................. 25
VI. External Frequency Modulation .................................................................................................. 26
Hea er JP302 (Frequency Select an HW Trigger/Reset) ................................................................................... 26
Important Notes: .................................................................................................................................................. 27
VII. PulseBlasterDDS-I-300 Interface for LabVIEW .......................................................................... 27
Overview of S inCore LabVIEW GUI Interface ........................................................................................................ 27
Related Products and Accessories ................................................................................................... 28
Contact Information ............................................................................................................................. 29
Document Information ........................................................................................................................ 29
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PulseBlasterDDS-I-300
I. Introduction
Product Overview
P lseBlasterDDS is a high-performance signal generator that combines two nits – the digital waveform synthesis nit
(DDS, Direct Digital Synthesis), and the P lseBlaster Timing Processor.
The P lseBlaster Timing Processor provides all the necessary timing control signals req ired for overall system control
and p lse synchronization. This part of the P lseBlasterDDS design also generates the programmable-length digital (TTL
logic) p lses. By adding DDS feat res, P lseBlasterDDS can now provide not only programmable TTL p lses b t also
RF (Radio Freq ency) o tp t signals. By tilizing the P lseBlaster Timing Processor core, the combined system can
generate sophisticated p lse seq ences with single-clock acc racy, meeting high-performance demands of advanced
sers.
The P lseBlasterDDS-I-300 is eq ipped with one 300 MHz DAC (Digital-to-Analog Converter), and it can prod ce
sef l o tp t signal freq encies from DC (Direct C rrent) (0 Hz) to 100 MHz. Arbitrary Waveform Generation (AWG),
o tp t gating and atten ation, and ser-programmable amplit de, freq ency, and phase mod lation are standard. In
addition to the ability to mod late the envelope of the generated signal, the shape of the carrier signal can be c stom-
defined as well, giving the ser the opport nity to explore novel excitation modes. Select designs allow for external
freq ency mod lation sing dedicated hardware inp t lines.
Packaged in a small USB form factor, the P lseBlasterDDS-I-300 series of boards provide sers the ability to control
their systems thro gh the generation of f lly synchronized digital and analog excitation p lses, ranging from simple RF and
TTL p lses to sophisticated excitation schemes with nested loops, s bro tines, etc., providing sers with a compelling
price/performance proposition nmatched by any other device on the market today.
Please note that c rrently, the PCI board version SP6 is only available for special orders.
Board Architecture
Block Diagram
Fig re 1, on the next page, presents the general architect re of the P lseBlasterDDS-I-300 board. The two major
b ilding blocks are the DDS Core (top level blocks in Fig re 1), and the P lseBlaster Timing Core (PB Core, bottom level
of blocks in Fig re 1).
The DDS Core contains a N merically Controlled Oscillator (NCO) that is eq ipped with programmable freq ency and
phase registers that are nder the p lse program control thro gh the P lseBlaster Timing Core. Following the NCO, the
Arbitrary Waveform Generator (AWG) nit can mod late the signal envelope to a ser programmable shape, e.g., a sinc
shape. Scaling, or atten ation of the signal amplit de, is also nder program control, as well as the additional gating
(blanking) in the digital domain.
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PulseBlasterDDS-I-300
The PB Core controls the timing of the gating p lses and provides the necessary control signals for freq ency, phase,
shape and amplit de registers. The PB Core also o tp ts TTL signals to the o tside world, as programmed by the ser.
The PB processor core exec tes instr ctions as written by the ser and stored in the on-chip SRAM mod le, and, once
programmed, the processor operates a tonomo sly.
The DDS and PB cores are driven from a common clock so rce (the 50 MHz1 Reference Clock in Fig re 1). The on-
board clock so rce is removable and, in lie of the on-board clock, any 3.3 V TTL compatible clock so rce of arbitrary
stability can be sed.
The DDS and PB cores have been integrated onto a single silicon chip. High performance DAC chip and high-c rrent
o tp t amplifier complement the design. User control of the system is provided thro gh the host-programming interface
over the PCI b s or USB controller.
1A 75 MHz clock may be sed with the P lseBlasterDDS-I-300.
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Figure 1: P lseBlasterDDS-I-300 Board Architect re.

PulseBlasterDDS-I-300
Product S ecifications
Parameter Min Typ Max Units
Analog O tp t D/A sampling rate 300 MHz
D/A sampling precision 14 bits
O tp t voltage range (peak-peak) 1 - 4 (1) -V
Phase resol tion 0.09(2) -deg.
Freq ency resol tion 1.11(3) -Hz
RF O tp t (8) DC (0 Hz) 100 MHz
Digital O tp t N mber of digital o tp ts 4(4) 9
Logical 1 o tp t voltage 3.3(5) -V
Logical 0 o tp t voltage 0-V
O tp t drive c rrent 25 mA
Rise/Fall time 1 -ns
Digital Inp t
(HW_Trig,HW_Reset)
Logical 1 inp t voltage 1.7 4.1 V
Logical 0 inp t voltage -0.5 0.7 V
P lse Program # of instr ction words 1024 to 4096(6) -words
P lse resol tion 13.3(7) -ns
Instr ction length 66.6 ns 693 days
Table 1: P lseBlasterDDS-I-300 Prod ct Specifications.
Notes
1) Analog o tp t voltage is factor adj stable p to 4 Vpp at 10 MHz. See RF O tp t Level section on the next page
for more information.
2) Phase-offset control word is 12-bit wide.
3) Ass ming a 50 MHz reference clock and a 300 MHz NCO freq ency. Freq ency control word is 28-bit wide.
4) On PCI boards, all 24 control bits are ro ted to on-board IDC header, and signals that are not sed internally can
be tilized to control o tside devices. Please contact SpinCore if yo req ire more digital o tp ts; c stom
designs with more o tp t bits may be available.
5) This is the val e seen witho t sing termination. When the line is terminated with 50 Ω, the o tp t voltage will be
lower.
6) This n mber can be larger on USB boards. Please contact SpinCore for c stom design feat ring a larger n mber
of instr ction words.
7) Ass ming a 50 MHz reference clock and a 75 MHz P lseBlaster timing core freq ency.
8) The RF o tp t can operate from direct c rrent - DC (0 Hz) to 100 MHz. The analog o tp t is DC co pled.
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PulseBlasterDDS-I-300
RF Out ut Level
There are c rrently two different options for P lseBlasterDDS-I-300 RF analog o tp t amplifier – the standard gain and
the high gain. Fig re 2, below shows the typical freq ency characteristics of the analog o tp t signals for the two o tp t
options. The standard-gain P lseBlasterDDS-I-300 for a 50 Ω load has an o tp t voltage of 1 Volt peak-to-peak at 10
MHz, with a 3 dB bandwidth of abo t 85 MHz. The high-gain amplifier with a 50 Ω load has a maxim m o tp t voltage of
abo t 3.75 Volts peak-to-peak, with a 3 dB bandwidth of abo t 21 MHz, while covering the same freq ency range as the
standard-gain board.
Please note, the s stained analog o tp t voltage feat re is only available on PCI boards. To obtain a s stained
analog o tp t voltage, set the freq ency register to 0.0 Hz, and se the content of the phase registers to control the act al
o tp t voltage level.
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Figure 2: P lseBlasterDDS-I-300 analog o tp t voltage vs. o tp t freq ency. The
dotted line represents the standard-gain o tp t amplifier, and the solid line
represents the high-gain o tp t amplifier. The voltage val es are for a 50 Ohm
load impedance. The zero dBm o tp t val e for both amplifiers occ rs at
approximately 90 MHz.
0 20 40 60 80 100 120
0
0.5
1
1.5
2
2.5
3
3.5
4
High Gain
Standard Gain
Freq ency (MHz)
Voltage (volts pk-pk on 50 Ohms)

PulseBlasterDDS-I-300
II. Installation
Installing the PulseBlasterDDS-I-300
To install the board yo m st complete the following three steps:
1. Download and install the latest SpinAPI software package and example programs on yo r comp ter. These are
available at: http://www.spincore.com/s pport/spinapi/
•SpinAPI is a c stom Application Programming Interface (API) package developed by SpinCore Technologies,
Inc. SpinAPI is designed to be sed only with SpinCore Technologies, Inc. prod cts. SpinAPI can be tilized
sing C/C++, or LabVIEW (described in Section VII).
•SpinAPI contains device drivers and example programs. A shortc t to the location of these files is created
a tomatically in the Windows Start Men at “Start>Programs>S inCore”. See the “readme.txt” file in this
location for more information.
2. Sh t down the comp ter
•For the PCI board: Insert the P lseBlasterDDS-I-300 card into an available PCI slot and fasten the PC
bracket sec rely with a screw.
•For the USB board: Pl g one end of the USB cable into the P lseBlasterDDS-I-300 board and the other
end into the host comp ter. Next, power the board thro gh the 5-pin DIN-type connector or 6-position
Molex-style connector. We recommend p rchasing the RadioProcessorUSB Power S pply, which has the
6-pin o tp t connector and is pin-compatible with the power connector of the PBDDS-I-300-USB board.
For more information on powering the P lseBlasterDDS-I-300 USB board please read Power Connectors
in Section V. USB Connection - Connecting to the P lseBlasterDDS-I-300-USB boards.
•Warning: Do not connect PEG (PCI Express Graphics) power connectors available in some comp ters
directly to the 6-position Molex-style power connector. Doing so will ca se irreparable damage to the
board. SpinCore Technologies is not liable for any damage ca sed by this.
3. T rn on the comp ter and follow the installation prompts. Windows may recognize yo r board as a
RadioProcessor board b t the board will still f nction as it sho ld, as the f nctionality of the PBDDS-I-300 is a s b-
set of the f nctionality of the RadioProcessor.
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PulseBlasterDDS-I-300
Testing the PulseBlasterDDS-I-300
Once yo r board is installed properly, the f nctionality of the device can be tested sing three example programs
available from the SpinCore website. All o tp t seq ences generated by test programs can be verified sing an
oscilloscope.
If yo are sing a high inp t impedance oscilloscope to monitor the P lseBlasterDDS-I-300's o tp t, place a resistor
that matches the characteristic impedance of the transmission line in parallel with the coaxial transmission line at the
oscilloscope inp t by attaching it to the line thro gh a T-Adapter(e.g., a 50 Ω resistor with a 50 Ω transmission line, see
Fig res 3 and 4 below). For ease of observing the p lsed RF signals, the oscilloscope sho ld be triggered by any of the
TTL o tp ts. When sing an oscilloscope with an adj stable bandwidth, set the bandwidth to as large as possible. Fail re
to do so may yield inacc rate reado ts on the oscilloscope.
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Figure 3: Left: BNC T-Adapter and Right: BNC 50 Ohm
resistor.

PulseBlasterDDS-I-300
The first program is pbdds_i_300_excite_test. This will prod ce a 1.0 MHz sine wave on the Analog O t connection and
a logical high signal on the Digital O t connection - these signals will t rn on for 10 μs and off for 1 ms and will be repeated
indefinitely. The Digital O t on the oscilloscope can be sed to trigger the capt re of the analog signal.
The signal o tp t can be stopped by sing the pb_stop.exe program. The corresponding pb_start.exe will restart the
PBDDS board. Reloading the board with a new program will also stop the exec tion of any r nning program.
Next, pbdds_i_300_phase_test will prod ce a 1.0 MHz o tp t on the Analog O t connection which will t rn on for 8 μs
and off for 1 ms. The sin wave will cycle thro gh 4 phase offset registers(one every 2 μs, 90 degrees apart) and will
repeat indefinitely.
To test the AWG feat re of the board, se pbdds_i_300_awg. This program will ask for two amplit de val es and one
freq ency val e, and then it will load the board to o tp t two sinc-shaped p lses, one with each amplit de val e. This will
repeat every 1 ms.
Along with the exec table programs, the folder also contains the C so rce code of all test programs. Any so rce code
can be modified, th s allowing the ser to start making c stomized programs as necessary. When SpinAPI tools are
installed on the comp ter, do ble-clicking any C so rce code will la nch a graphical integrated environment for easy
editing and reb ilding of new exec tables via the “Reb ild All” men f nctionality.
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Figure 4: BNC T-Adapter on oscilloscope with coaxial
transmission line connected on the left and BNC 50 Ohm
resistor connected on the right, to terminate the line.

PulseBlasterDDS-I-300
III. Using the PulseBlasterDDS-I-300
Controlling the PulseBlasterDDS-I-300 with S inAPI
This section describes the f nction and se of each feat re of the P lseBlasterDDS-I-300.
The P lseBlasterDDS-I-300 is a highly versatile excitation board, and as a res lt there are many possible approaches
to program the board. However, most applications can be programmed following these basic steps:
1. Load freq ency and phase registers with desired val es.
2. Load shape and DDS data and amplit de registers (if applicable).
3. Specify a p lse program which will control the timing of the experiment.
4. Trigger the p lse program. The experiment will then proceed a tonomo sly.
These steps are described below. For each of the steps, the relevant SpinAPI f nctions are listed which control the
actions needed to perform that partic lar step.
SpinAPI is a control library which allows programs to be written to comm nicate with yo r SpinCore board. The most
straightforward way to interface with this library is with a C/C++ program, and the API definitions are described in this
context. However, virt ally all programming lang ages and software environments (incl ding software s ch as LabView
and Matlab) provide mechanisms for accessing the f nctionality of standard libraries s ch as SpinAPI.
Please see the example programs described in the preceding section, “Testing the P lseBlasterDDS-I-300,” for an an
explanation of how to se SpinAPI. A reference doc ment for the API is available online at:
http://spincore.com/s pport/spinapi/. Under the “Download” b llet there is a link called “API Reference”. An API reference
is also provided in the folder C:\SpinCore\SpinAPI when SpinAPI has been downloaded and installed in the defa lt
location.
Frequency and Phase Registers
The P lseBlasterDDS-I-300 contains one N merically Controlled Oscillator and associated digital circ itry that drives
the on-board digital-to-analog (DAC) converter, th s forming the Analog O tp t channel. The freq ency and phase of the
o tp t signal are controlled by selecting val es from a bank of on-board registers. These registers sho ld be programmed
with appropriate val es after board initialization, b t before triggering the board. Each p lse instr ction selects which
register is sed at any given time d ring an experiment. The n mber of available registers for each channel is given in the
table below. Certain designs allow the ser to select freq ency registers sing dedicated hardware control lines. See
section VI. External Freq ency Mod lation for more information.
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PulseBlasterDDS-I-300
Register Bank umber of registers
Freq ency 162
Phase 163
Table 2: Freq ency Register information.
Relevant SpinAPI functions:
pb_start_programming()
pb_set_phase()
pb_set_freq()
pb_stop_programming()
Sample Output
Fig re 5, below, shows an example RF 70 MHz o tp t p lse that was generated by the board. The data was capt red
sing a Tektronix TDS224 oscilloscope. Notice the time base of 25 ns/division.
2Firmware design 10-16 has been modified to have 1024 freq ency registers.
3Firmware design 10-16 has been modified to have 4 available TX phase registers.
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Figure 5: 185 ns 70 MHz RF/IF o tp t p lse.

PulseBlasterDDS-I-300
Fig re 6, below, demonstrates the zero-latency phase-switching agility. In this fig re, two short back-to-back p lses
were recorded with a 180-degree phase offset and a 70 MHz carrier freq ency (expanded view).
Fig re 7, below, demonstrates the freq ency-shift agility. In this fig re, the freq ency j mps from 20 MHz to 10 MHz
with no latency.
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Figure 7: Freq ency shift from 20 MHz to 10 MHz.
Figure 6: Two RF o tp t p lses, back to back, with a
180 degree phase switch and 70 MHz RF freq ency.

PulseBlasterDDS-I-300
Sha e and Am litude Registers (AWG)
The AWG (Arbitrary Waveform Generator) system can be programmed with a wide variety of parameters. The main
feat res of this system are:
•RF o tp ts can be shaped by an arbitrary waveform. (for example, a sinc waveform).
•RF o tp ts can be scaled by a constant val e.
•The RF carrier signal itself can be set to waveforms other than a sinewave (e.g., triangle wave, sq are wave, etc.).
•The shortest possible p lse is 66.6 ns, the longest is 693 days.
To make se of the AWG feat re, se the pb_inst_dds_shape() f nction to generate the instr ctions of yo r p lse
program. This f nction has two additional parameters over the standard pb_inst_dds() function. They are:
use_shape: if this is 0, no shape will be applied to the p lse. If it is nonzero, whatever waveform is
loaded as the shape will be sed to shape the RF p lse. The shape waveform can be loaded by the ser
with the pb_dds_load() f nction
amp: This selects which amplit de register to se. The val es stored in the amplit de register can be set with the
pb_set_amp() f nction.
Relevant SpinAPI functions:
pb_start_programming()
pb_inst_dds()
pb_inst_dds_shape()
pb_stop_programming()
pb_set_amp()
pb_dds_load()
Example program that are incl ded with SpinAPI in the PBDDS-I-300 directory demonstrate how the AWG capabilities
are sed. The so rce code for those programs is well doc mented, aiding in gaining a better nderstanding on how the
AWG feat res of the board are controlled.
Sample Output
Fig res 8-10 ill strate sample capabilities of the AWG feat res of the PBDDS-I-300 board. Fig re 8 demonstrates a
simple sinc-shaped soft p lse of 0.5 ms in d ration. The shape of the p lse is not limited to a sinc-shape - it is ser-
loadable with any arbitrary waveform. Fig re 9 ill strates that m ltiple soft p lses can be generated in a p lse seq ence,
and m ltiple amplit des can be assigned to individ al p lses. Fig re 10 shows that it is also possible to combine soft and
hard RF p lses in a seq ence.
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PulseBlasterDDS-I-300
Figure 8: Sinc-shaped soft p lse. P lse d ration of 0.5 ms.
Figure 9: Combination of soft RF p lses with variable
amplit des.
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PulseBlasterDDS-I-300
Figure 10: Combination of soft and hard RF p lses in
seq ence.
Pulse Programs
The P lseBlasterDDS-I-300 contains an integrated P lseBlaster p lse generation timing core. This timing core
controls all aspects of the systems f nctionality by setting internal control lines at ser specified times. Nine ser
programmable digital o tp ts are also available for control of external hardware. The internal control lines and ser
programmable o tp ts are collectively referred to as flags. The p lse program modifies these flags in a ser-defined way
to control all aspects of an experiment.
The P lseBlaster ses a rob st instr ction set to enable the creation of complex p lse programs with ease. Each
instr ction is defined by an Operational Code (OpCode) which specifies the action of that instr ction and an optional
Instr ction data (inst_data) field which elaborates on that action. In addition, each instr ction specifies the desired val e
for the flags, as well as the exec tion time of the given instr ction, i.e., the delay ntil the next instr ction starts exec ting.
The “next” instr ction is not necessarily the next seq ential instr ction, as the instr ction set contains branching and
looping instr ctions which can ca se the program to be exec ted o t of seq ential order. A list of the available instr ctions
is given in the following table (Table 3).
OpCode # Instruction Inst_data field Function
0 CONTINUE Un sed Program exec tion contin es to next
instr ction.
1 STOP Un sed
Stop exec tion of program. Analog
o tp ts t rn off. Digital o tp ts may be
t rned off or remain from their previo s
state depending on the firmware.
2 LOOP
N mber of desired loops. This
val e m st be greater than or eq al to
1.
Specify beginning of a loop.
Exec tion contin es to next instr ction.
Data sed to specify n mber of loops
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PulseBlasterDDS-I-300
3 END_LOOP Address of beginning of loop
Specify end of a loop. Exec tion
ret rns to begging of loop and
decrements loop co nter.
4 JSR Address of first s bro tine
instr ction
Program exec tion j mps to
beginning of a s bro tine
5 RTS Un sed Program exec tion ret rns to
instr ction after JSR was called
6 BRANCH Address of instr ction to skip to
Program exec tion contin es at
specified instr ction. This behaves like
the goto statement fo nd in many
programming lang ages
7 LONG_DELAY
N mber of desired loops. This
val e m st be greater than or eq al to
2.
For long interval instr ctions.
Exec tes length of p lse given in the
time field m ltiplied by the val e in the
data field.
8 WAIT Un sed
Program exec tion pa ses and waits
for a software or hardware trigger to
res me it. The latency between a trigger
occ rring and the program res ming is
the time sed as the delay for the wait
instr ction pl s a fixed time of 6 clock
cycles.
Table 3: P lseBlaster Instr ctions.
Control lines
To control the operation of the P lseBlasterDDS-I-300, each instr ction in the p lse program specifies a flag word
which sets both the internal control lines and ser programmable digital o tp ts. The control lines stay in the given state
for the d ration of the instr ction. The internal control lines are described below in Table 4.
Control Line Function
freq ency select Selects between the 16 available freq ency registers4
TX5 channel phase select Selects between the 16 available phase registers6
tx_enable Enables TX o tp t on the Analog O t connector. If this control line is disabled,
the Analog O t channel is t rned off (zero o tp t voltage).
phase_reset When this control line is enabled, all DDS channels will be reset to their time=0
phase. For example, if a channel is set to se a phase register with 90deg, it will be
reset to the midpoint o tp t level and stay that way ntil the phase reset control line
is disabled. This allows the the phase of p lses to be synchronized between scans.
Table 4: Internal control lines.
4Firmware design 10-16 has been modified to have 1024 available freq ency registers.
5TX refers to RF o tp t.
6Firmware design 10-16 has been modified to have 4 available phase registers.
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PulseBlasterDDS-I-300
Triggering
The P lseBlasterDDS-I-300 can be triggered in two ways, either by software trigger or hardware trigger. The software
trigger is initiated by sending a command from the host PC. Beca se these boards are typically sed with non real-time
operating systems, the exact time between iss ing a software trigger and the board acting on that trigger cannot be
precisely specified. For precision control, the p lse program can also be triggered by setting the HW_Trigger pin to a
logical 0. This will ca se the p lse program to be triggered within two clock cycles (starting a program), or a minim m of 8
clock cycles (res ming from WAIT instr ction).
Triggering the p lse program has one of the following three effects:
1. Begin exec tion of a p lse program.
2. Restart exec tion of a p lse program after the board has been reset.
3. Res me exec tion of a p lse program which is c rrently pa sed by a WAIT instr ction.
Relevant SpinAPI f nctions:
pb_start()
Clock out ut on BNC0
P lseBlasterDDS-I-300 boards have the capability of o tp tting a 10 MHz7 signal on the BNC0 connector (PCI boards),
or on one of the on-board IDC headers (USB boards). This signal is a 50% d ty cycle sq are wave derived directly from
the on-board 50 MHz clock oscillator, and is intended for synchronization p rposes.
To enable this o tp t, call the following SpinAPI f nction:
pb_set_radio_control(BNC0_CLK);
To have BNC0 ret rn to normal p lse program behavior, call:
pb_unset_radio_control(BNC0_CLK);
If this clock o tp t is enabled, loading the board with another p lse program will not affect the o tp t clock signal. The
10 MHz signal will contin e to be present on the o tp t connector ntil one of the following events occ rs: (1) the comp ter
is t rned off, (2) pb_unset_radio_control(BNC0_CLK) is called, or (3) pb_set_defaults() is called. Condition 3
may occ r if yo are sing m ltiple programs to control yo r P lseBlasterDDS-I-300, and can be avoided by making s re
that only one of the programs calls pb_set_defaults() and that this program is not r n after the one that calls
pb_set_radio_control(BNC0_CLK).
NOTE: When enabled, this option does not affect the f nctionality of the Digital O tp t 0 pin on the IDC connector. This
pin will still serve as a digital o tp t nder control of the p lse program.
7Ass ming a 50 MHz clock. A 75 MHz clock wo ld give a 15 MHz reference signal.
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PulseBlasterDDS-I-300
Clock In ut Signal Standard
The P lseBlasterDDS-I-300 is a digital system b ilt in CMOS technology and powered off a 3.3 V DC so rce. It will
accept external clock signals that conform to the low-voltage 3.3 V TTL standard only. Negative voltage below 0.2 Volts
wo ld damage the processor chip, and th s any external sin soidal signal wo ld need to be converted to the positive-only
TTL signal prior to sing with the P lseBlasterDDS-I-300.
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PulseBlasterDDS-I-300
IV. PCI Connection - Connecting to the
PulseBlasterDDS-I-300-PCI boards
Connector Information
There are two main connector types on the P lseBlasterDDS-I-300 PCI board: the BNC connectors and the IDC
headers – see Fig re 11 below. BNC connectors are mo nted on the PCI bracket and are available o tside of the
comp ter. The IDC connectors are mo nted on-board and are available inside the comp ter only. There are two long IDC
headers and one short IDC header.
B C Connectors
The fo r BNC connectors provide the primary o tp t interface of the P lseBlasterDDS-I-300 PCI board. All connectors
are impedance matched to 50 Ω. BNC2 is the Analog O tp t port. BNC1 and BNC0 are both general p rpose digital
o tp ts which can be controlled thro gh the p lse program. BNC3 is not sed for the P lseBlasterDDS-I-300.
The analog o tp t connector (BNC2), is not eq ipped with an interpolating filter. This allows for maxim m flexibility in
o tp t freq ency, b t it means that the o tp t may appear q antized if no filter is sed on the o tp t. To eliminate this
behavior and obtain a smooth RF p lse, the ser may filter the o tp t with a bandpass or lowpass filter which will c t off
the ndesired freq ency components above the intended RF signal.
Long IDC Headers
There are two long (2x13 pins) IDC headers on the P lseBlasterDDS-I-300 PCI board. The headers provide access to
all 24 bits of the flag word, nine of which are available to the ser as general p rpose digital o tp ts. These are labeled
Flag0..11_O t and Flag12..23_O t. On each IDC header the top row of pins (14-26) are gro nds, and the signals are
carried on pins 1-13.
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Figure 12: IDC header pino t.
14 15 16 17 18 19 2 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 1 11 12 13
Figure 11: PCI Board Connector Locations.
IDC Headers
BNC3 (Not Used)
BNC1 (Digital O t)
BNC0 (Digital O t)
Hardware Trigger/Reset
(Digital O t)
BNC2 (Analog O t)
IDC Headers
Flag0..11_O t Flag12..23_O t