Sundance Spas SMT301A User manual

SMT301A
SU MUTSS TG MT
Document No: SMT301A-UG—1.10 ; 10/04/97
VXI 8 SLOT MOTHERBOARD
User Guide

Disclaimer
Every effort has been made to ensure the
accuracy of this document, however the
manufacturer cannot accept responsibility
for any loss or damage caused as a result of
using this document.
Notice of any mistakes, inconsistencies or
comments relating to this document would
be gratefully received by fax to Sundance.
Fax No.: [phone]
All rights reserved. No part of this
document may be reproduced, in any form.
or by any means, without the written
permission of Sundance.

TABLE OF CONTENTS
1. Features 2
2. Architectural Overview 3
3. Global Bus Resources 4
4. VXI Interface 6
5. VXI Interface Registers 7
6. Control and Status Registers 10
7. Dual Port RAM (DPR) 14
8. JTAG Debugging Logic 15
9. Comm-port Interface 18
10. Reset Board Register 19
11. ‘C4x Memory Map 20
12. Communications Ports 21
13. TIM Sites 24
14. FIFO and High Speed Interface 25
15. Circuit / Schematic Description 27
16. Physical Characteristics 42
17. References 44
Sundance SMT301 User Guide
10 April, 1997 -1-

1 Features
q Eight slot TIM motherboard
q Flexible communications port linking
q All 8 front panel comm-ports fully buffered
q Double pipe architecture - comm-ports unbuffered
q Global board resources
q 1MByte of one-wait-state SRAM accessible by TIM sites or VXI
q Memory expansion by daughter module (can be zero-wait-state)
q On board JTAG debugging circuit - accessed from VXI
q On board comm-port interface to VXI
q High speed Hewlett Packard ‘Local Bus’ interface via 32x 2KByte in and out
FIFO (100MBytes/s)
SMT301 User Guide Sundance
-2- 10 April, 1997

2 Architectural Overview
This description should be read with reference to the diagram titled ‘VXI
Motherboard Architecture’. Note that the layout of TIM sites on theboard, is in the
same order as shown in the diagram.
link
patch
headers
Front
Panel
Links
TDI
TDO
Front
Panel
JTAG
In and
Out
41 1 1
3
2
50
0
5
3
2
3
2
0
5
4
4412
5
0
3
3
0
5
124
3
2
14
5
03
2
14
5
0
05
3
2
14
TIM
Slot
8
TIM
Slot
7
TIM
Slot
6
TIM
Slot
5
TIM
Slot
1
TIM
Slot
2
TIM
Slot
3
TIM
Slot
4
buffer
buffer
buffer
buffer
byte swap buffers
Bi-FIFO
High speed
bus i/face
'C40 link
i/face
JTAG TDI
TDO
link
switch
IIOF0 (site 1)
IIOF0 (site 5)
RAM
expansion
connection
RAM
1MByte
VME
address
decode
RAM Bus
JTAG decode
link decode
RAM decode
VXI VME
FIFO Bus
Global
Bus 2
interrupt
Arbiter
& buffer
control
buffer
Figure 1: VXI Motherboard Architecture
Sundance SMT301 User Guide
10 April, 1997 -3-

3 Global Bus Resources
There are two main global bus resources available on this motherboard. These are
the bi-directional FIFO with itsHewlett Packard ‘Local Bus’ interface and thestatic
Dual Port RAM (DPR). Mutually exclusive access to these resources can be made
by either of the TIM sites which have a global bus connector (the two nearest the
VXI connectors, sites 1 and 5). TIM A can access the FIFO at the same time as TIM
B is accessing the DPR (or vice-versa). A VXI bus master can also access the on
board DPR at the same time as a TIM is accessing the FIFO.
The DPR is organised to allow the VXI to perform D8, D16 or D32 cycles, byte
swapping buffers are included for this purpose. The DPR access time is 20ns, and
the TIMs are connected to this DPR through fast (approximately 5ns) buffers. This
allows ‘C4x accesses to be performed with one- wait -state. The DPR is decoded at
TIM addresses 0xDF000000 and upward (on ‘C4x STRB1). Extra memory can be
added using the DPR expansion site. TIM access to this DPR can be zero- wait-
state if 12ns devices are used.
The bi-directional FIFO consists of two separate FIFOs, one for incoming and one
for outgoing data. The FIFOs can operate concurrently, although the Hewlett
Packard interface is not full duplex.
Access to the global resources is selected by arbitration state machines. Two
arbiters are present, one controlling access to the FIFO, and the other accesses to the
RAM and VXI bus and board control registers. The relevant resource is left granted
to the last resource master after the cycle has finished. Arbitration only occurs when
two (or more) possible bus masters are requesting the same resource. Arbitration
takes two ‘C4x cycles.
The other Global Bus Resources are VXI bus master access and the board control
registers. Because VXI bus arbitration and Global Bus Resource arbitration are
separate, a deadlock situation can occur. This deadlock isonlypossible when a TIM
starts a VXI bus master cycle around the same time that another VXI bus master
starts a cycle to access the SMT301. This situation is resolved by signaling ‘Bus
Error’ to the existing VXI bus master, which is forced to abort its’ VXI bus cycle.
Thiscycle may bere-tried after ashort delay(a few microseconds) to allow the TIM
VXI cycle to complete. This possibility must be taken into account when designing
system software.
3.1 ‘C4x Comm-port
The ‘C4x VXI interface, is designed to allow the VXI to perform D16 or D32
cycles, to access the comm-port interface register. These accesses are converted to
the correct protocol for communicating via a ‘C4x comm-port. This logic and
associated circuitry includes double buffering on reads and writes negating the need
SMT301 User Guide Sundance
-4- 10 April, 1997

for an external FIFO. The comm-port which is connected to this interface can be
switched to either of the two TIMs which have global access (TIM1 or TIM5).
A full duplex comm-port pipeline is hardwired between all of the TIMs, with TIM
sites 1 and 5 as the pipeline ends. These comm-ports are unbuffered for maximum
speed. All other TIM comm-ports are routed unbuffered to a link patch area, as are
the 8 buffered front panel comm-ports.
3.2 JTAG
A Texas Instruments Test Bus Controller (TBC) is used to control the JTAG daisy
chain between TIMs. This device is accessed from the VXI as a D16 operation only.
3.3 Interrupts
A single FPGA interrupt controller coordinates all interrupts. It contains a status
register showing unmasked interrupt sources, and 3 mask registers. These allow the
interrupt sources to be masked, before they are logically ORed, to generate 3
separate interrupt inputs, one for each of the global TIM sites and one for the VXI
bus.
A VXI interrupt, with programmablelevel, can be generated byeither global access
TIM. From each of these TIMs, the IIOF0 signal is connected to the interrupt
FPGA, and the assertion of this line generates the interrupt if it is unmasked. The
interrupt is cleared by the VXI master, when it masks the source of the interrupt.
The FIFO flags appear as interrupt sources for all three interrupt receivers. The
Global TIM sites have VXI bus error as an interrupt source. The VXI bus also has
the JTAG controller and the TIM IIOF0 outputs as interrupt sources.
Sundance SMT301 User Guide
10 April, 1997 -5-

4 VXI Interface
The VXI interface uses the P1 connector and the centre row of the P2 connector for
additional date and address lines. The interface forms a complete D8/16/32
master/slave. The card does not support slot 0 operation, block transfers or
unaligned transfers.
4.1 VXI Slave Interface
VXI address decoding is selected by the setting of the VXI base address
configuration register. The base address in VXI A32 space of the DPR is separate
to the JTAG and Link Interface and Control registers, (see next section).
Any expansion DPR fitted appears in the VXI memory map above the DPR already
presenton the board. Allof these DPR areas are accessible by the VXI master at the
same speed as the TIM sites.
4.2 VXI Master Interface
The card can support D8, D16 and D32 transfers in A16, A24 and A32 address
spaces. The TIM global data bus signals drive the VXI data bus through buffers but
no byte or word swapping is performed. That is a D8 transfer to VXI address
0x0000 would need the significant data to be in the ‘C4x data bits 7..0. A D8
transfer to address 0x0001wouldneed the significant data tobe in the‘C4x data bits
15..8. etc.
No support is provided for accessing words or longwords across longword
boundaries. i.e., all transfers must be within longword boundaries.
The ‘C4x address lines A0..A21 drive the VXI address lines A2..23. The VXI DS
signals and the VXI address bits A1, A24-31, AM0-5, LWORD are set by the
contents of Control register 4. This requires the use of a 4M Word ‘C4x address
region for VXI master access.
SMT301 User Guide Sundance
-6- 10 April, 1997

5 VXI Interface Registers
The VXI specification defines a register block within A16 address space which is
used for control, status and board set-up. These registers are shown below:
Offset Register description
00 ID register
02 Device type
04 Status / Control
06 DPR Offset
08 Sub-class Offset register
0A - 1D Sub-class dependent registers (unused)
1E Sub-class register
20 - 3F Sub-class dependent registers (unused)
The address of this register block is defined by an 8-bit DIL switch (LK1). They are
accessed in A16 address space. The top two address lines (A14 and A15) must be
‘1’. The base address (set on the switches) is compared to address bits A6 to A13.
The address bits A1 to A5 select which register to access. Switch 1 corresponds to
A13 and switch 8 to A6. The switch must be set to ‘ON’ for the corresponding
address bit to be recognised as 0.
Switch VXI Address Bit
1 A13
2 A12
3 A11
4 A10
5A9
6A8
7A7
8A6
For example:
Address 0xC000 = All on.
Address 0xD000 = All on except switch 2
Sundance SMT301 User Guide
10 April, 1997 -7-

Address 0xF800 = All on except switches 1,2,3.
Address 0xFFC0 = All off.
The VXI address modifiers must be set to 0x29 or 0x2D as these define an A16
transfer.
5.1 VXI ID Register (00)
The bit definitions for this register are:
Bit Definition
11..0 Manufacturer ID (set to 123 decimal
13..12 Address spaces 01 - A16/A32
15..14 Device classes 01 - extended (SMT301 is extended)
Always reads as 507B hex.
5.2 VXI Device Type Register (02)
The bit definitions for this register are:
Bit Definition
11..0 Model code (set to 301 decimal)
15..12 Required memory ‘m’ = 0 to 15
With 1MByte of SRAM, always reads as B12D hex.
5.3 VXI Status Register (04)
The bit definitions for the read only status register are:
SMT301 User Guide Sundance
-8- 10 April, 1997