Sundance Spas SMT301A User manual

SMT301A
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Document No: SMT301A-UG—1.10 ; 10/04/97
VXI 8 SLOT MOTHERBOARD
User Guide

Disclaimer
Every effort has been made to ensure the
accuracy of this document, however the
manufacturer cannot accept responsibility
for any loss or damage caused as a result of
using this document.
Notice of any mistakes, inconsistencies or
comments relating to this document would
be gratefully received by fax to Sundance.
Fax No.: [phone]
All rights reserved. No part of this
document may be reproduced, in any form.
or by any means, without the written
permission of Sundance.

TABLE OF CONTENTS
1. Features 2
2. Architectural Overview 3
3. Global Bus Resources 4
4. VXI Interface 6
5. VXI Interface Registers 7
6. Control and Status Registers 10
7. Dual Port RAM (DPR) 14
8. JTAG Debugging Logic 15
9. Comm-port Interface 18
10. Reset Board Register 19
11. ‘C4x Memory Map 20
12. Communications Ports 21
13. TIM Sites 24
14. FIFO and High Speed Interface 25
15. Circuit / Schematic Description 27
16. Physical Characteristics 42
17. References 44
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1 Features
q Eight slot TIM motherboard
q Flexible communications port linking
q All 8 front panel comm-ports fully buffered
q Double pipe architecture - comm-ports unbuffered
q Global board resources
q 1MByte of one-wait-state SRAM accessible by TIM sites or VXI
q Memory expansion by daughter module (can be zero-wait-state)
q On board JTAG debugging circuit - accessed from VXI
q On board comm-port interface to VXI
q High speed Hewlett Packard ‘Local Bus’ interface via 32x 2KByte in and out
FIFO (100MBytes/s)
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2 Architectural Overview
This description should be read with reference to the diagram titled ‘VXI
Motherboard Architecture’. Note that the layout of TIM sites on theboard, is in the
same order as shown in the diagram.
link
patch
headers
Front
Panel
Links
TDI
TDO
Front
Panel
JTAG
In and
Out
41 1 1
3
2
50
0
5
3
2
3
2
0
5
4
4412
5
0
3
3
0
5
124
3
2
14
5
03
2
14
5
0
05
3
2
14
TIM
Slot
8
TIM
Slot
7
TIM
Slot
6
TIM
Slot
5
TIM
Slot
1
TIM
Slot
2
TIM
Slot
3
TIM
Slot
4
buffer
buffer
buffer
buffer
byte swap buffers
Bi-FIFO
High speed
bus i/face
'C40 link
i/face
JTAG TDI
TDO
link
switch
IIOF0 (site 1)
IIOF0 (site 5)
RAM
expansion
connection
RAM
1MByte
VME
address
decode
RAM Bus
JTAG decode
link decode
RAM decode
VXI VME
FIFO Bus
Global
Bus 2
interrupt
Arbiter
& buffer
control
buffer
Figure 1: VXI Motherboard Architecture
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3 Global Bus Resources
There are two main global bus resources available on this motherboard. These are
the bi-directional FIFO with itsHewlett Packard ‘Local Bus’ interface and thestatic
Dual Port RAM (DPR). Mutually exclusive access to these resources can be made
by either of the TIM sites which have a global bus connector (the two nearest the
VXI connectors, sites 1 and 5). TIM A can access the FIFO at the same time as TIM
B is accessing the DPR (or vice-versa). A VXI bus master can also access the on
board DPR at the same time as a TIM is accessing the FIFO.
The DPR is organised to allow the VXI to perform D8, D16 or D32 cycles, byte
swapping buffers are included for this purpose. The DPR access time is 20ns, and
the TIMs are connected to this DPR through fast (approximately 5ns) buffers. This
allows ‘C4x accesses to be performed with one- wait -state. The DPR is decoded at
TIM addresses 0xDF000000 and upward (on ‘C4x STRB1). Extra memory can be
added using the DPR expansion site. TIM access to this DPR can be zero- wait-
state if 12ns devices are used.
The bi-directional FIFO consists of two separate FIFOs, one for incoming and one
for outgoing data. The FIFOs can operate concurrently, although the Hewlett
Packard interface is not full duplex.
Access to the global resources is selected by arbitration state machines. Two
arbiters are present, one controlling access to the FIFO, and the other accesses to the
RAM and VXI bus and board control registers. The relevant resource is left granted
to the last resource master after the cycle has finished. Arbitration only occurs when
two (or more) possible bus masters are requesting the same resource. Arbitration
takes two ‘C4x cycles.
The other Global Bus Resources are VXI bus master access and the board control
registers. Because VXI bus arbitration and Global Bus Resource arbitration are
separate, a deadlock situation can occur. This deadlock isonlypossible when a TIM
starts a VXI bus master cycle around the same time that another VXI bus master
starts a cycle to access the SMT301. This situation is resolved by signaling ‘Bus
Error’ to the existing VXI bus master, which is forced to abort its’ VXI bus cycle.
Thiscycle may bere-tried after ashort delay(a few microseconds) to allow the TIM
VXI cycle to complete. This possibility must be taken into account when designing
system software.
3.1 ‘C4x Comm-port
The ‘C4x VXI interface, is designed to allow the VXI to perform D16 or D32
cycles, to access the comm-port interface register. These accesses are converted to
the correct protocol for communicating via a ‘C4x comm-port. This logic and
associated circuitry includes double buffering on reads and writes negating the need
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for an external FIFO. The comm-port which is connected to this interface can be
switched to either of the two TIMs which have global access (TIM1 or TIM5).
A full duplex comm-port pipeline is hardwired between all of the TIMs, with TIM
sites 1 and 5 as the pipeline ends. These comm-ports are unbuffered for maximum
speed. All other TIM comm-ports are routed unbuffered to a link patch area, as are
the 8 buffered front panel comm-ports.
3.2 JTAG
A Texas Instruments Test Bus Controller (TBC) is used to control the JTAG daisy
chain between TIMs. This device is accessed from the VXI as a D16 operation only.
3.3 Interrupts
A single FPGA interrupt controller coordinates all interrupts. It contains a status
register showing unmasked interrupt sources, and 3 mask registers. These allow the
interrupt sources to be masked, before they are logically ORed, to generate 3
separate interrupt inputs, one for each of the global TIM sites and one for the VXI
bus.
A VXI interrupt, with programmablelevel, can be generated byeither global access
TIM. From each of these TIMs, the IIOF0 signal is connected to the interrupt
FPGA, and the assertion of this line generates the interrupt if it is unmasked. The
interrupt is cleared by the VXI master, when it masks the source of the interrupt.
The FIFO flags appear as interrupt sources for all three interrupt receivers. The
Global TIM sites have VXI bus error as an interrupt source. The VXI bus also has
the JTAG controller and the TIM IIOF0 outputs as interrupt sources.
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4 VXI Interface
The VXI interface uses the P1 connector and the centre row of the P2 connector for
additional date and address lines. The interface forms a complete D8/16/32
master/slave. The card does not support slot 0 operation, block transfers or
unaligned transfers.
4.1 VXI Slave Interface
VXI address decoding is selected by the setting of the VXI base address
configuration register. The base address in VXI A32 space of the DPR is separate
to the JTAG and Link Interface and Control registers, (see next section).
Any expansion DPR fitted appears in the VXI memory map above the DPR already
presenton the board. Allof these DPR areas are accessible by the VXI master at the
same speed as the TIM sites.
4.2 VXI Master Interface
The card can support D8, D16 and D32 transfers in A16, A24 and A32 address
spaces. The TIM global data bus signals drive the VXI data bus through buffers but
no byte or word swapping is performed. That is a D8 transfer to VXI address
0x0000 would need the significant data to be in the ‘C4x data bits 7..0. A D8
transfer to address 0x0001wouldneed the significant data tobe in the‘C4x data bits
15..8. etc.
No support is provided for accessing words or longwords across longword
boundaries. i.e., all transfers must be within longword boundaries.
The ‘C4x address lines A0..A21 drive the VXI address lines A2..23. The VXI DS
signals and the VXI address bits A1, A24-31, AM0-5, LWORD are set by the
contents of Control register 4. This requires the use of a 4M Word ‘C4x address
region for VXI master access.
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5 VXI Interface Registers
The VXI specification defines a register block within A16 address space which is
used for control, status and board set-up. These registers are shown below:
Offset Register description
00 ID register
02 Device type
04 Status / Control
06 DPR Offset
08 Sub-class Offset register
0A - 1D Sub-class dependent registers (unused)
1E Sub-class register
20 - 3F Sub-class dependent registers (unused)
The address of this register block is defined by an 8-bit DIL switch (LK1). They are
accessed in A16 address space. The top two address lines (A14 and A15) must be
‘1’. The base address (set on the switches) is compared to address bits A6 to A13.
The address bits A1 to A5 select which register to access. Switch 1 corresponds to
A13 and switch 8 to A6. The switch must be set to ‘ON’ for the corresponding
address bit to be recognised as 0.
Switch VXI Address Bit
1 A13
2 A12
3 A11
4 A10
5A9
6A8
7A7
8A6
For example:
Address 0xC000 = All on.
Address 0xD000 = All on except switch 2
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Address 0xF800 = All on except switches 1,2,3.
Address 0xFFC0 = All off.
The VXI address modifiers must be set to 0x29 or 0x2D as these define an A16
transfer.
5.1 VXI ID Register (00)
The bit definitions for this register are:
Bit Definition
11..0 Manufacturer ID (set to 123 decimal
13..12 Address spaces 01 - A16/A32
15..14 Device classes 01 - extended (SMT301 is extended)
Always reads as 507B hex.
5.2 VXI Device Type Register (02)
The bit definitions for this register are:
Bit Definition
11..0 Model code (set to 301 decimal)
15..12 Required memory ‘m’ = 0 to 15
With 1MByte of SRAM, always reads as B12D hex.
5.3 VXI Status Register (04)
The bit definitions for the read only status register are:
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Bit Definition
0..1 Device dependent ( not used)
2Passed self tests (always asserted)
3Ready (connected to TIM CONFIG line)
4TIM config (normally read as C00C Hex)
5 .. 13 Device dependent ( not used)
14 - MOD ID line status (inverted MOD ID)
15 A32 active
5.4 VXI Control Register (04)
The bit definitions for the write only control register are:
Bit Definition
0Reset (set to reset whole SMT301)
1Sysfail inhibit(sysfail not implemented)
14..2 Device dependent (not used)
15 A32 enable
A32 enable MUST be set to allow A32 access to the rest of the board.
5.5 VXI DPR Offset Register (06)
This 16-bit register defines the base address of the DPR (and DPR expansion) for
A32 addressing modes. In A32 mode, all ‘m’ bits are compared to VXI address
signals A16..31. The number of significant bits is ‘m’, and is specified in the
‘Device Type’ register.
5.6 VXI Sub-class Offset Register (08)
This 16-bit register is used to set the base address (in 256 byte blocks) of the ‘Other
Peripherals’ (JTAG, Link interface, control register etc.). This base address is
compared to the incoming A32 address bits 8-23, while bits 24-31 are compared to
FF hex. A match decodes a 256 byte space which is further decoded to access the
‘Other Peripherals’.
5.7 VXI Sub-class Register (1E)
The bit definitions for this 16-bit read only register are given below:
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Bit Definition
11..0 Manufacturer ID (set to 123 decimal)
14..12 Manufacturer sub-class (set to 001)
15 0 - normal
Always reads as 107B hex.
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6 Control and Status Registers
There are 5 control registers:
6.1 Control Registers 1 and 2 = TIM Site 1 and 5
Interrupt Masks
TheFIFO flagscan be programmed to produce an interrupt which goes to TIM sites
1 and 5. The VXI bus error signal can also generate a TIM interrupt. Each TIM site
has its own register which is accessible to both the VXI bus and the TIMs. The
registers are the general control register 1 for TIM site 1, and general control
register 2 for TIM site 5. Note that ‘VXI Bus Error’ is latched by either of the bit 8
masks below. Therefore both must be cleared to unlatch ‘VXI Bus Error’.
Bit Function
8VXI bus error
7FIFO out full
6FIFO out almost full
5FIFO out almost empty
4FIFO out empty
3FIFO in full
2 FIFO in almost full
1FIFO in almost empty
0FIFO in empty
General Control Register 1 (TIM1)
Bit Function
8VXI bus error
7FIFO out full
6FIFO out almost full
5FIFO out almost empty
4 FIFO out empty
3FIFO in full
2FIFO in almost full
1FIFO in almost empty
0FIFO in empty
General Control Register 2 (TIM 5)
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6.2 Control Register 3 = VXI Interrupt Masks
Each of the two TIM sites 1 and 5 can cause an interrupt to the VXI system. The
interrupt level is selected by bits 12 ..10 of Control Register 4.. In addition to the
IIOF0 lines causing a VXI interrupt, the FIFO flags can also generate a VXI
interrupt.
These can be enabled within the general control register 3 bits, described below.
Bit Function
10 TIM 5 IIOF0
9 TIM 1 IIOF0
8JTAG
7FIFO out full
6FIFO out almost full
5FIFO out almost empty
4FIFO out empty
3FIFO in full
2FIFO in almost full
1FIFO in almost empty
0 FIFO in empty
General Control Register 3
6.3 Control Register 4 = VXI Bus Master cycle control
This 32-bit control register is defined as the general control register 4, and the
function is described below;
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Bit Function
24 - 31 VXI address lines A24 to A31 during ‘C4x master cycle
18 - 23 Address modifier codes AM0 to AM5 during ‘C4x master cycle
17 VXI LWORD during ‘C4x master cycle
16 VXI A1 during ‘C4x master cycle
15 Link interface switch control (0 = TIM site 1, 1 = TIM site 5)
14 VXI bus request level bit 1
13 VXI bus request level bit 0
12 VXI bus interrupt level request bit 2
11 VXI bus interrupt level request bit 1
10 VXI bus interrupt level request bit 0
9VXI DS1 during ‘C4x master cycle
8VXI DS0 during ‘C4x master cycle
0-7 VXI bus interrupt acknowledge vector
General Control Register 4
If no response from the addressed slave is observed within a fixed time (time-out
period) then the VXI Slot 0 controller will generate a ‘Bus Error’, the ‘C4x cycle
will be terminated and a VXI Bus Error interrupt generated.
6.4 Control Register 5 = General Status Register
A status register is availablefor access by the TIMs and the VXI. Thebit definitions
are shown below;
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Bit Function
10 TIM 5 IIOF0
9TIM 1 IIOF0
8VXI Bus Error (Latched)
7FIFO out full
6 FIFO out almost full
5FIFO out almost empty
4FIFO out empty
3FIFO n full
2FIFO in almost full
1 FIFO in almost empty
0FIFO in empty
General Control Register 5
NOTE:
The FIFO flags are only valid while the FIFOs receive a read/write clock. This is
either provided by a TIM or by the SMT301 itself when no TIM is granted access
to the FIFO bus. During arbitration, this clock may be absent for a maximum of
100ns, during which time the FIFO flags will not be updated.
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7 Dual Port RAM (DPR)
The DPR is composed of 1MByte SRAM. This can beaccessedas D8, D16or D32
via the VXI data bus. It can only be accessed in the A32 address space. The base
address of thismemory isset by the VXI offset register, and it resides on a 1MByte
boundary.
7.1 DPR Expansion
Memory expansion is provided for by the inclusion of a memory expansion
daughter module socket. The memory (or peripheral) associated with this daughter
module can be up to 512MBytes (using DRAMs) and appears in the VXI address
space directly after the 1MByte DPR. This expanded memory option will run at
zero-wait-states, when fitted with very high speed SRAM (12ns or faster).
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8 JTAG Debugging Logic
This device is an SN74ACT8990 Test Bus Controller (TBC). It can only be
accessed with a D16 cycle from the VXI host. The address range for access to this
device is from the base address (specified in the VXI sub class offset register) to the
base address + 0x7F. The following registers are held in of the TBC:
JTAG IN
TBC
JTAG OUT
TIM SITES
S
W
I
T
C
H
S
W
I
T
C
H
TDI
TDO TDI TDO
TDI
TDO
TDI
TDO
TDI
TDO
Figure 2: Routing of TDO and TDI Signals
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Address Register Read/Write
base + 02h JTAG Control 0 R/W
base + 06h JTAG Control 1 R/W
base + 0Ah JTAG Control 2 R/W
base + 0Eh JTAG Control 3 R/W
base + 12h JTAG Control 4 R/W
base + 16h JTAG Control 5 R/W
base + 1Ah JTAG Control 6 R/W
base + 1Eh JTAG Control 7 R/W
base + 22h JTAG Control 8 R/W
base + 26h JTAG Control 9 R/W
base + 2Ah JTAG Minor Command R/W
base + 2Eh JTAG Major Command R/W
base + 32h JTAG counter 1 Update 0 R/W
base + 36h JTAG counter 1 Update 1 R/W
base + 3Ah JTAG counter 2 Update 0 R/W
base + 3Eh JTAG counter 2 Update 1 R/W
base + 42h JTAG status 0 R
base + 46h JTAG status 1 R
base + 4Ah JTAG status 2 R
base + 4Eh JTAG status 3 R
base + 52h JTAG Capture 0 R
base + 56h JTAG Capture 1 R
base+ 5Ah JTAG Read Buffer R
base + 5Eh J TAG Write Buffer W
The Test Bus Controller is capable of driving theJTAG scan chain throughall TIM
modules. If a module is not present then the modules SENSE signal is used to
enable (or disable) a tri-state buffer inserted in the TDO/TDI (JTAG Data In and
Data Out) scan chain. An FCT2244 type device is used which allows for the chain
to function correctly with only one module site occupied. Each buffer has a
propagation delay of 5ns maximum, which can limit the maximum JTAG clock
frequency. The internal JTAG clock is 5MHz, which is slow enough tosupport the
delay around a board with a single TIM fitted. External JTAG controllers should
also use 5MHz maximum clock frequency.
Two connectors are present on the front panel. One is the scan chain out, and the
other is the scan chain in. If another motherboard is connected to the scan chain in
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(JTAG IN), or a TI debugger, then the TBC on this motherboard must be disabled.
This is automatically done by a dedicated pin on the JTAG IN connector which
forces the TDI signal for the first TIM site to be derived from this JTAG IN
connector rather than the on board TBC. Similarly, if the JTAG OUT connector is
connected to another motherboard’s JTAG IN connector, then the TDO signal
returned to both the on board TBC and the JTAG IN connector, will be derived
from the JTAG OUT connector.
This diagram shows the routing of the TDO and TDI signals. The top selector is
controlled by the presence of the JTAG OUT connector, and the lower selector is
controlled by the JTAG IN connector. If another JTAG controller is plugged into
the JTAG IN socket, TDI1 into the local TBC is pulled low so that software can
determine if the TBC is the local JTAG controller or not.
The JTAG IN connector (J34) has the following signals:
TDI, TDO, TRST, TMS, TCK, TCK_RET, EMU0, EMU1, GND, PD(+5v),
JTOUT_DET. The JTOUT_DET signal is pulled up on the motherboard, and if a
JTAG OUT from one motherboard is connected to the JTAG IN then a
corresponding GND pin on the JTAG OUT connector will pull JTOUT_DET low,
to signal the TBC as described above. This connector also contains a reset_in signal
and the config signal (both of which may be disabled by removing a jumper).
These details can all be found in the table in the section describing the JTAG front
panel connections.
The JTAG OUT connector (J35) has the following signals:
TDI, TDO, TRST, TMS, TCK, TCK_RET, EMU0, EMU1, GND, SENSE.
The SENSE line is pulled down on the motherboard, and thus if the JTAG OUT is
connected to another motherboard’s JTAG IN then the SENSE line is pulled high
by the connection to PD(+5v). This configures the other selector as described
above. This connector also contains a reset_out signal and the config signal. All
outputs and inputs from and to the JTAG IN and OUT connectors are passed
through buffers, except CONFIG which is a global open collector signal. Both the
JTAG in and out connectors are 3M 20-way SCSI 2 type, part number
10220-5212JL.
These details can be found in the table in the section describing the JTAG front
panel connections.
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