Sundance Spas SMT327 User manual

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
SMT327
Compact PCI 4 SLOT MOTHERBOARD
User Guide

Preliminary Page 2of 2SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
SMT327
User Guide Contents
1. INTRODUCTION.....................................................................................................................................................................4
1.1 FEATURES OF THE SMT327.............................................................................................................................................4
2. INSTALLATION......................................................................................................................................................................5
3. ARCHITECTURAL OVERVIEW ..........................................................................................................................................6
4. PATCH AREA ARCHITECTURE. ........................................................................................................................................7
5. FRONT PANEL CONFIGURATION....................................................................................................................................9
6. BUFFERED COMMUNICATION PORTS........................................................................................................................10
7. JTAG INPUT & OUTPUT PORTS....................................................................................................................................11
8. FMS CONNECTORS (INTERNAL COMMUNICATION PORTS).............................................................................13
9. REGISTERS...........................................................................................................................................................................14
9.1 COMPORT REGISTERS (OFFSET 10H)............................................................................................................................14
9.2 CONTROL REGISTER (OFFSET 14H)..............................................................................................................................15
9.3 STATUS REGISTER (OFFSET 14H)..................................................................................................................................16
9.4 INTERRUPT CONTROL REGISTER (OFFSET 18H)........................................................................................................17
9.5 TEST BUS CONTROLLER-TBC (OFFSETS 80H-AFH)...................................................................................................17
10. BRIDGE -C40 OPERATION...........................................................................................................................................19
10.1 8.1. FIFO..........................................................................................................................................................................19
10.2 8.2. PCI ADDRESS...........................................................................................................................................................20
10.3 8.3. C40 CONTROL REGISTER.......................................................................................................................................20
11. PHYSICAL CHARACTERISTICS..................................................................................................................................21
11.1 POWER CONSUMPTION................................................................................................................................................21
11.2 BOARD DIMENSIONS.....................................................................................................................................................21
Figure 1 Motherboard Architecture......................................................................................................6
Figure 2 Patch Area Layout ...............................................................................................................7
Figure 3 Front Panel .........................................................................................................................9
Table 1 Buffered Communication Port ...............................................................................................10
Table 2 JTAG Slave Port (Input)........................................................................................................11
Table 3 JTAG Master Port (Output)...................................................................................................12
Table 4 FMS Connector...................................................................................................................13

Preliminary Page 3of 3SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Figure 4 Master Mode Interface........................................................................................................19

Preliminary Page 4of 4SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
1. Introduction
This document is the user guide for the Sundance SMT327 TIM Carrier for CompactPCI. The board is 6U
high and 8T wide (double width) to accommodate various TIM’s.
1.1 Features of the SMT327
•Fully compliant with CompactPCI specification.
•Four TIM slots
•Two internal communication port pipelines
•TIM to TIM communication ports are non-buffered for highest speed
•All 6 front panel communication ports are fully buffered
•On board JTAG debugging circuit -accessed from PCI -supports Code Composer
•External JTAG access with master and slave ports
•Master mode for TIM slot 0 allows global bus access to PCI memory space
•C40-as-master transfers to/from PCI -better than 43Mbytes/s @ 60MHz
•Host communications port with > 10Mbytes/s performance
•Software compatible with the SMT320 PCI Tim Carrier
•3.3 V Available to all TIM positions

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
2. Installation
The SMT327 requires no switch or link configuration prior to installation.
It is assumed that 3L Parallel C is already installed on the host system.
A TIM should be fitted to the TIM1 position in order to run the installation test and in general a TIM should
always be fitted to this position in order to provide an H1 clock to the PCI bridge.
NOTE
All installation directions in this document refer to the 3L support programs and environment.1
NOTE
•Insert a TIM card into TIM site 1. With the power to the host system switched off and taking anti-static
precautions, (e.g., wearing an anti-static earth strap), plug the SMT327 into the PCI slot. Ensure that
the SMT327 is located correctly.
•Ensure that the carrier board environment variables are set up correctly for running 3L’s Parallel C TIS
loader program. (see 3L’s C40 Technical Note 62).
TISLINK=SMT320,INDEX:0,DEVICE:0327.
•A new 3L TIS loader program for Windows ‘95, TIS_WD32.EXE, is supplied with the SMT327. This
must be copied into your 3L installation directory, usually TIC2V0:
copy a:\tis_wd32.exe c:\tic2v2\tis.exe
You will be requested if you wish to overwrite the original in this directory. This is required as the
present version of TIS is not a protected mode program. There is also a DOS4GW.EXE which must be
copied to this directory.
•At the DOS prompt run the C40worm utility and confirm that the TIM in TIM site 1 has been detected.
To run C40worm type:
C40worm
The program should report back the number of processors on the SMT327. For example:
1 processor found:
root processor: TMS320C44 with 1MW of off-chip memory (4MB)
If C40worm fails to report back any information check the correct carrier board configuration has been
assigned in the environment variables, e.g. TISLINK, TISROOT, etc.
Refer to your 3L User Guide for further information on executing C40worm.
13L Parallel C compiler and tools from 3L Limited, 86/92 Causewayside, Edinburgh, EH9 1PY, Scotland.
Reference: http://www.threel.co.uk/technotes/03700/03700.htm

Preliminary Page 6of 6SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
3. Architectural Overview
The SMT327 is a CompactPCI ® version of the SMT320 PCI TIM carrier for standard PCI systems. It
maintains 100% software compatibility with the Sundance SMT320 and Alpha Data ADC-C40-PCI
meaning that existing applications can be easily migrated.
The SMT327 provides 4 TIM positions which can accommodate either single width or double width modules. A dedicated pipe is
hard wired using communication ports 2 and 5 of each TIM, in common with the SMT320. In addition, all other communication
ports are available using FMS-14 connectors for inter-TIM connections.
Two further pipes using ports 0/3 and 1/4 of each TIM can be broken to allow other topologies to be constructed. These pipes
use logic to detect when a cable is inserted to avoid contention between the pipe and the desired connection.
PCI Bus
3401
25
TIM 1
3401
25
TIM 2
3401
25
TIM 3
3401
25
TIM 4
FMS Connector
Patch Area FMS Connector Patch Area
Front Panel Buffered
Ports Front Panel Buffered Ports
0 1 3 2 4 5
PCI-C40
Bridge
Initiator
FIFO &
Control Global Bus
Target
Control
Target
Comm-port
IIOF/Reset
Target
JTAG I/F
ACT8990
TBC
Front Panel
JTAG I/O
All TIMS
= Quick Switch Isolator
Figure 1Motherboard Architecture

Preliminary Page 7of 7SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
4. Patch Area Architecture.
The layout of the SMT327 is shown below. Two patch areas, upper and lower, allow each pair of TIM’s to be interconnected.
Between these areas, three routing channels are provided to allow additional communication port connections between each
pair of TIM’s.
Each patch area has 3 front panel FMS connectors that allow a communication port to be buffered to a front panel connector.
Buffered communication ports can be used between SMT327 boards or other compatible systems at distances up to 0.8m.
The diagram below details the layout of the TIM slots and potential routing of the flat flexible cables.
Front Panel Area
T1C0-O
FP0-O
J1
J2
TIM 4
TIM 3
TIM 2 TIM 1
TBC
Tunnel C
T1C3-I Tunnel C
Tunnel B
Tunnel B
Tunnel A
Tunnel A
T2C0-O
T2C3-I
FP3-IFP1-O
T2C1-O T2C4-I
T1C4-IT1C1-O
FP4-IFP2-OFP5-I
T3C3-I T3C0-O T4C3-I T4C0-O
T3C1-O
T3C4-I
T4C1-O
T3C4-I
Figure 2Patch Area Layout

Preliminary Page 8of 8SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Note that when connecting communication ports with the FMS cables, to ensure pin 1 is connected topin
1 on the alternative communication port. One end of the cable must be inserted opposite to the other, i.e.
on one the blue backing must be facing out and on the other the silver of the connectors must be facing
outwards.
The connection between internal communication ports of the form TxCy must use the rule that RTO and
RTI ports are the only valid connection. Like ports must never be connected using FMS cables as these
ports are unprotected (except for some series termination) with damage a likely outcome.
Connections in the patch area to the front panel FMS connectors, FPn-I/O, must match RTO to RTO and
RTI to RTI as these ports are simply buffers to the outside world. The following table list some valid
connections.
T1C3-I to T2C0-O
T1C0-O to Tunnel-A(bottom) & Tunnel-A(top) to T4C3-I
T2C1-O to FP2-O
The rules for communication port matching must always be followed through Tunnel-n connections.

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
5. Front Panel Configuration
The front panel conforms to IEEE 1101.1 and 1101.10. This provides for EMC compatibility and
mechanical insertion and extraction. The layout in terms of JTAG and communication port layout is as
shown below.
3
O
U
T
I
N
0
JTAG
SMT327
52
41
Figure 3Front Panel
The layout of the front panel connections is organised to match the communications port of a Texas C40
processor. The left side ports, 0-2, are Reset To Out (RTO) ports by default and represent a similarly
numbered port within the SMT327. The right side ports, 3-5, are Reset To In (RTI).
IMPORTANT. In all system configurations, RTO ports should only be connected to RTI ports. This applies
to internal flat cable connections as well as buffered port connections. Because of the high current drivers
used in the buffered ports, protection is built in and will cause the drivers to switch off if like ports are
connected together.
In systems with buffered communication port connections between SMT327 boards it is necessary to
connect the JTAG ports. In this case, a 20 way cable between a JTAG-IN and a JTAG-OUT is required.
The SMT327 board designated as “ROOT” for 3L server purposes should also be the JTAG master with no
connection to its JTAG-IN port.

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
6. Buffered Communication Ports
Each front panel buffered port has the following pin out and uses a 3M MDR style 26 way connector.
These buffered communications ports are compatible with the Sundance SMT328 VME TIM carrier.
Pin Twisted Pair Signal
11STRB
21GND
32RDY
42GND
53REQ
63GND
74ACK
84GND
95DIR_OUT
10 5GND
11 6DIR_IN
12 6GND
13 7D0
14 7D1
15 8D2
16 8D3
17 9D4
18 9D5
19 10 D6
20 10 D7
21 11 VCC
22 11 GND
23 12 /RESET_OUT
24 12 GND
25 13 SPARE
26 13 GND
SHELL -SHIELD
Table 1Buffered Communication Port

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
7. JTAG Input & Output Ports
Both input and output ports for JTAG are provided, designed to be compatible with the SMT328 and
SMT301 motherboards.
The JTAG interface is designed to operate at a maximum 10MHz across up to 4 SMT327 motherboards.
By default this frequency is 8.33MHz (PCI_CLK/4) or less, depending on the PCI_CLK on the host.
The JTAG ports of the SMT327 auto-detect connections and will by default become a JTAG master with
no connections or with a slave SMT327 connected to the JTAG-OUT port. An SMT327 that detects a
cable connection on its JTAG-IN port automatically becomes a slave and routes the TAP port accordingly.
Pin Signal Direction Description
1TDI IN JTAG data in
2GND
3TDO OUT JTAG data out
4GND
5TMS IN JTAG Test mode select
6GND
7TCK IN JTAG clock, up to 10MHz
8GND
9TCK_RET OUT JTAG clock return
10 GND
11 -TRST IN JTAG Reset
12 GND
13 -RESET IN Board Reset in
14 PD OUT Presence detect, +5V 1A
fused
15 -DETECT IN Detect external JTAG
controller when grounded
16 CONFIG OPEN COLL Global open collector C4x
CONFIG
17 EMU0 OUT Buffered EMU0 output
18 EMU1 OUT Buffered EMU1 output
19 SPARE1
20 SPARE2
Table 2JTAG Slave Port (Input)

Preliminary Page 12 of 12 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Pin Signal Direction Description
1TDO OUT JTAG data out
2GND
3TDI IN JTAG data in
4GND
5TMS OUT JTAG Test mode select
6GND
7TCK OUT JTAG clock 10MHz
8GND
9TCK_RET IN JTAG clock return
10 GND
11 -TRST OUT JTAG Reset
12 GND
13 -RESET OUT Board Reset out
14 PD IN Presence detect when pulled
high
15 -DETECT OUT Detect external JTAG
controller when grounded
16 CONFIG OPEN COLL Global open collector C4x
CONFIG
17 EMU0 IN EMU0 input
18 EMU1 IN EMU1 input
19 SPARE1
20 SPARE2
Table 3JTAG Master Port (Output)

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
8. FMS Connectors (Internal Communication Ports)
The FMS connectors utilise flat flexible cable for internal board communication links. These 14 pin
connectors are configured as shown below.
FMS Pin Signal FMS Pin Signal
1DIS- 1GND
2D0 2D0
3D1 3D1
4D2 4D2
5D3 5D3
6D4 6D4
7D5 7D5
8D6 8D6
9D7 9D7
10 REQ 10 REQ
11 ACK 11 ACK
12 STRB 12 STRB
13 RDY 13 RDY
14 GND 14 DIS-
RTI Ports RTO Ports
Table 4FMS Connector
Note that these connectors have sense pins to detect when a cable is inserted. This avoids contention
between the intended connection and the pipe.

Preliminary Page 14 of 14 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
9. Registers
In target mode, the SMT327 is accessed by a host device across the PCI bus. This allows access to the
target mode registers. The operating system or BIOS will normally allocate a base address for the target
mode registers of each SMT327. Access to each register within the SMT327 is then specified by this
base address and the offset shown in the table below.
The I/O address space is decoded as shown in the table below.
Offset Register(Write) Register(Read) Width
0--
+4 --
+8 --
+0C --
+10 COMPORT_OUT COMPORT_IN 32
+14 CONTROL STATUS 32
+18 INT_CONTROL 32
+1C --
+20 to +3F Not used Not used
+40 to +7E Mailbox Write Mailbox Read 32
+80 to +AF TBC Write TBC Read 16
9.1 Comport Registers (Offset 10h)
The host is connected to the first TIM site using comport 3. This port is bi-directional and will
automatically switch direction to meet a request from either the host or the C40. Both input and output
registers are 32 bits wide. Data can only be written to COMPORT_OUT when STATUS[OBF] is 0. Data
received from the C40 is stored in COMPORT_IN and STATUS[IBF] is set to 1. Reading COMPORT_IN
will clear STATUS[IBF] and allow another word to be received from the C40.

Preliminary Page 15 of 15 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
9.2 Control Register (Offset 14h)
The CONTROL register can only be written. It contains flags which control the boot modes of the first TIM
site.
Boot Control
Note. On PCI system reset, RESET is asserted to all TIM sites.
Bit 7-543210
Name Not used notNMI IIOF2 IIOF1 IIOF0 RESET
RESET Write a 1 to this bit to assert the reset signal to all TIM modules on the
SMT320.
IIOF0
IIOF1,
IIOF2
These bits connect to the corresponding pins on the first TIM site. These
bits are open-drain and can only pull down. If not required before or after
booting they should be written with 1’s.
NotNMI A 0 written to this bit will assert the active low NMI to the TIM1 C40.

Preliminary Page 16 of 16 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
9.3 Status Register (Offset 14h)
The STATUS register can only be read.
OBE IE Set if comport output buffer empty interrupts enabled.
IBF IE Set if comport input buffer full interrupts enabled
TBC IE Set if JTAG interrupts enabled
C40 IE Set if interrupt from TIM1 C40 enabled
OBE INT Set if comport output buffer becomes empty.
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
IBF INT Set if comport input buffer receives a word.
Cleared by writing a 1to the corresponding bit in the interrupt control
register
TBC INT Set when the TBC asserts its interrupt.
Cleared by removing the source of the interrupt in the TBC.
C40 INT Set when the TIM1 C40 sets its host interrupt bit.
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
INTA This is a logical OR of bits 7 to 4 in this register gated with each
ones enable bit.
OBF Set when a word is loaded into the comport output register. Cleared
when the word is transmitted to the C40.
IBF Set when a word is received into the comport input register from the
TIM1 C40.
MASTER When set, the comport interface token is owned by the SMT320
bridge.
TBC RDY Reflects the current state of the TBC RDY pin. This bit is active high
and therefore and inversion of the TBC pin.
CONFIG_L Reflects the current state of the CONFIG signal from the TIM1 C40.
Active low.
Bit 31:22 21 20 19 18 17 16
Name XCONFIG_L TBC RDY 0MASTER IBF OBF
Bit 15 14 13 12 11 10 98
Name XXXXXXXINTA
Bit 76543210
Name C40 INT TBC
INT IBF INT OBE INT C40 IE TBC IE IBF IE OBE IE

Preliminary Page 17 of 17 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
9.4 Interrupt Control Register (Offset 18h)
This write-only register controls the generation of interrupts on the PCI bus. Each interrupt source has an
associated enable and clear flag. This register can be written with the contents of bits 7:0 of the Status
Register.
Enable Group
Bit 76543210
Name CLEAR
C40 INT 0CLEAR IBF INT CLEAR OBE
INT
C40 IE TBC IE IBF IE OBE IE
IBF IE Input Buffer Full Interrupt Enable. Allows an interrupt to be generated
when the host comport input register is loaded with data from the C40.
OBE IE Output Buffer Empty Interrupt. Allows an interrupt to be generated when
the host comport register has transmitted its contents.
TBC IE Test Bus Controller Interrupt Enable. Interrupts from the Texas JTAG
controller are enabled when set.
C40 IE C40 Interrupt Enable. Allows a programmed interrupt to be generated by
the C40 when set.
CLEAR
OBE INT Write a one to this bit to clear the interrupt resulting from a comport output event.
CLEAR
IBF INT Write a one to this bit to clear the interrupt event resulting from comport input.
CLEAR
C40 INT Write a one to this bit to clear down the C40 INT event.
The JTAG controller which generates TBC INT must be cleared of all interrupt sources in order to clear the
interrupt.
9.5 Test Bus Controller-TBC (Offsets 80h-AFh)
Refer to the Texas 74ACT8990 data manual for register usage.
The clock for the TBC is ½ the PCI clock rate. So for a standard PCI slot this will therefore clock the
74ATC8990 at 16.67 MHz approximately.
The offsets and write / read capability of all TBC registers is shown below.

Preliminary Page 18 of 18 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Offset (hex) Write Read
80 Control0 Control0
82 Control1 Control1
84 Control2 Control2
86 Control3 Control3
88 Control4 Control4
8A Control5 Control5
8C Control6 Control6
8E Control7 Control7
90 Control8 Control8
92 Control9 Control9
94 Minor Command Minor Command
96 Major Command Major Command
98 Counter 1 Update 0 Counter 1 Update 0
9A Counter 1 Update 1 Counter 1 Update 1
9C Counter 2 Update 0 Counter 2 Update 0
9E Counter 2 Update 1 Counter 2 Update 1
A0 -Status 0
A2 -Status 1
A4 -Status 2
A6 -Status 3
A8 -Capture 0
AA -Capture 1
AC -Read Buffer
AE Write Buffer -
The organisation of the TBC registers is of a stack of 16 bit registers aligned to 16 bit boundaries. They
are however accessed using both lower and upper 16 bits of the PCI bus.
IMPORTANT. Only 16 bit I/O operations should be used to access the TBC registers and each transfer
must be WORD aligned.
The state of the TBC RDY signal can be tested in the Status register.

Preliminary Page 19 of 19 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
10. Bridge -C40 Operation.
The first TIM position on the SMT327 makes use of the global bus to allow the C40 to read and write the
entire PCI address space. Burst mode and single transfers can be used to access the PCI address
space.
Figure 4Master Mode Interface
The C40 can access any PCI location but in should be noted that data written and read will always be
long word aligned and 32 bits wide. The table below illustrates the available registers.
Address Register(Write) Register(Read) Width
C0000000 FIFO FIFO 32
C0400000 PCI Address -32
C0800000 Control -2
10.1 8.1. FIFO
The SMT327incorporates 16 deep x 32 wide FIFO buffers on both read and write paths between the C40
and PCI bus. The FIFO is only effective when burst mode is enabled in the control register. With burst
mode disabled, the bridge will request the PCI bus for each word transferred.
With burst mode enabled, data written to the empty FIFO will be absorbed until 16 words make the FIFO
full. This state will trigger a PCI burst write of 16 words in length thus transferring 64 bytes to the
destination. The FIFO can be written with the next 16 words during the PCI burst transaction to maintain
throughput. The C40 may incur wait states if the FIFO becomes full during this time.
For burst mode read transactions, reading from the empty FIFO will trigger a PCI burst of 16 words from
source memory, filling the FIFO with 64 bytes of data. The C40 will be able to read the first word of data
as soon as it is loaded into the FIFO from the PCI bus.
32 bit
Add
Ctrl
FIFO
16 x32
FIFO
16 x32
PCI
ADIO
Add
Data
C40
Decoder

Preliminary Page 20 of 20 SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
10.2 8.2. PCI Address
The PCI address register is a 30 bit counter loaded from bits D31:2 of the C40 data bus. The counter
output is a 32 bit address with bits 1:0 always at logic 0.
The PCI Address register must be written with a valid PCI address prior to writing or reading from the
FIFO. The value written into the address register loses the bottom two bits in order to match the PCI bus
mode used by the bridge. The address counter increments on every valid PCI to track the source or
destination pointer in the event of a target disconnect. The bridge may disconnect during burst transfers
but this will be transparent to the C40.
10.3 8.3. C40 Control Register
The Control register provides the C40 interface with control over the generation of interrupts on the PCI
bus. Writing a 1 to the PCI INT bit will generate an interrupt on the PCI bus via the INTA line. The interrupt
is cleared / acknowledged through the target interrupt control register.
Bit(s) 31-24 23:16 15:2 10
Name 000PCI INT BURST