Sundance Spas SMT327 User manual

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
SMT327
Compact PCI 4 SLOT MOTHERBOARD
User Guide

Preliminary Page 2of 2SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
SMT327
User Guide Contents
1. INTRODUCTION.....................................................................................................................................................................4
1.1 FEATURES OF THE SMT327.............................................................................................................................................4
2. INSTALLATION......................................................................................................................................................................5
3. ARCHITECTURAL OVERVIEW ..........................................................................................................................................6
4. PATCH AREA ARCHITECTURE. ........................................................................................................................................7
5. FRONT PANEL CONFIGURATION....................................................................................................................................9
6. BUFFERED COMMUNICATION PORTS........................................................................................................................10
7. JTAG INPUT & OUTPUT PORTS....................................................................................................................................11
8. FMS CONNECTORS (INTERNAL COMMUNICATION PORTS).............................................................................13
9. REGISTERS...........................................................................................................................................................................14
9.1 COMPORT REGISTERS (OFFSET 10H)............................................................................................................................14
9.2 CONTROL REGISTER (OFFSET 14H)..............................................................................................................................15
9.3 STATUS REGISTER (OFFSET 14H)..................................................................................................................................16
9.4 INTERRUPT CONTROL REGISTER (OFFSET 18H)........................................................................................................17
9.5 TEST BUS CONTROLLER-TBC (OFFSETS 80H-AFH)...................................................................................................17
10. BRIDGE -C40 OPERATION...........................................................................................................................................19
10.1 8.1. FIFO..........................................................................................................................................................................19
10.2 8.2. PCI ADDRESS...........................................................................................................................................................20
10.3 8.3. C40 CONTROL REGISTER.......................................................................................................................................20
11. PHYSICAL CHARACTERISTICS..................................................................................................................................21
11.1 POWER CONSUMPTION................................................................................................................................................21
11.2 BOARD DIMENSIONS.....................................................................................................................................................21
Figure 1 Motherboard Architecture......................................................................................................6
Figure 2 Patch Area Layout ...............................................................................................................7
Figure 3 Front Panel .........................................................................................................................9
Table 1 Buffered Communication Port ...............................................................................................10
Table 2 JTAG Slave Port (Input)........................................................................................................11
Table 3 JTAG Master Port (Output)...................................................................................................12
Table 4 FMS Connector...................................................................................................................13

Preliminary Page 3of 3SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Figure 4 Master Mode Interface........................................................................................................19

Preliminary Page 4of 4SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
1. Introduction
This document is the user guide for the Sundance SMT327 TIM Carrier for CompactPCI. The board is 6U
high and 8T wide (double width) to accommodate various TIM’s.
1.1 Features of the SMT327
•Fully compliant with CompactPCI specification.
•Four TIM slots
•Two internal communication port pipelines
•TIM to TIM communication ports are non-buffered for highest speed
•All 6 front panel communication ports are fully buffered
•On board JTAG debugging circuit -accessed from PCI -supports Code Composer
•External JTAG access with master and slave ports
•Master mode for TIM slot 0 allows global bus access to PCI memory space
•C40-as-master transfers to/from PCI -better than 43Mbytes/s @ 60MHz
•Host communications port with > 10Mbytes/s performance
•Software compatible with the SMT320 PCI Tim Carrier
•3.3 V Available to all TIM positions

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
2. Installation
The SMT327 requires no switch or link configuration prior to installation.
It is assumed that 3L Parallel C is already installed on the host system.
A TIM should be fitted to the TIM1 position in order to run the installation test and in general a TIM should
always be fitted to this position in order to provide an H1 clock to the PCI bridge.
NOTE
All installation directions in this document refer to the 3L support programs and environment.1
NOTE
•Insert a TIM card into TIM site 1. With the power to the host system switched off and taking anti-static
precautions, (e.g., wearing an anti-static earth strap), plug the SMT327 into the PCI slot. Ensure that
the SMT327 is located correctly.
•Ensure that the carrier board environment variables are set up correctly for running 3L’s Parallel C TIS
loader program. (see 3L’s C40 Technical Note 62).
TISLINK=SMT320,INDEX:0,DEVICE:0327.
•A new 3L TIS loader program for Windows ‘95, TIS_WD32.EXE, is supplied with the SMT327. This
must be copied into your 3L installation directory, usually TIC2V0:
copy a:\tis_wd32.exe c:\tic2v2\tis.exe
You will be requested if you wish to overwrite the original in this directory. This is required as the
present version of TIS is not a protected mode program. There is also a DOS4GW.EXE which must be
copied to this directory.
•At the DOS prompt run the C40worm utility and confirm that the TIM in TIM site 1 has been detected.
To run C40worm type:
C40worm
The program should report back the number of processors on the SMT327. For example:
1 processor found:
root processor: TMS320C44 with 1MW of off-chip memory (4MB)
If C40worm fails to report back any information check the correct carrier board configuration has been
assigned in the environment variables, e.g. TISLINK, TISROOT, etc.
Refer to your 3L User Guide for further information on executing C40worm.
13L Parallel C compiler and tools from 3L Limited, 86/92 Causewayside, Edinburgh, EH9 1PY, Scotland.
Reference: http://www.threel.co.uk/technotes/03700/03700.htm

Preliminary Page 6of 6SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
3. Architectural Overview
The SMT327 is a CompactPCI ® version of the SMT320 PCI TIM carrier for standard PCI systems. It
maintains 100% software compatibility with the Sundance SMT320 and Alpha Data ADC-C40-PCI
meaning that existing applications can be easily migrated.
The SMT327 provides 4 TIM positions which can accommodate either single width or double width modules. A dedicated pipe is
hard wired using communication ports 2 and 5 of each TIM, in common with the SMT320. In addition, all other communication
ports are available using FMS-14 connectors for inter-TIM connections.
Two further pipes using ports 0/3 and 1/4 of each TIM can be broken to allow other topologies to be constructed. These pipes
use logic to detect when a cable is inserted to avoid contention between the pipe and the desired connection.
PCI Bus
3401
25
TIM 1
3401
25
TIM 2
3401
25
TIM 3
3401
25
TIM 4
FMS Connector
Patch Area FMS Connector Patch Area
Front Panel Buffered
Ports Front Panel Buffered Ports
0 1 3 2 4 5
PCI-C40
Bridge
Initiator
FIFO &
Control Global Bus
Target
Control
Target
Comm-port
IIOF/Reset
Target
JTAG I/F
ACT8990
TBC
Front Panel
JTAG I/O
All TIMS
= Quick Switch Isolator
Figure 1Motherboard Architecture

Preliminary Page 7of 7SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
4. Patch Area Architecture.
The layout of the SMT327 is shown below. Two patch areas, upper and lower, allow each pair of TIM’s to be interconnected.
Between these areas, three routing channels are provided to allow additional communication port connections between each
pair of TIM’s.
Each patch area has 3 front panel FMS connectors that allow a communication port to be buffered to a front panel connector.
Buffered communication ports can be used between SMT327 boards or other compatible systems at distances up to 0.8m.
The diagram below details the layout of the TIM slots and potential routing of the flat flexible cables.
Front Panel Area
T1C0-O
FP0-O
J1
J2
TIM 4
TIM 3
TIM 2 TIM 1
TBC
Tunnel C
T1C3-I Tunnel C
Tunnel B
Tunnel B
Tunnel A
Tunnel A
T2C0-O
T2C3-I
FP3-IFP1-O
T2C1-O T2C4-I
T1C4-IT1C1-O
FP4-IFP2-OFP5-I
T3C3-I T3C0-O T4C3-I T4C0-O
T3C1-O
T3C4-I
T4C1-O
T3C4-I
Figure 2Patch Area Layout

Preliminary Page 8of 8SMT327 User Guide
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
Note that when connecting communication ports with the FMS cables, to ensure pin 1 is connected topin
1 on the alternative communication port. One end of the cable must be inserted opposite to the other, i.e.
on one the blue backing must be facing out and on the other the silver of the connectors must be facing
outwards.
The connection between internal communication ports of the form TxCy must use the rule that RTO and
RTI ports are the only valid connection. Like ports must never be connected using FMS cables as these
ports are unprotected (except for some series termination) with damage a likely outcome.
Connections in the patch area to the front panel FMS connectors, FPn-I/O, must match RTO to RTO and
RTI to RTI as these ports are simply buffers to the outside world. The following table list some valid
connections.
T1C3-I to T2C0-O
T1C0-O to Tunnel-A(bottom) & Tunnel-A(top) to T4C3-I
T2C1-O to FP2-O
The rules for communication port matching must always be followed through Tunnel-n connections.

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
5. Front Panel Configuration
The front panel conforms to IEEE 1101.1 and 1101.10. This provides for EMC compatibility and
mechanical insertion and extraction. The layout in terms of JTAG and communication port layout is as
shown below.
3
O
U
T
I
N
0
JTAG
SMT327
52
41
Figure 3Front Panel
The layout of the front panel connections is organised to match the communications port of a Texas C40
processor. The left side ports, 0-2, are Reset To Out (RTO) ports by default and represent a similarly
numbered port within the SMT327. The right side ports, 3-5, are Reset To In (RTI).
IMPORTANT. In all system configurations, RTO ports should only be connected to RTI ports. This applies
to internal flat cable connections as well as buffered port connections. Because of the high current drivers
used in the buffered ports, protection is built in and will cause the drivers to switch off if like ports are
connected together.
In systems with buffered communication port connections between SMT327 boards it is necessary to
connect the JTAG ports. In this case, a 20 way cable between a JTAG-IN and a JTAG-OUT is required.
The SMT327 board designated as “ROOT” for 3L server purposes should also be the JTAG master with no
connection to its JTAG-IN port.

Preliminary
Document Name: User Guide Issue : 01 Rev 02
Product Name: SMT327 Revision Date: 8August,2000
Author: Bill Blyth Original Date: 30 April 1998
6. Buffered Communication Ports
Each front panel buffered port has the following pin out and uses a 3M MDR style 26 way connector.
These buffered communications ports are compatible with the Sundance SMT328 VME TIM carrier.
Pin Twisted Pair Signal
11STRB
21GND
32RDY
42GND
53REQ
63GND
74ACK
84GND
95DIR_OUT
10 5GND
11 6DIR_IN
12 6GND
13 7D0
14 7D1
15 8D2
16 8D3
17 9D4
18 9D5
19 10 D6
20 10 D7
21 11 VCC
22 11 GND
23 12 /RESET_OUT
24 12 GND
25 13 SPARE
26 13 GND
SHELL -SHIELD
Table 1Buffered Communication Port