Teridian 73s1209f User manual

73S1209F

Self-Contained PINpad, Smart Card Reade

IC UART to ISO7816 / EMV Bridge IC

Simplifying System Integration™ DATA SHEET

December 2008

GENERAL DESCRIPTION

The Teridian Semiconductor Corporation 73S1209F is a

versatile and economical CMOS System-on-Chip device

intended for smart card reader applications. More

generally, it is suitable anywhere a UART to ISO-7816 /

EMV bridge function is needed. The circuit is built around

an 80515 high-performance core; it features primarily an

ISO-7816 / EMV interface and a generic asynchronous

serial interface. Delivered with turnkey Teridian embedded

firmware, it forms a ready-to-use smart card reader solution

that can be seamlessly incorporated into any

microprocessor-based system where a serial line is

available.

The solution is scalable, thanks to a built-in I2C interface

that allows to drive external electrical smart card interfaces

such as Teridian 73S8010R/C ICs. This makes the solution

immediately able to support multi-card slots or multi-SAM

architectures.

In addition, the 73S1209F features a 5x6 PINpad interface,

9 user I/Os, 2 LED outputs (programmable current),

multiple interrupt options and an analog voltage input (for

DC voltage monitoring such as battery level detection) that

make it suitable for low-cost PINpad reader devices.

The 80515 CPU core instruction set is compatible with the

industry standard 8051, while offering one clock-cycle per

instruction processing power (most instructions). With a

CPU clock running up to 24MHz, it results in up to 24MIPS

available that meets the requirements of various encryption

needs such as AES, DES / 3-DES and even RSA (for PIN

encryption for instance).

The circuit requires a single 6MHz to 12MHz crystal.

The respective 73S1209F embedded memories are 32KB

Flash program memory, 2KB user XRAM memory, and

256B IRAM memory. Dedicated FIFOs for the ISO7816

UART are independent from the user XRAM and IRAM.

Alternatively to the turnkey firmware offered by Teridian,

customers can develop their own embedded firmware

directly within their application or using Teridian 73S1209F

Evaluation Board through a JTAG-like interface.

Overall, the Teridian 73S1209F IC requires 2 distinct power

supply voltages to operate normally with full support of all

smart card voltages, 1.8V, 3V and 5V. The digital power

supply VDD requires a 2.7V to 3.6V voltage, and the analog

power supply VPC requires typically a 4.75V to 6.0V.

While the VDD is used to power up the CPU core and the

digital functions of the IC, the VPC voltage is used to supply

the proper VCC voltage to the smart card interface: The chip

incorporates an low drop-out linear voltage regulator that

generates the smart card power-supply VCC from the power

supply source VPC.

Embedded Flash memory is in-system programmable

and lockable by means of on-silicon fuses. This makes

the 73S1209F suitable for both development and

production phases.

Teridian Semiconductor Corporation offers with its

73S1209F a very comprehensive set of software

libraries for EMV. Refer to the 73S12xxF Software

User’s Guide for a complete description of the

Application Programming Interface (API Libraries) and

related Software modules.

A complete array of development and programming

tools, libraries and demonstration boards enable rapid

development and certification of readers that meet

most demanding smart card standards.

APPLICATIONS

•UART to ISO-7816 / EMV Bridges

•PINpad smart card readers:

oWith serial connectivity

oIdeal for low-cost POS Terminals) & Digital

Identification (Secure Login, Gov’t ID...)

•SIM Readers in Telecom & Personal Wireless

devices

•Payphones and vending machines

•General purpose smart card readers

ADVANTAGES

•Reduced BOM

•Low-Cost

•Dual power supply required 3.3V and 5V

typical

•Higher performance CPU core (up to 24MIPS)

•Built-in EMV/ISO slot, expandable to multi-

slots

•Powerful In-Circuit Emulation and

Programming

•A complete set of EMV4.1 / ISO-7816

libraries

•Turnkey PC/SC and CCID firmware and host

drivers

oSupported OS: Windows XP, WindowsTM

Mobile; Windows CE; Linux

oOther OS: Contact Teridian Semiconductor

73S1209F Data Sheet DS_1209F_004

2 Rev. 1.2

FEATURES

80515 Core:

•1 clock cycle per instruction (most instructions)

•CPU clocked up to 24MHz

•32kB Flash memory with security

•2kB XRAM (User Data Memory)

•256 byte IRAM

•Hardware watchdog timer

Oscillators:

•Single low-cost 6MHz to 12MHz crystal

•An Internal PLL provides all the necessary clocks

to each block of the system

Interrupts:

•Standard 80C515 4-priority level structure

•9 different sources of interrupt to the core

Power Down Modes:

•2 standard 80C515 Power Down and IDLE

modes

•Extensive device power down mode

Timers:

•(2) Standard 80C52 timers T0 and T1

•(1) 16-bit timer

Built-in ISO-7816 Card Interface:

•Linear regulator produces VCC for the card

(1.8V, 3V or 5V)

•Full compliance with EMV 4.1

•Activation/Deactivation sequencers

•Auxiliary I/O lines (C4 and C8 signals)

•7kV ESD protection on all interface pins

Communication with Smart Cards:

•ISO-7816 UART for protocols T=0, T=1

•(2) 2-Byte FIFOs for transmit and receive

•Configured to drive multiple external Teridian

73S8010x interfaces (for multi-SAM

architectures)

Communication Interfaces:

•Full-duplex serial interface (1200bps to

115kbps UART)

•I

2C Master Interface (400kbps)

Man-Machine Interface and I/Os:

•5x6 Keyboard (hardware scanning,

debouncing and scrambling)

•(9) User I/Os

•Up to 2 programmable current outputs (LED)

Voltage Detection:

•Analog Input (detection range: 1.0V to 2.5V)

•Operating Voltage:

•2.7V to 3.6V Digital power supply

•4.75 to 5.5V Analog, smart card power

supply

Operating Temperature:

•-40°C to 85°C

Package:

•68-pin QFN, 44-pin QFN

Software:

•Turnkey firmware:

oCompliant with PC/SC, CCID, ISO7816

and EMV4.1 specifications

oFeatures a Power Down mode accessible

form the host

oSupports Plug & Play over serial interface

oWindows® XP driver available (*)

oWindows CE / Mobile driver available (*)

oLinux and other OS: Upon request

•Or for custom developments:

oA complete set of ISO-7816, EMV4.1 and

low-level libraries are available for T=0 /

T=1

oTwo-level Application Programming

Interface (ANSI C-language libraries)

(*) Contact Teridian Semiconductor for

conditions and availability

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 3

Table of Contents

1Hardware Description......................................................................................................................... 8

1.1Pin Description.............................................................................................................................. 8 

1.2Hardware Overview .................................................................................................................... 11

1.380515 MPU Core ........................................................................................................................ 11

1.3.180515 Overview............................................................................................................. 11

1.3.2Memory Organization .................................................................................................... 11

1.4Program Security ........................................................................................................................ 16

1.5Special Function Registers (SFRs) ............................................................................................ 18

1.5.1Internal Data Special Function Registers (SFRs).......................................................... 18

1.5.2IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19

1.5.3External Data Special Function Registers (SFRs) ........................................................ 21

1.6Instruction Set............................................................................................................................. 23

1.7Peripheral Descriptions............................................................................................................... 23

1.7.1Oscillator and Clock Generation.................................................................................... 23

1.7.2Power Control Modes .................................................................................................... 27

1.7.3Interrupts........................................................................................................................ 32

1.7.4UART .............................................................................................................................39

1.7.5Timers and Counters ..................................................................................................... 44

1.7.6WD Timer (Software Watchdog Timer) ......................................................................... 46

1.7.7User (USR) Ports........................................................................................................... 49

1.7.8Analog Voltage Comparator .......................................................................................... 51

1.7.9LED Drivers ................................................................................................................... 53

1.7.10I2C Master Interface....................................................................................................... 54

1.7.11Keypad Interface............................................................................................................ 61

1.7.12Emulator Port................................................................................................................. 67

1.7.13Smart Card Interface Function ...................................................................................... 68

1.7.14VDD Fault Detect Function.......................................................................................... 102

2Typical Application Schematics.................................................................................................... 103

3Electrical Specification................................................................................................................... 105

3.1Absolute Maximum Ratings ...................................................................................................... 105

3.2Recommended Operating Conditions ...................................................................................... 105

3.3Digital IO Characteristics .......................................................................................................... 106

3.4Oscillator Interface Requirements ............................................................................................ 106

3.5DC Characteristics: Analog Input ............................................................................................. 106

3.6Smart Card Interface Requirements......................................................................................... 107

3.7DC Characteristics.................................................................................................................... 109

3.8Voltage / Temperature Fault Detection Circuits ....................................................................... 109

4Equivalent Circuits ......................................................................................................................... 110

4.1Package Pin Designation (68-pin QFN) ................................................................................... 117

4.2Package Pin Designation (44-pin QFN) ................................................................................... 118

4.3Packaging Information .............................................................................................................. 119

5Ordering Information ...................................................................................................................... 121

6Related Documentation.................................................................................................................. 121

7Contact Information........................................................................................................................ 121

Revision History...................................................................................................................................... 122

73S1209F Data Sheet DS_1209F_004

Figures

Figure 1: IC Functional Block Diagram ......................................................................................................... 7

Figure 2: Memory Map ................................................................................................................................ 15

Figure 3: Clock Generation and Control Circuits ........................................................................................ 24

Figure 4: Oscillator Circuit........................................................................................................................... 26

Figure 5: Power-Down Control.................................................................................................................... 27

Figure 6: Detail of Power-Down Interrupt Logic.......................................................................................... 28

Figure 7: Power-Down Sequencing ............................................................................................................ 28

Figure 8: External Interrupt Configuration................................................................................................... 32

Figure 9: I2C Write Mode Operation........................................................................................................... 55

Figure 10: I2C Read Operation.................................................................................................................... 56

Figure 11: Simplified Keypad Block Diagram.............................................................................................. 61

Figure 12: Keypad Interface Flow Chart ..................................................................................................... 63

Figure 13: Smart Card Interface Block Diagram......................................................................................... 68

Figure 14: External Smart Card Interface Block Diagram........................................................................... 69

Figure 15: Asynchronous Activation Sequence Timing .............................................................................. 72

Figure 16: Deactivation Sequence.............................................................................................................. 72

Figure 17: Smart Card CLK and ETU Generation ...................................................................................... 73

Figure 18: Guard, Block, Wait and ATR Time Definitions........................................................................... 74

Figure 19: Synchronous Activation ............................................................................................................. 76

Figure 20: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 76

Figure 21: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 77

Figure 22: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 77

Figure 23: Operation of 9-bit Mode in Sync Mode ...................................................................................... 78

Figure 24: 73S1209F Typical PINpad, Smart Card Reader Application Schematic................................. 103

Figure 25: 73S1209F Typical SIM / Smart Card Reader Application Schematic ..................................... 104

Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 110

Figure 27: Digital I/O Circuit ...................................................................................................................... 110

Figure 28: Digital Output Circuit ................................................................................................................ 111

Figure 29: Digital I/O with Pull Up Circuit.................................................................................................. 111

Figure 30: Digital I/O with Pull Down Circuit ............................................................................................. 112

Figure 31: Digital Input Circuit................................................................................................................... 112

Figure 32: Keypad Row Circuit ................................................................................................................. 113

Figure 33: Keypad Column Circuit ............................................................................................................ 113

Figure 34: LED Circuit............................................................................................................................... 114

Figure 35: Test and Security Pin Circuit ................................................................................................... 114

Figure 36: Analog Input Circuit.................................................................................................................. 115

Figure 37: Smart Card Output Circuit ....................................................................................................... 115

Figure 38: Smart Card I/O Circuit.............................................................................................................. 116

Figure 39: PRES Input Circuit ................................................................................................................... 116

Figure 40: PRES Input Circuit ................................................................................................................... 116

Figure 41: 73S1209F Pinout ..................................................................................................................... 117

Figure 42: 73S1209F Pinout ..................................................................................................................... 118

Figure 43: 73S1209F 68 QFN Pinout ....................................................................................................... 119

Figure 44: 73S1209F 44 QFN Pinout ....................................................................................................... 120

4 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 5

Tables

Table 1: 73S1209F Pinout Description ......................................................................................................... 8

Table 2: MPU Data Memory Map................................................................................................................ 11

Table 3: Flash Special Function Registers ................................................................................................. 13

Table 4: Internal Data Memory Map ........................................................................................................... 14

Table 5: Security Control Registers ............................................................................................................ 17

Table 6: IRAM Special Function Registers Locations................................................................................. 18

Table 7: IRAM Special Function Registers Reset Values........................................................................... 19

Table 8: XRAM Special Function Registers Reset Values ......................................................................... 21

Table 9: PSW Register Flags...................................................................................................................... 22

Table 10: Port Registers ............................................................................................................................. 23

Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25

Table 12: The MCLKCtl Register ................................................................................................................ 25

Table 13: The MPUCKCtl Register ............................................................................................................. 26

Table 14: The INT5Ctl Register .................................................................................................................. 29

Table 15: The MISCtl0 Register.................................................................................................................. 29

Table 16: The MISCtl1 Register.................................................................................................................. 30

Table 17: The MCLKCtl Register ................................................................................................................ 30

Table 18: The PCON Register .................................................................................................................... 31

Table 19: The IEN0 Register....................................................................................................................... 33

Table 20: The IEN1 Register....................................................................................................................... 34

Table 21: The IEN2 Register....................................................................................................................... 34

Table 22: The TCON Register .................................................................................................................... 35

Table 23: The T2CON Register .................................................................................................................. 35

Table 24: The IRCON Register................................................................................................................... 36

Table 25: External MPU Interrupts.............................................................................................................. 36

Table 26: Control Bits for External Interrupts.............................................................................................. 37

Table 27: Priority Level Groups................................................................................................................... 37

Table 28: The IP0 Register ......................................................................................................................... 37

Table 29: The IP1 Register ......................................................................................................................... 38

Table 30: Priority Levels.............................................................................................................................. 38

Table 31: Interrupt Polling Sequence.......................................................................................................... 38

Table 32: Interrupt Vectors.......................................................................................................................... 38

Table 33: UART Modes............................................................................................................................... 39

Table 34: Baud Rate Generation ................................................................................................................ 39

Table 35: The PCON Register .................................................................................................................... 40

Table 36: The BRCON Register ................................................................................................................. 40

Table 37: The MISCtl0 Register.................................................................................................................. 41

Table 38: The S0CON Register .................................................................................................................. 42

Table 39: The S1CON Register .................................................................................................................. 43

Table 40: The TMOD Register .................................................................................................................... 44

Table 41: TMOD Register Bit Description................................................................................................... 44

Table 42: Timers/Counters Mode Description ............................................................................................ 45

Table 43: The TCON Register .................................................................................................................... 46

Table 44: The IEN0 Register....................................................................................................................... 47

Table 45: The IEN1 Register....................................................................................................................... 47

Table 46: The IP0 Register ......................................................................................................................... 48

Table 47: The WDTREL Register ............................................................................................................... 48

Table 48: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49

Table 49: UDIR Control Bit.......................................................................................................................... 49

Table 50: Selectable Controls Using the UxIS Bits..................................................................................... 49

Table 51: The USRIntCtl1 Register ............................................................................................................ 50

Table 52: The USRIntCtl2 Register ............................................................................................................ 50

Table 53: The USRIntCtl3 Register ............................................................................................................ 50

Table 54: The USRIntCtl4 Register ............................................................................................................ 50

Table 55: The ACOMP Register ................................................................................................................. 51

Table 56: The INT6Ctl Register .................................................................................................................. 52

73S1209F Data Sheet DS_1209F_004

Table 57: The LEDCtl Register ................................................................................................................... 53

Table 58: The DAR Register ....................................................................................................................... 57

Table 59: The WDR Register...................................................................................................................... 57

Table 60: The SWDR Register.................................................................................................................... 58

Table 61: The RDR Register....................................................................................................................... 58

Table 62: The SRDR Register .................................................................................................................... 59

Table 63: The CSR Register ....................................................................................................................... 59

Table 64: The INT6Ctl Register .................................................................................................................. 60

Table 65: The KCOL Register..................................................................................................................... 64

Table 66: The KROW Register ................................................................................................................... 64

Table 67: The KSCAN Register .................................................................................................................. 65

Table 68: The KSTAT Register ................................................................................................................... 65

Table 69: The KSIZE Register .................................................................................................................... 66

Table 70: The KORDERL Register ............................................................................................................. 66

Table 71: The KORDERH Register ............................................................................................................ 67

Table 72: The INT5Ctl Register .................................................................................................................. 67

Table 73: The SCSel Register .................................................................................................................... 79

Table 74: The SCInt Register...................................................................................................................... 80

Table 75: The SCIE Register ...................................................................................................................... 81

Table 76: The VccCtl Register .................................................................................................................... 82

Table 77: The VccTmr Register .................................................................................................................. 83

Table 78: The CRDCtl Register .................................................................................................................. 84

Table 79: The STXCtl Register ................................................................................................................... 85

Table 80: The STXData Register................................................................................................................ 86

Table 81: The SRXCtl Register................................................................................................................... 86

Table 82: The SRXData Register ............................................................................................................... 87

Table 83: The SCCtl Register ..................................................................................................................... 88

Table 84: The SCECtl Register................................................................................................................... 89

Table 85: The SCDIR Register ................................................................................................................... 90

Table 86: The SPrtcol Register ................................................................................................................... 91

Table 87: The SCCLK Register................................................................................................................... 92

Table 88: The SCECLK Register ................................................................................................................ 92

Table 89: The SParCtl Register .................................................................................................................. 93

Table 90: The SByteCtl Register................................................................................................................. 94

Table 91: The FDReg Register ................................................................................................................... 95

Table 92: Divider Ratios Provided by the ETU Counter ............................................................................. 95

Table 93: Divider Values for the ETU Clock ............................................................................................... 96

Table 94: The CRCMsB Register ............................................................................................................... 97

Table 95: The CRCLsB Register ................................................................................................................ 97

Table 96: The BGT Register ....................................................................................................................... 98

Table 97: The EGT Register ....................................................................................................................... 98

Table 98: The BWTB0 Register .................................................................................................................. 99

Table 99: The BWTB1 Register .................................................................................................................. 99

Table 100: The BWTB2 Register ................................................................................................................ 99

Table 101: The BWTB3 Register ................................................................................................................ 99

Table 102: The CWTB0 Register................................................................................................................ 99

Table 103: The CWTB1 Register................................................................................................................ 99

Table 104: The ATRLsB Register ............................................................................................................. 100

Table 105: The ATRMsB Register ............................................................................................................ 100

Table 106: The STSTO Register............................................................................................................... 100

Table 107: The RLength Register............................................................................................................. 100

Table 108: Smart Card SFR Table ........................................................................................................... 101

Table 109: The VDDFCtl Register ............................................................................................................ 102

Table 110: Order Numbers and Packaging Marks ................................................................................... 121

6 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 7

SMART

CARD

ISO

INTERFACE

SCLK

SIO

EXTERNAL

SMART

CARD

INTERFACE

VCC

CONTROL

LOGIC

LED

DRIVERS

GND

TBUS1

TBUS2

TBUS3

TBUS0

RXTX

ERST

ISBR

TCLK

TXD

RXD

LED1

LED0

ICE INTERFACE

SEC

SMART CARD LOGIC

ISO UART and CLOCK GENERATOR

FLASH/ROM

PROGRAM

MEMORY

32KB

DATA

XRAM

2KB

CORE

SERIAL

VDD

INT2

INT3

GND

PERIPHERAL

INTERFACE

and SFR LOGIC

FLASH

INTERFACE

TEST

OCDSI

ISR

WATCH-

DOG

TIMER

PMU

PORTS

TIMER_0_

MEMORY_

CONTROL

UNIT

RAM_

SFR_

CONTROL

ALU

RESET

VOLTAGE REFERENCE

AND FUSE TRIM

CIRCUITRY

VPD REGULATOR

ANA_IN

PLL

and

TIMEBASES

VDD

SCRATCH

IRAM

256B

12MHz

OSCILLATOR

X12OUT

X12IN

COL4

COL3

COL2

COL1

COL0

ROW5

ROW4

ROW3

ROW2

ROW1

ROW0

KEYPAD

INTERFACE

I2C

MASTER

INT.

SDA

SCL

USR(8:0)

DRIVERS

USR7

USR6

USR5

USR4

USR3

USR1

USR2

USR0

USR8

VCC

RST

CLK

I/O

AUX2

AUX1

PRES

PRESB

VPC

Pins avaiable on both 68 and 44 pin packages.

Pins only avaiable on 68 pin package.

GND

VDD

Figure 1: IC Functional Block Diagram

73S1209F Data Sheet DS_1209F_004

1 Hardware Description

1.1 Pin Description

Table 1: 73S1209F Pinout Description

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

X12IN 10 8 I

Figure 26 MPU clock crystal oscillator input pin. A 1MΩresistor is

required between pins X12IN and X12OUT.

X12OUT 11 9 O Figure 26 MPU clock crystal oscillator output pin.

ROW (5:0)

Figure 32 Keypad row input sense.

COL(4:0)

O Figure 33 Keypad column output scan pins.

USR(8:0)

IO Figure 29 General-purpose user pins, individually configurable as

inputs or outputs or as external input interrupt ports.

SCL 5 5 O Figure 28 I2C (master mode) compatible Clock signal. Note: the

pin is configured as an open drain output. When the

I2C interface is being used, an external pull up resistor

is required. A value of 3K is recommended.

SDA 6 6 IO Figure 27 I2C (master mode) compatible data I/O. Note: this pin is

bi-directional. When the pin is configured as output, it is

an open drain output. When the I2C interface is being

used, an external pull up resistor is required. A value of

3K is recommended.

LED(1:0)

Figure 34 Special output drivers, programmable pull-down current

to drive LEDs. May also be used as inputs.

RXD 17 11 I Figure 31 Serial UART Receive data pin.

TXD 18 12 O Figure 28 Serial UART Transmit data pin.

INT3 51 I Figure 31 General purpose interrupt input.

8 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 9

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

INT2 52 32 I Figure 31 General purpose interrupt input.

SIO 50 31 IO Figure 27 IO data signal for use with external Smart Card interface

circuit such as 73S8010.

SCLK 48 30 O Figure 28 Clock signal for use with external Smart Card interface

circuit.

PRES 64 43 I Figure 39 Smart Card presence. Active high. Note: the pin has a

very weak pull down resistor. In noisy environments, an

external pull down may be desired to insure against a

false card event.

PRESB 56 35 I Figure 40 Smart Card presence. Active low. Note: the pin has a

very weak pull up resistor. In noisy environments, an

external pull up may be desired to insure against a false

card event.

CLK 57 36 O Figure 37 Smart card clock signal.

RST 59 38 O Figure 37 Smart card Reset signal.

IO 63 42 IO Figure 38 Smart card Data IO signal.

AUX1 62 41 IO Figure 38 Auxiliary Smart Card IO signal (C4).

AUX2 61 40 IO Figure 38 Auxiliary Smart Card IO signal (C8).

VCC 60 39 PSO Smart Card VCC supply voltage output. A 0.47μF

capacitor is required and should be located at the smart

card connector. The capacitor should be a ceramic type

with low ESR.

GND 58 37 GND Smart Card Ground.

VPC 55 34 PSI Smart Card LDO regulator power supply source. A

10μF and a 0.1μF capacitor are required at the VPC

input. The 10μF capacitor should be a ceramic type

with low ESR.

TBUS(3:0)

Trace bus signals for ICE.

RXTX 45 28 IO ICE control.

ERST 40 25 IO ICE control.

ISBR 68 IO ICE control.

TCLK 41 26 I ICE control.

ANA_IN 15 10 AI

Figure 36 Analog input pin. This signal goes to a programmable

comparator and is used to sense the value of an

external voltage.

SEC 67 2 I Figure 35 Input pin for use in programming security fuse. It should

be connected to ground when not in use.

TEST 54 33 DI Figure 35 Test pin, should be connected to ground.

73S1209F Data Sheet DS_1209F_004

Pin Name

Pin (68 QFN)

Pin (44 QFN)

Type

Equivalent

Circuit*

Description

VDD 28

I General positive power supply pins. All digital IO is

referred to this supply voltage. There is an on-chip

regulator that uses VDD to provide power for internal

circuits (VPD). A 0.1μF capacitor is recommended at

each VDD pin.

N/C 2

No connect.

GND 9

GND

General ground supply pins for all IO and logic circuits.

RESET 66 1 I Figure 31 Reset input, positive assertion. Resets logic and

registers to default condition.

* See the figures in the Equivalent Circuits section.

10 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 11

1.2 Hardware Overview

The 73S1209F single smart card controller integrates all primary functional blocks required to implement

a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up

to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card interface,

expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, 2 LED drivers,

RAM, FLASH memory, and a variety of I/O pins. A functional block diagram of the 73S1209F is shown in

Figure 1.

1.3 80515 MPU Core

1.3.1 80515 Overview

The 73S1209F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one

clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution

of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most

of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)

improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application

(cryptographic calculations, key management, memory management, and I/O management) using the

XRAM special function register MPUCKCtl.

Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of

Teridian’s standard library. A standard ANSI “C” 80515-application programming interface library is

available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.

1.3.2 Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.

Memory organization in the 80515 is similar to that of the industry standard 8051. There are three

memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory

(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2

Table 2: MPU Data Memory Map

Address

(hex)

Memory

Technology Memory Type Typical Usage Memory Size

(bytes)

0000-7FFF Flash Memory Non-volatile Program and non-volatile data 32KB

0000-07FF Static RAM Volatile MPU data XRAM 2KB

FC00-FFFF External SFR Volatile Peripheral control 1KB

Note: The IRAM is part of the core and is addressed differently.

Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to

0x7FFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.

After reset, the MPU starts program execution from location 0x0000. The lower part of the program

memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting

from 0x0003. Reset is located at 0x0000.

Flash Memory: The program memory consists of flash memory. The flash memory is intended to

primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to

specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent

inadvertent erasure of the flash memory.

73S1209F Data Sheet DS_1209F_004

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit in the FLSHCTL register (SFR address 0xB2[1]).

2. Write pattern 0xAA to ERASE (SFR address 0x94).

Note: The mass erase cycle can only be initiated when the ICE port is enabled.

The page erase sequence is:

1. Write the page address to PGADDR (SFR address 0xB7[7:1])

2. Write pattern 0x55 to ERASE (SFR address 0x94)

The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and

there are 128 pages within the flash memory. The PGADDR denotes the upper seven bits of the flash

memory address such that bit 7:1 of the PGADDR corresponds to bit 15:9 of the flash memory address.

Bit 0 of the PGADDR is not used and is ignored. The MPU may write to the flash memory. This is one of

the non-volatile storage options available to the user. The FLSHCTL SFR bit FLSH_PWE (flash program

write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM

writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows

the location and description of the 73S1209F flash-specific SFRs.

Any flash modifications must set the CPUCLK to operate at 3.6923 MHz (MPUCLKCtl = 0x0C)

before any flash memory operations are executed to insure the proper timing when modifying the

flash memory.

12 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 13

Table 3: Flash Special Function Registers

Address

R/W Description

ERASE 0x94 W This register is used to initiate either the Flash Mass Erase cycle or the

Flash Page Erase cycle. Specific patterns are expected for ERASE in

order to initiate the appropriate Erase cycle (default = 0x00).

0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to

PGADDR @ SFR 0xB7.

0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled.

Any other pattern written to ERASE will have no effect.

PGADDR 0xB7 R/W Flash Page Erase Address register containing the flash memory page

address (page 0 through 127) that will be erased during the Page Erase

cycle (default = 0x00). Note: the page address is shifted left by one bit

(see detailed description above).

Must be re-written for each new Page Erase cycle.

FLSHCTL 0xB2 R/W

Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to flash. Writes to

this bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash

memory and CE program RAM. This bit is reset on chip reset and may

only be set. Attempts to write zero are ignored.

73S1209F Data Sheet DS_1209F_004

Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory.

The internal data memory address is always one byte wide and can be accessed by either direct or

indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is

available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal

RAM.

The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form

four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which

bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 0x00-

0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4

shows the internal data memory map.

Table 4: Internal Data Memory Map

Address Direct Addressing Indirect Addressing

0xFF Special Function

Registers (SFRs) RAM

0x80

0x7F

Byte-addressable area

0x30

0x2F

Byte or bit-addressable area

0x20

0x1F Register banks R0…R7 (x4)

0x00

External Data Memory: While the 80515 can address up to 64KB of external data memory in the space

from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 2 contain physical memory. The

80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A

instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR

instruction.

There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect

address to the external data RAM.

In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight

lower-ordered bits of address. This method allows the user access to the first 256 bytes of the 2KB of

external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer

generates a sixteen-bit address.

14 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 15

Address Use

0xFFFF Peripheral Control

Registers (128b)

0XFF80

0xFF7F Smart Card Control

(384b)

0XFE00

Address Use 0xFBFF

---

0x7FFF

Flash

Program

memory

32K

Bytes

0x0800

Address

Use

0x07FF

XRAM

Indirect

Access

Direct

Access

0xFF Byte RAM SFRs

0x80

0x7F Byte RAM

0x48

0x47 Bit/Byte RAM

0x20

0x1F Register bank 3

0x18

0x17 Register bank 2

0x10

0x0F Register bank 1

0x08

0x07 Register bank 0

0x0000 0x0000 0x00

Program Memory External Data Memory Internal Data Memory

Figure 2: Memory Map

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a

16-bit register that is used to address external memory. In the 80515 core, the standard data pointer is

called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active

pointer. The data pointer select bit is located at the LSB of the DPS IRAM special function register

(DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.

The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related

instructions use the currently selected DPTR for any activity.

Note: The second data pointer may not be supported by certain compilers.

73S1209F Data Sheet DS_1209F_004

1.4 Program Security

Two levels of program and data security are available. Each level requires a specific fuse to be blown in

order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE bit

(bit 6 of SFR register FLSHCTL 0xB2) Mode 0 limits the ICE interface to only allow bulk erase of the

flash program memory. All other ICE operations are blocked. This guarantees the security of the user’s

MPU program code. Security (Mode 0) is enabled by MPU code that sets the SECURE bit. The MPU

code must execute the setting of the SECURE bit immediately after a reset to properly enable Mode 0.

This should be the first instruction after the reset vector jump has been executed. If the “startup.a51”

assembly file is used in an application, then it must be modified to set the SECURE bit after the reset

vector jump. If not using “startup.a51”, then this should be the first instruction in main(). Once security

Mode 0 is enabled, the only way to disable it is to perform a global erase of the flash followed by a full

circuit reset. Once the flash has been erased and the reset has been executed, security Mode 0 is

disabled and the ICE has full control of the core. The flash can be reprogrammed after the bulk erase

operation is completed. Global erase of the flash will also clear the data XRAM memory. The security

enable bit (SECURE) is reset whenever the MPU is reset. Hardware associated with the bit only allows it

to be set. As a result, the code may set the SECURE bit to enable the security Mode 0 feature but may

not reset it. Once the SECURE bit is set, the code is protected and no external read of program code in

flash or data (in XRAM) is possible. In order to invoke the security Mode 0, the SECSET0 (bit 1 of XRAM

SFR register SECReg 0xFFD7) fuse must be blown beforehand or the security mode 0 will not be

enabled. The SECSET0 and SECSET1 fuses once blown, cannot be overridden.

Specifically, when SECURE is set:

•The ICE is limited to bulk flash erase only.

•Page zero of flash memory may not be page-erased by either MPU or ICE. Page zero may only be

erased with global flash erase. Note that global flash erase erases XRAM whether the SECURE bit is

set or not.

•Writes to page zero, whether by MPU or ICE, are inhibited.

Security mode 1 is in effect when the SECSET1 fuse has been programmed (blown open). In security

mode 1, the ICE is completely and permanently disabled. The Flash program memory and the MPU are

not available for alteration, observation, or control. As soon as the fuse has been blown, the ICE is

disabled. The testing of the SECSET1 fuse will occur during the reset and before the start of pre-boot

and boot cycles. This mode is not reversible, nor recoverable. In order to blow the SECSET1 fuse, the

SEC pin must be held high for the fuse burning sequence to be executed properly. The firmware can

check to see if this pin is held high by reading the SECPIN bit (bit 5 of XRAM SFR register SECReg

0xFFD7). If this bit is set and the firmware desires, it can blow the SECSET1 fuse. The burning of the

SECSET0 does not require the SEC pin to be held high.

In order to blow the fuse for SECSET1 and SECSET0, a particular set of register writes in a specific order

need to be followed. There are two additional registers that need to have a specific value written to them

in order for the desired fuse to be blown. These registers are FUSECtl (0xFFD2) and TRIMPCtl

(0xFFD1). The sequence for blowing the fuse is as follows:

1. Write 0x54H to FUSECtl.

2. Write 0x81H for security mode 0 Note: only program one security mode at a time.

Write 0x82H for security mode 1 Note: SEC pin must be high for security mode 1.

3. Write 0xA6 to TRIMPCtl.

4. Delay about 500 us

5. Write 0x00 to TRIMPCtl.

16 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 17

Table 5: Security Control Registers

Address

R/W Description

FLSHCTL 0xB2 R/W Bit 0 (FLSH_PWE): Program Write Enable:

0 – MOVX commands refer to XRAM Space, normal operation (default).

1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

This bit is automatically reset after each byte written to flash. Writes to this

bit are inhibited when interrupts are enabled.

W Bit 1 (FLSH_MEEN): Mass Erase Enable:

0 – Mass Erase disabled (default).

1 – Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

R/W Bit 6 (SECURE):

Enables security provisions that prevent external reading of flash memory

and CE program RAM. This bit is reset on chip reset and may only be set.

Attempts to write zero are ignored.

TRIMPCtl 0xFFD1 W 0xA6 value will cause the selected fuse to be blown. All other values will

stop the burning process.

FUSECtl 0xFFD2 W 0x54 value will set up for security fuse control. All other values are

reserved and should not be used.

SECReg 0xFFD7 W Bit 7 (PARAMSEC):

0 – Normal operation

1 – Enable permanent programming of the security fuses.

R Bit 5 (SECPIN):

Indicates the state of the SEC pin. The SEC pin is held low by a pull-down

resistor. The user can force this pin high during boot sequence time to

indicate to the firmware that sec mode 1 is desired.

R/W Bit 1 (SECSET1):

See Program Security section.

R/W Bit 0 (SECSET0):

See Program Security section.

73S1209F Data Sheet DS_1209F_004

1.5 Special Function Registers (SFRs)

The 73S1209F utilizes numerous SFRs to communicate with the 73S1209F s many peripherals. This

results in the need for more SFR locations outside the direct address IRAM space (0x80 to 0xFF). While

some peripherals are mapped to unused IRAM SFR locations, additional SFRs for the smart card and

other peripheral functions are mapped to the top of the XRAM data space (0xFC00 to 0xFFFF).

1.5.1 Internal Data Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 6.

Table 6: IRAM Special Function Registers Locations

Hex\

Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/

Hex

F8 FF

F0 BF7

E8 EF

E0 AE7

D8 BRCON DF

D0 PSW KCOL KROW KSCAN KSTAT KSIZE KORDERL KORDERH D7

C8 T2CON CF

C0 IRCON C7

B8 IEN1 IP1 S0RELH S1RELH BF

FLSHCTL

PGADDR B7

A8 IEN0 IP0 S0RELL AF

A0 USR8 UDIR8 A7

98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL 9F

90 USR70 UDIR70 DPS

ERASE 97

88 TCON TMOD TL0 TL1 TH0 TH1

MCLKCtl 8F

80 SP DPL DPH DPL1 DPH1 WDTREL PCON 87

Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1209F are

shown in bold print (gray background). Any read access to unimplemented addresses will return

undefined data, while most write access will have no effect. However, a few locations are reserved and

not user configurable in the 73S1209F. Writes to the unused SFR locations can affect the operation

of the core and therefore must not be written to. This applies to all the SFR areas in both the

IRAM and XRAM spaces. In addition, all unused bit locations within valid SFR registers must be

left in their default (power on default) states.

18 Rev. 1.2

DS_1209F_004 73S1209F Data Sheet

Rev. 1.2 19

1.5.2 IRAM Special Function Registers (Generic 80515 SFRs)

Table 7 shows the location of the SFRs and the value they assume at reset or power-up.

Table 7: IRAM Special Function Registers Reset Values

Name Location Reset Value Description

SP 0x81 0x07 Stack Pointer

DPL 0x82 0x00 Data Pointer Low 0

DPH 0x83 0x00 Data Pointer High 0

DPL1 0x84 0x00 Data Pointer Low 1

DPH1 0x85 0x00 Data Pointer High 1

WDTREL 0x86 0x00 Watchdog Timer Reload register

PCON 0x87 0x00 Power Control

TCON 0x88 0x00 Timer/Counter Control

TMOD 0x89 0x00 Timer Mode Control

TL0 0x8A 0x00 Timer 0, low byte

TL1 0x8B 0x00 Timer 1, high byte

TH0 0x8C 0x00 Timer 0, low byte

TH1 0x8D 0x00 Timer 1, high byte

MCLKCtl 0x8F 0x0A Master Clock Control

USR70 0x90 0xFF User Port Data (7:0)

UDIR70 0x91 0xFF User Port Direction (7:0)

DPS 0x92 0x00 Data Pointer select Register

ERASE 0x94 0x00 Flash Erase

S0CON 0x98 0x00 Serial Port 0, Control Register

S0BUF 0x99 0x00 Serial Port 0, Data Buffer

IEN2 0x9A 0x00 Interrupt Enable Register 2

S1CON 0x9B 0x00 Serial Port 1, Control Register

S1BUF 0x9C 0x00 Serial Port 1, Data Buffer

S1RELL 0x9D 0x00 Serial Port 1, Reload Register, low byte

USR8 0xA0 0x00 User Port Data (8)

UDIR8 0xA1 0x01 User Port Direction (8)

IEN0 0xA8 0x00 Interrupt Enable Register 0

IP0 0xA9 0x00 Interrupt Priority Register 0

S0RELL 0xAA 0xD9 Serial Port 0, Reload Register, low byte

FLSHCTL 0xB2 0x00 Flash Control

PGADDR 0xB7 0x00 Flash Page Address

IEN1 0xB8 0x00 Interrupt Enable Register 1

IP1 0xB9 0x00 Interrupt Priority Register 1

S0RELH 0xBA 0x03 Serial Port 0, Reload Register, high byte

S1RELH 0xBB 0x03 Serial Port 1, Reload Register, high byte

IRCON 0xC0 0x00 Interrupt Request Control Register

T2CON 0xC8 0x00 Timer 2 Control

73S1209F Data Sheet DS_1209F_004

Name Location Reset Value Description

PSW 0xD0 0x00 Program Status Word

KCOL 0XD1 0x1F Keypad Column

KROW 0XD2 0x3F Keypad Row

KSCAN 0XD3 0x00 Keypad Scan Time

KSTAT 0XD4 0x00 Keypad Control/Status

KSIZE 0XD5 0x00 Keypad Size

KORDERL 0XD6 0x00 Keypad Column LS Scan Order

KORDERH 0XD7 0x00 Keypad Column MS Scan Order

BRCON 0xD8 0x00 Baud Rate Control Register (only BRCON.7 bit used)

A0xE0 0x00 Accumulator

B0xF0 0x00 B Register

20 Rev. 1.2

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