Tern P52 User manual

P52™
I/O expansion card with ADC, DAC, 24 PPI I/Os, 100M BaseT Ethernet,
Quadrature Decoders, RS232/485
Technical Manual
1724 Picasso Avenue, Davis, CA 95616, USA
Tel: [phone] Fax: [phone]
Internet Email: [email protected] http://www.tern.com

COPYRIGHT
P50, 586-Engine, i386-Engine, A-Engine86, NT-Kit, MemCard, and ACTF are
trademarks of TERN, Inc.
SC520, Am188ES and Am186ES are trademarks of Advanced Micro Devices, Inc.
Microsoft, MS-DOS, Windows, Windows95/98/2000 are trademarks of Microsoft
Corporation.
IBM is a trademark of International Business Machines Corporation.
Version 1.00
February 27, 2007
No part of this document may be copied or reproduced in any form or by any means
without the prior written consent of TERN, Inc.
© 1994-2000
1724 Picasso Avenue, Davis, CA 95616, USA
Tel: [phone] Fax: [phone]
Email: [email protected] http://www.tern.com
Important Notice
TERN is developing complex, high technology integration systems. These systems are
integrated with software and hardware that are not 100% defect free. TERN products are
not designed, intended, authorized, or warranted to be suitable for use in life-support
applications, devices, or systems, or in other critical applications. TERN and the Buyer
agree that TERN will not be liable for incidental or consequential damages arising from
the use of TERN products. It is the Buyer's responsibility to protect life and property
against incidental failure.
TERN reserves the right to make changes and improvements to its products
without providing notice.

P52 Chapter 1: Introduction
1-1
Chapter 1: Introduction
1.1 Functional Description
Measuring 4.4 x 3.1 inches, the P52 is an I/O expansion board designed for and driven by a Tern host
controller. A 16-bit external data bus is required to run the parallel ADC and DAC on the P52. Many
embedded applications demand high speed ADC and DAC with buffered operational amplifiers supporting
variable gains or offset for analog signals. The P52 supports four 16-bit, parallel DACs (DAC8544)
buffered by 4 ops with gain=2 (hardware adjustable), providing ±5V analog output by default. A resistor
pot is used to adjust the DAC analog output offset. It also supports eight 16-bit parallel ADC inputs
(AD7655).
The P52 can buffer PIOs with 16 sourcing drivers (UDN2982), or 14 sinking drivers (ULN2003). These
drivers can source or sink 350 mA at 50V per line to directly drive solenoids, relays, or lights. Eight high
isolation voltage photocouplers (PS2701, NEC) can be installed to provide optically isolators to PIOs. Two
quadrature decoders, (HCTL2020, Hewlett Packard) can be installed to interface incremental motion
encoders. In addition, 24 bi-directional TTL PPI I/Os (82C55) are software programmable and free to use.
100M BaseT
Ethernet
Serial Port 0
(Debug Port)
Serial Port 1
24 TTL I/O
’
s
2 Quadrature
Decoder inputs
+12V input
GND
8 16-bit ADC
inputs
4 16-bit DAC
ouputs
DAC offset-
adjusting POT
8 Opto-
coupler
inputs
14 High
Voltage
outputs

P52 Chapter 1: Introduction
1-2
A 100M BaseT Ethernet controller (Wiznet) can be installed to provide network connectivity. A software
stack library is available, supporting network protocols like ARP, DHCP, UDP, ICMP, and of course TCP
over the Ethernet network.
Two channels of RS-232 drivers and a 5V linear regulator are on-board. An optional RS232 or RS485
driver can be installed for the optional 3rd UART of the host controller. The P52 requires 8.5V to 12V DC
power supply with linear regulator, or up to 30V DC power input with an optional switching regulator
without generating excessive heat.
TERN host
controller
586-Engine
or A-Engine86,
i386-Engine
PAL
HP2020
Quad.
Decoders
P52 High speed
parallel
ADC
High speed
parallel
DAC
8 channels
opto-couplers
address,
data bus
CPU PIOs
address bus
sinking/sourcing
H.V. drivers
100M base-T
Ethernet
interface
data bus
Figure 1.1 Functional block diagram of the P52
1.2 Features
►4.4x3.1x0.5 inches.
►Driven by 586-Engine™ , i386-Engine™, A-Engine86™.
►Power consumption: < 200 mA @ 9V-12V
►2 channels RS-232 serial communication
►24 PPIs, 14 high voltage sourcing or sinking drivers
►Wiznet 100M Base-T Ethernet Controller
►8 ch. 16-bit ADC( AD7655) x 2
►4 ch. 16-bit DAC (DAC8544) with buffer ops*.
►8 opto-isolators and 2 quadrature decoders*
►5V switching regulator*
►RS-232/485 for optional 3rd UART on controlling ‘Engine’*
*optional

P52 Chapter 2: Installation
2-1
Chapter 2: Installation
2.1 Connecting the P52 and the host ‘Engine’ to the PC
Using P52 COM Ports:
The following diagram (Figure 2.1) illustrates the connection between the P52 and the PC via a serial
cable.
A host controller must be installed on the P52 via J1 and J2 headers before power on. The host
communicates through SER0 for debugging by default. Thus, the 5x2 IDC connector must be installed on
the SER0 of the P52 (header H2). IMPORTANT: Note that the red side of the cable must point to pin 1
of the H2 header. The DB9 connector should be connected to one of your PC's COM Ports (COM1 or
COM2).
Figure 2.1 P52 driven by host controller A-Engine-40
Serial Port 0
(Debug Port)
Red edge of
Debug Cable
12V Power
Plug (Center
Negative)

P52 Chapter 2: Installation
2-2
Using Host Controller COM ports:
In the case where the host controller already provides Serial Ports 0 and 1, such as the 5P shown below,
P52 header H2 (Ser 0) will be blocked off. To negotiate with this change, we can use the debug port (Ser
0) on the host controller and avoid Serial ports 0 and 1 on the P52, as shown below with the 5P as host.
Figure 2.2 P52 driven by host controller 586-Engine-P.
The P52 must be powered by an unregulated +12 Volts (or up to +30V with an optional switching
regulator). A 2x1 screw terminal is installed to accept this +12V input. See schematic for orientation of
screw terminal. Using the power jack adapter provided with a TERN EV-P or DV-P Kit, connect the
output of the wall transformer to your P52 (as seen in above diagram).
Serial Port 0
on 5P
12V Power Jack
Adapter (Center
Negative)
Red edge of
Debug Cable

P52 Hardware
3-1
Chapter 3: Hardware
3.1 Engine controllers
The P52 was designed to be driven by a Tern host controller, using the 16-bit external data/address bus to
drive the parallel ADC and DAC, as well as other components. Any ‘Engine’ used will be installed on top
of the P52 via 20x2 pin headers J1 and J2, and can be secured by two #4-40 mounting screws.
3.2 Serial Ports Drivers
The P52 can provide up to 3 channels RS-232/485 drivers. By default, two RS-232 drivers are ready for
the two asynchronous serial UARTs from the installed Engine controller via 20x2 pin header J1 and J2.
One optional 3rd RS232 or RS485 driver can be installed to support the optional UART SCC2691 on the
Engine controller.
The default debug serial port SER0 is routed at H2, SER1 at H3, and SCC port at H4.
Note: H4 is hidden beneath the Wiznet Ethernet Module. If the Ethernet is installed while H4 is needed,
an angled header should be considered.
H2 Serial Port 0
(Debug Port)
H3
Serial Port 1
H4
3
r
d
UART Port
H4 hidden
under ethernet
module.

Chapter 3: Hardware P52
3-2
3.3 I/O Mapped Devices
3.3.1 I/O Space
External I/O devices can use I/O mapping for access. You can access such I/O devices with inportb(port)
or outportb(port,dat). These functions will transfer one byte of data to the specified I/O address. Refer to
the software chapter of the controlling Engine’s technical manual for additional information on I/O space
and access.
The tables below shows more information about I/O mapping,
I/O space Select Signal Location Usage
0x00,02,04,06 /PP1 U1 pin 7 /PPI for PPI
0x10 /RD /AD U15 pin 31 /AD for AD7655
0x20 /RD /AD1 U22 pin 31 /AD1 for AD7655
0x10 /WR LD U3 pin 27 LD for DA8544
0x20 /WR /DA U3 /DA for DA8544
0x30 /WR /ADR U2 pin 11 /ADR for ethernet
0x40 /RD /RDT U16 pin 1 /RDT read optos
0x48 /RD
0x50
/HP1
/HP2
U6 pin 4
U8 pin 4
read HP2020 (U6)
read HP2020(U8)
0x60 /WR
0x68
/HV1
/HV2
U23 pin 4
U24 pin 4
write HC259 (U23)
write HC259 (U24)
0x70
0x78
/CV
/CV1
U15 pin 35
U22 pin 35
/CV for AD7655 (U15)
/CV1 for AD7655 (U22)
Table 3.1 186-Engine Mapping
I/O space Select Signal Location Usage
0x1080,82,84,86 /PP1 U1 pin 7 /PPI for PPI
0x1090 /RD /AD U15 pin 31 /AD for AD7655
0x10A0 /RD /AD1 U22 pin 31 /AD1 for AD7655
0x1090 /WR LD U3 pin 27 LD for DA8544
0x10A0 /WR /DA U3 /DA for DA8544
0x10B0 /WR /ADR U2 pin 11 /ADR for ethernet
0x10C0 /RD /RDT U16 pin 1 /RDT read optos
0x10C8 /RD
0x10D0
/HP1
/HP2
U6 pin 4
U8 pin 4
read HP2020 (U6)
read HP2020(U8)
0x10E0 /WR
0x10E8
/HV1
/HV2
U23 pin 4
U24 pin 4
write HC259 (U23)
write HC259 (U24)
0x10F0
0x10F8
/CV
/CV1
U15 pin 35
U22 pin 35
/CV for AD7655 (U15)
/CV1 for AD7655 (U22)
Table 3.2 586-Engine Mapping

P52 Hardware
3-3
3.3.2 Programmable Peripheral Interface (82C55A)
The U1 PPI (8255) is a low-power CMOS programmable parallel interface unit for use in microcomputer
systems. It provides 24 I/O pins that may be individually programmed in two groups of 12 and used in
three major modes of operation.
In MODE 0, the two groups of 12 pins can be programmed in sets of 4 and 8 pins to be inputs or outputs.
In MODE 1, each of the two groups of 12 pins can be programmed to have 8 lines of input or output. Of
the 4 remaining pins, 3 are used for handshaking and interrupt control signals. Finally, MODE 2 is a
strobed bi-directional bus configuration.
76 012345
GROUP 1
Port 2
(L ow er)
Port 1
Mode
0
1
0
1
0
1
Output
Input
Output
Input
Mode 0
Mode 1
GROUP 2
Port 2
(U pper)
Port 0
M ode
0
1
0
1
00
01
Output
Input
Output
Input
M ode 0
M ode 1
M ode 2
1X
Command
Select
0
1
Bit
mani
p
ulation
M ode
Select
Figure 3.1 Mode Select Command Word
P52 maps U1, the PPI 8255, at base I/O address PPI = 0x1080 (586-Engine) and 0x00 (186-Engine).
All ports/registers are offsets of this I/O base address.
The Command Register address = PPI+6; Port 0 address = PPI+0; Port 1 address = PPI+2;
and Port 2 address = PPI+4.
The following code example will set all ports to output mode:
outportb(PPI+6,0x80); /* Mode 0 all output selection. */
And then write to specific pins after setup:
outportb(PPI+0,0x55); /* Sets port 0 to alternating high/low I/O pins. */
outportb(PPI+2,0x55); /* Sets port 1 to alternating high/low I/O pins. */
outportb(PPI+4,0x55); /* Sets port 2 to alternating high/low I/O pins. */
To set all ports to input mode:
outportb(PPI1+6,0x9f); /* Mode 0 all input selection. */

Chapter 3: Hardware P52
3-4
You can read the ports with:
inportb(PPI+0); /* Port 0 */
inportb(PPI+2); /* Port 1 */
inportb(PPI+4); /* Port 2 */
These inport(PPI+i); statements return an 8-bit value for each port, with each bit corresponding to the
appropriate line on the port.
There are 24 TTL level I/O pins free to use for your application. These I/O lines are specified as 4 mA
driving current capability. PPI outputs are routed to J3.1-24. See schematics for PPI connection header J3
.
3.3.3 HCTL2020
Two quadrature decoder/counter interface chips, (HCTL2020, Hewlett Packard, U6 and U8) can be
installed on the P52. The quadrature decoder is used to interface incremental motion encoders with the
microprocessor system or to improve system performance for digital closed-loop motion control systems.
The HCTL2020 includes a quadrature decoder, a 16-bit counter, and an 8-bit bus interface. It features full
4x decoding, up to 14 MHz clock operation, high noise immunity due to Schmitt-trigger inputs and digital
noise filters, quadrature decoder output signals, up/down signal, count signals, and cascade output signal.
Many types of optical incremental encoder modules, such as the HEDS-9000, HEDS-9100, and HEDS-
9200 from HP, can be directly interfaced to the HCTL2020.
Channel A and B signals buffered with Schmitt trigger inputs (U7, 74HC14, CHA1/2, CHB1/2) are routed
at pins 31, 32, 35, and 36 on header J3. The HCTL2020 has built-in filters, which allow reliable operation
in noisy environments.
3.3.4 Four channel, 16-bit ADC (AD7655)
Two AD7655 ADC’s may be installed on the P52. The unique 16-bit parallel ADC (AD7655, 0-5V)
supports ultra high-speed (1 MHz conversion rate) analog signal acquisition. The AD7655 contains two
low noise, high bandwidth track-and-hold amplifiers that allow simultaneous sampling on two channels.
Each track-and hold amplifier has a multiplexer in front to provide a total of 4 channels analog inputs. The
parallel ADC achieves very high throughput by requiring only two CPU I/O operations (one start, one
read) to complete a 16-bit ADC reading. With a precision external 2.5V reference, the ADC accepts 0-5V
analog inputs at 16-bit resolution of 0-65,535. U22 inputs are found on J5.7-10, while U15 inputs are on
J5.11-14.
See sample program “p52_ad.c” in \tern\186\samples\p52 or \tern\586\samples\p52 for details on reading
the ADC. The sample program is also included in the pre-built sample project “p52.ide” in
\tern\186\samples\p52 and \tern\586\samples\p52.
Refer to the data sheet for additional specifications; \tern_docs\parts\ad7655.pdf.
3.3.5 Four channel, 16-bit DAC (DA8544)
The DA8544 is a parallel 16-bit D/A converter. This device supports 4 voltage output channels buffered by
ops with hardware configurable gain (default gain=2), giving default output range of ±5V. An on-board pot
allows for adjustable analog output voltage. The DAC requires an external 5V reference given by a
precision reference installed at U0.
The P52 uses data bus D15 to D0 to directly interface to the DAC’s full 16-bit data bus for maximum data
transfer rate. Four outputs are routed to J5.17-20.
A sample program “p52_da.c” is in the \tern\186\samples\p52 and \tern\586\samples\p52 directory.

P52 Hardware
3-5
3.3.6 100 MHz Base-T Ethernet
An WizNet™ Fast Ethernet Module can be installed to provide 100M Base-T network connectivity. This
Ethernet module has a hardware LSI TCP/IP stack. It implements TCP/IP, UDP, ICMP and ARP in
hardware, supporting internet protocol DLC and MAC. It has 16KB internal transmit and receiving buffer
which is mapped into host processor’s direct memory. The host can access the buffer via high speed DMA
transfers. The hardware Ethernet module releases internet connectivity and protocol processing from the
host processor. It supports 4 independent stack connections simultaneously at a 4Mbps protocol processing
speed. An RJ45 8-pin connector is on-board for connecting to 10/100 Base-T Ethernet network. A software
library is available for Ethernet connectivity.
3.3.7 Opto-couplers
There are 8 opto-couplers on the P52. These opto-couplers provide optical isolation and can be used for
digital inputs, relay contact monitor, or powerline monitor. These optos have a 3 micro-second ON time
and 5 micro-second OFF time. The on-board input pins have a 1kΩpullup, so a low input signal will turn
the coupler ON. Opto-coupler intputs are routed to pins J4.1-8.
3.3.8 High-Voltage, High-Current Drivers
ULN2003 (U13 and U14) are high voltage, high current Darlington transistor arrays, consisting of 7 silicon
NPN Darlington pairs on a common monolithic substrate. All channels feature open-collector outputs for
sinking 350 mA at 50V, and integral protection diodes for driving inductive loads. Peak inrush currents of
up to 600 mA sinking are allowed. Outputs may be paralleled to achieve high-load capability, although
each driver has a maximum continuous collector current rating of 350 mA at 50V. The maximum power
dissipation allowed is 2.20 W per chip at 25 degrees C. The common substrate VS is routed to J4 pin 31.
All currents sinking in must return to the J4 pin 31, which should be shorted to GND. A heavy gage(20)
wire must be used to connect the GND terminal to an external common ground return. K connects to the
protection diodes in the ULN2003 chips and should be tied to highest voltage in the external load system.
K can be connected to an unregulated on board +12V. ULN2003 is a sinking driver not sourcing driver.
Typical application wiring is shown below.
K +12V
+12V
GND/SUB
GND/SUB
Power Supply
Solenoid
O1
ULN2003 TinyDrive
Figure 3.2 Drive inductive load with high voltage/current drivers.

Chapter 3: Hardware P52
3-6
3.4 Headers and Connectors
Two 20x2, 0.1 spacing sockets are installed on the P52.
Figure 3.3 Pin header locations
J1 pin 1
J2 pin 1
H7 pin 1
H4 pin 1H3 pin 1H2 pin 1
J3 pin 1
J5 pin 1J4 pin 1
H8 pin 1
H0 pin 1

P52 Hardware
3-7
3.4.1 Jumpers and Headers
The jumpers and connectors on the P50 are listed below.
Name Size Function Possible Configuration
J1 20x2 main expansion port
J2 20x2 main expansion port
J3 20x2 PPI TTL I/Os / Q.D. signals PPI(U1), Q.D.(U6 and U8)
J4 17x2 HV and opto-couplers HV(U13 and U14), opto (P1-P8)
J5 10x2 ADC and DAC lines ADC(U15), ADC(U22) , DAC(U3)
H0 2x1 +12V Jumpers V+ from U19 to +12V. Board should not
take in any voltage higher than 12 Volts!
H1 2x1 +VI, GND Input voltage to board
H2 5x2 SER0 (DEBUG), RS232
H3 5x2 SER1, RS232
H4 5x2 SCC2691: RS232/485
TXD, RXD, GND
Install RS232 or RS485 driver for 3rd UART on the
host controller
H7 3x1 Ethernet chip select selector 586-Engine, jumper on pins 1&2
H8 2x1 VOFF Jumpers VOFF to Ground
3.4.2 Expansion Headers J1 and J2
J2 Signal
GND 40 39 VCC
38 37 /ET
36 35
TXD0 34 33 /INT
RXD0 32 31 /RTS1
30 29
TXD1 28 27
RXD1 26 25
24 23 P22
/CTS1 22 21 P21
20 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
GND 2 1
J1 Signal
VCC 1 2 GND
MPO 3 4 CLK
RXD 5 6 GND
TXD 7 8 D0
VOFF 9 10 D1
11 12 D2
D15 13 14 D3
/RST 15 16 D4
RST 17 18 D5
/CS6 19 20 D6
D14 21 22 D7
D13 23 24 GND
25 26 A7
D12 27 28 A6
/WR 29 30 A5
/RD 31 32 A4
D11 33 34 A3
D10 35 36 A2
D9 37 38 A1
D8 39 40 A0
Table 3.1 J1 and J2, 20x2 expansion ports for P52
Signal definitions for J1:
VCC +5V power supply
GND Ground
CLK Software programmable clock output from host

Chapter 3: Hardware P52
3-8
RxD data receive of UART SCC2691
TxD data transmit of UART SCC2691
MPO Multi-Purpose Output of SCC2691
VOFF real-time clock output
D0-D15 external data bus
A7-A0 lower address lines
/RST reset signal, active low
RST reset signal, active high
/CS6 8-bit chip select on the host
/WR active low when write operation
/RD active low when read operation
Signal definitions for J2:
VCC +5V power supply
GND Ground
Pxx PIO pins
TxD0 transmit data of serial channel 0
RxD0 receive data of serial channel 0
TxD1 transmit data of serial channel 1
RxD1 receive data of serial channel 1
/CTS1 Clear-to-Send signal for SER1
/RTS0 Request-to-Send signal for SER0
/RTS1 Request-to-Send signal for SER1

Appendix A: P52 mechanical dimensions A-1
___________________________________________________________________________________
Appendix A: P52 mechanical dimensions
U13 2982 AD
H2
J6
U3 DAC
U2 CS89
U1 PPI
J5
J4
J3
J1
J2
H3
H4
H1
U6 HP2020
U8 HP2020
U14 2003
HC14 HC14
1019 324
232
232
10BT
324
U5 PAL
P2
P1
P6
P3
P4
P5
P7
P8
SER0
SER1
SCC
12V
GND
0, 0
3.48, 0.18 4.27, 0.23
4.33, 0.68
1.88, 0.19
0.13, 0.13
4.33, 1.28
4.33, 2.03
4.43, 3.08
4.31, 2.73
2.18, 2.99
4.23, 0.78
3.37, 2,493.08, 2.99
0.11, 0.44
0.17, 0.59
0.33, 2.53
0.13, 2.73

Date: February 19, 2007 Sheet 1 of 1
Size Document Number REV
B P52.SCH
Title ET, I/O, DAC, ADC, HV, OPTO
TERN/STE
VCC
/HP1 D3
D1
D2
D4
D5
D6
A1
D0
CB1
CA1
D0
1
CLK
2
SEL
3
/OE
4
U/D
5
NC
6
/RST
7
CHB
8
CHA
9
VSS
10
VCC 20
D1 19
D2 18
D3 17
CNTC 16
CAS 15
D4 14
D5 13
D6 12
D7 11
U6
HP2020
/RST
T2
UD1
CLK
GND
T1
T2
Q12
1
Q6
2
Q5
3
Q7
4
Q4
5
Q3
6
Q2
7
GND
8
VCC 16
Q11 15
Q10 14
Q8 13
Q9 12
RST 11
CLK 10
Q1 9
U20
4040
VCC
V+ V-
D1-
V1
V2 V3
V4
D2- D3-
D4-
RE
RE RE
RE
A
1
A-
2
A+
3
V+
4
B+
5
B-
6
B
7
D14
D- 13
D+ 12
V- 11
C+ 10
C- 9
C8
U4
LM324S
D7
D6
D5
D4
D3
D2
D1
D0 AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
D1
3 Q1 2
D2
4 Q2 5
D3
7 Q3 6
D4
8 Q4 9
D5
13 Q5 12
D6
14 Q6 15
D7
17 Q7 16
D8
18 Q8 19
CLK
11
CLR
1
U2
74HC273
VCC
B00
B01
B02
B03
B04
B05
B06
GND
GND
D0
D2
/RST
10
9
8
7
6
5
4
3
2
1
RN2 10K
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
JP2
HD28
HD28
GND
GND
GND
GND
A7
A5 D1 D3
/RD
/INT
RST
AD9
AD11
AD13
VCC
D7
D6
D5
D4
B17
GND
A6
/WR
AD8
AD12
AD14
AD10
/ET
V33 1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
JP1
HD28
C1
D0
D1
D2
D3
RST
/WR /WR 40
P07
41
P06
42
P05
43
P04
44
NC
1
P03
2
P02
3
P01
4
P00
5
/RD
6
R
S
T
3
9
D
0
3
8
D
1
3
7
D
2
3
6
D
3
3
5
N
C
3
4
D
4
3
3
D
5
3
2
D
6
3
1
D
7
3
0
V
D
D
2
9
P17 28
P16 27
P15 26
P14 25
P13 24
NC 23
P12 22
P11 21
P10 20
P23 19
P22 18/
C
S
7
G
N
D
8
A
1
9
A
0
1
0
P
2
7
1
1
N
C
1
2
P
2
6
1
3
P
2
5
1
4
P
2
4
1
5
P
2
0
1
6
P
2
1
1
7
U1
PPIS
PPI8255
/RD
B00
B01
B02
B03
B04
B05
B06
B07 B16
B15
B14
B13
B12
B11
B10
B23
B22
A4
A2
A0
V33 V33
GNDGND
D5
D7
A3
A1
V33
10
9
8
7
6
5
4
3
2
1
RN3 10K VCC
I8
I7
I5
P1+
P2+
GND
GND
I+
1
I-
2 O+ 4
O- 3
P1
I+
1
I-
2 O+ 4
O- 3
P2
I+
1
I-
2 O+ 4
O- 3
P3
IN1
IN2
D4
D6
V33
I2
I1
/RST
/ADR
D
13 Q0 4
Q1 5
S0
1 Q2 6
S1
2 Q3 7
S2
3 Q4 9
Q5 10
G
14 Q6 11
CLR
15 Q7 12
U23
74HC259
D0
A1
A2
A0
D0
A1
A2
A0
W0
W1
W2
W3
W6
W7
B07 DA1 D1-
DA2
DA3
DA4
D2-
D3-
D4-
TEMP
VCC
1 2
3 4
5 6
7 8
RP1
10K
D
13 Q0 4
Q1 5
S0
1 Q2 6
S1
2 Q3 7
S2
3 Q4 9
Q5 10
G
14 Q6 11
CLR
15 Q7 12
U24
74HC259
S0
S1
S2
S3
S6
S7
V1
V2
V3
V4
REF
2.5V
NC
1
IN
2
TEMP
3
GND
4
NC 8
HEAT 7
OUT 6
TRIM 5
U17
LT1019
LT1019
1 2
3 4
5 6
7 8
RP2
10K
D7
VCC
D3
D1
D2
D4
D5
A1
D0
/RST
T2 D0
1
CLK
2
SEL
3
/OE
4
U/D
5
NC
6
/RST
7
CHB
8
CHA
9
VSS
10
VCC 20
D1 19
D2 18
D3 17
CNTC 16
CAS 15
D4 14
D5 13
D6 12
D7 11
U8
HP2020
/HP2
UD2
CB2
/HP1
/HP2
D6
D7
CA2
A4
A3
A5
/CS
/RST
/RDT
A
1
B
2
C
3
G1
6
G2A
4
G2B
5
Y0 15
Y1 14
Y2 13
Y3 12
Y4 11
Y5 10
Y6 9
Y7 7
U21
74HC138
/CV
/HV2
/HV1
VCC
D0
D1
D2
/RDT
1G
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
2Y1
9
GND
10
VCC 20
2G 19
1Y1 18
2A4 17
1Y2 16
2A3 15
1Y3 14
2A2 13
1Y4 12
2A1 11
U16
244V
74HC244
I2
I1
I6
D7
D6
D5
/RDT
I4
I5
I7
I8
S4
S5
1
2
3
H7
HDRS3
HDRS3
/ET
/MCS1
/MCS0
GND REF
REF
GND
GND
GND
ADA
ADB ADD
ADC
/RST
/HV1 /RST /HV2
W4
W5P3+
P4+
GND
GND
I+
1
I-
2 O+ 4
O- 3
P4
IN3
IN4
GND
DA3
DA2
RF5
I3
I4
GND
GND
DA1
RF5
RF5
I4
I2
I1
I6
I3
B21
B20
GND REF
REF
GND
GND
GND
AD0
AD1 AD3
AD2
C21
CAPNP C17 CAPNP
A1
A2
GND B24
B25
B26B27
/PPI
GND
NC-
NC+ NC
1
C+
2
G
3
C-
4
V+ 8
OS 7
LV 6
V- 5
U19
ICL7662
V-
V+
B00 B01
B02 B03
B04 B05
B06 B07
B22
B20 B23 B21
NC-
NC+
C24
10UF35V +12V
V+ 1
2
H0
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J3
D1
D0
GND
GND
A2
GND
GND
GND
AG
1
AV
2
A0
3
BYTE
4
A/B
5
DG
6
IMPUL
7
S/P
8
D0
9
D1
10
D2
11
D3
12
A
G
4
8
A
G
4
7
I
N
A
1
4
6
I
N
A
N
4
5
I
N
A
2
4
4
R
E
F
A
4
3
R
E
F
B
4
2
I
N
B
2
4
1
I
N
B
N
4
0
I
N
B
1
3
9
R
E
F
G
3
8
R
E
F
3
7
DV 36
CNV 35
PD 34
RST 33
CS 32
RD 31
EOC 30
BSY 29
D15 28
D14 27
D13 26
D12 25
D
4
1
3
D
5
1
4
D
6
1
5
D
7
1
6
O
G
N
D
1
7
O
V
1
8
D
V
1
9
D
G
N
D
2
0
D
8
2
1
D
9
2
2
D
1
0
2
3
D
1
1
2
4
U15
AD7655
AD7655
AD15
VCC
D14
D15
RST
/AD
VCC
GND
/RD
VCC
GND
GND
D14
D13
D12
D15
D11
D10
V
1
G
2
IOG
3
IVD
4
D15
5
D14
6
D13
7
D12
8
D11
9
D10
10
D9
11
D8
12
R
A
-
4
8
R
A
+
4
7
F
A
4
6
V
A
4
5
R
B
-
4
4
R
B
+
4
3
F
B
4
2
V
B
4
1
R
C
-
4
0
R
C
+
3
9
F
C
3
8
V
C
3
7
RD- 36
RD+ 35
FD 34
VD 33
V32
G31
/PD 30
RST 29
G28
LD 27
R/W 26
/CS 25
D
7
1
3
D
6
1
4
D
5
1
5
D
4
1
6
D
3
1
7
D
2
1
8
D
1
1
9
D
0
2
0
I
V
D
2
1
G
2
2
A
1
2
3
A
0
2
4
U3
DA8544
V33
/CV
LD
GND
RST
VCC
GND
GND
DA4
VCC
RF5 GND
GND
GND
GND
GND
AD15
VCC
D1
D0
A2
AG
1
AV
2
A0
3
BYTE
4
A/B
5
DG
6
IMPUL
7
S/P
8
D0
9
D1
10
D2
11
D3
12
A
G
4
8
A
G
4
7
I
N
A
1
4
6
I
N
A
N
4
5
I
N
A
2
4
4
R
E
F
A
4
3
R
E
F
B
4
2
I
N
B
2
4
1
I
N
B
N
4
0
I
N
B
1
3
9
R
E
F
G
3
8
R
E
F
3
7
DV 36
CNV 35
PD 34
RST 33
CS 32
RD 31
EOC 30
BSY 29
D15 28
D14 27
D13 26
D12 25
D
4
1
3
D
5
1
4
D
6
1
5
D
7
1
6
O
G
N
D
1
7
O
V
1
8
D
V
1
9
D
G
N
D
2
0
D
8
2
1
D
9
2
2
D
1
0
2
3
D
1
1
2
4
U22
AD7655
AD7655
C1+
C1-
C2+
C2-
V+
V-
D4
D14
D15
RST
VCC
GND
/RD
/AD1
/CV1
V-
C25
C8 C9
C20 VCC
GND
TXD1
RXD1
/TXD1
/RXD1
C1+
1
V+
2
C1-
3
C2+
4
C2-
5
V-
6
T2O
7
R2I
8
VCC 16
GND 15
T1O 14
R1I 13
R1O 12
T1I 11
T2I 10
R2O 9
U11
MAX232A
D3
I3
C1-
C1+
C2+
GND
V+
V-
REF
C19
R2
220
C15
C14
C10
C11
/CV1
C2-
C3-
C3+
C4-
C4+ VCC
R1
10K
R3
10K
RTS
RTS CTS
CTS
VCC R4
10K
C13
C12
/ET
VCC
GND
MPO
MPI
RXD0
TXD0
RTS
CTS
C1+
1
V+
2
C1-
3
C2+
4
C2-
5
V-
6
T2O
7
R2I
8
VCC 16
GND 15
T1O 14
R1I 13
R1O 12
T1I 11
T2I 10
R2O 9
U12
MAX232A
C3+
C3-
C4+
C4-
V+
V-
/TXD0
/RXD0
CK
1
I1
2
I2
3
I3
4
I4
5
I5
6
I6
7
I7
8
I8
9
G
10
5V 20
O7 19
O6 18
O5 17
O4 16
O3 15
O2 14
O1 13
O0 12
/OE 11
U5
PAL16V8
P52-P000.PDS
D13
D12
D7
D6
D5
D4 D11
D10
D9
D8
GND GNDD0
A2
A1
GND
/DA
R/W
V33
D3
D2D13
D12 D9 D8
D7
D6
D5
D4
D3U0
LM285
R0 2K
D7
D6
D5
D4
D3
D2
D11
D10
D9
D8
GND GND
CHB2
VCC
CHB1
VCC
B24 B25
B26 B27
B17B16 B15B14 B13B12 B11B10
VCCGND
UD2UD1
GND
IDX2
CHA2
GND
IDX1
CHA1
B21
B20
B24
B25
B26
B27
VCC
8
7
6
5
4
3
2
1
RN1 10K
AD0AD1
AD2 AD3
GNDTEMP
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
J5
VCC
RF5
VCC
GNDGND S0
S1
S2
S3
S4
S5
ADA ADB
ADC ADD
HV0
HV2
HV4
HV5
HV3
HV1
I1
1
I2
2
I3
3
I4
4
I5
5
I6
6
I7
7
I8
8
VS
9
O1 18
O2 17
O3 16
O4 15
O5 14
O6 13
O7 12
O8 11
G10
U14
UDS2982
D2RF5 V+
C06
CAPNP
W0
W1
W2
W3
W4
W5
HV8
HV9
HV10
HV11
HV12
HV13
I1
1
I2
2
I3
3
I4
4
I5
5
I6
6
I7
7
I8
8
VS
9
O1 18
O2 17
O3 16
O4 15
O5 14
O6 13
O7 12
O8 11
G10
U13
UDS2982
P5+
P6+
P7+
P8+
IN5
IN6
IN7
D1
A4
GND
A5
/RD
A6
A7
/WR
GND
GND
GND
I+
1
I-
2 O+ 4
O- 3
P5
I+
1
I-
2 O+ 4
O- 3
P6
I+
1
I-
2 O+ 4
O- 3
P7
I+
1
I-
2 O+ 4
O- 3
P8
/RTS1
/CTS1
/CS6
VCC
I6
I5
I7
I8
VCC
GND
/RXD
/TXD
/DA
/PPI
LD
/ADR
R/W
C00
/CS
/AD
/AD1
C3
TXD
RXD
VCC
RXD
TXD
MPO
GND CTS
RTS
RO
1
/RE
2
DE
3
DI
4
VCC 8
B7
A6
GND 5
U10
LTC485 +VI
K
VOFF 1
2
H8
1
2
H1
VCC R6
10K
/CS6
C18
VCC R7
10K
/INT
+12V+VI
GND
/TXD
/RXD RTS
CTS
1 2
3 4
5 6
7 8
9 10
H4
GND
D2
1N5817 C16
10UF35V
GND
GND
/TXD0
/RXD0
1 2
3 4
5 6
7 8
9 10
H2
1
2
J0
HDRD2
GND
VCC
GNG
1
VO
2
VI
3 VO 4
U18
BB1117
V33V33
C2
D6
D5
D4
D3
D2
D1
D0
VCC
VCC GND
/RST
RST
GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J1
HDRD40
/CS6
VOFF
RXD
TXD
MPO CLK
VCC
D15
GND
1
2
3
H5
HDRS3
GND
RXD0
TXD1
RXD1
TXD0
VCC
12 34 56 78 910 1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334 3536 3738 3940
J2
HDRD40
/RTS1
/CTS1
/INT
P21
P22 /MCS0
/MCS1
HV14
HV15 IN8
REF
RE
K
1 2
3 4
5 6
7 8
9 10
H3
+12V GND
V
I
N
1
V
O
U
T
2
G
N
D
3
F
B
4
O
F
F
/
O
N
5
U9 LM2575
HV6
HV7
K
R5
1M
VS
/TXD1
/RXD1
W6
W7
C4
C5
GND
V1 V2
V3 V4
REF
VS
HV0
HV2
HV4HV5
HV3
HV1
IN1 IN2
IN3 IN4
IN5 IN6
IN7 IN8
GNDGND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
J4
REF
C7
CAPNP
S6
S7
B23
B22
B17
B16
B15
B14
B13
B12
B11
B10
VCC
10
9
8
7
6
5
4
3
2
1
RN5 10K
UDS2982 VS=+VI K=GND
ULN2003 VS=GND K=+VI
P7+
VCC
10
9
8
7
6
5
4
3
2
1
RN4 10K
P5+
P4+
P3+
P6+
P1+
P8+
P2+
IN4 CUT!
C6
K
HV6HV7
HV8HV9 HV10HV11 HV12HV13 HV14HV15
GND
GND GND
VS +VI
LX1
VOFF VCC +12V
GND
I1
330 uH
RCH110
VCC
D1
1N5817 C01
CHB2
CA2
VCC
GND
1A
1
1Y
2
2A
3
2Y
4
3A
5
3Y
6
G
7
V14
6A 13
6Y 12
5A 11
5Y 10
4A 9
4Y 8
U7
74HC14
CHA1
CA1
CHB1
CB1
CHA2
CB2IDX1 IDX2
P22
P21 GND
D7
A1
A2
A3
A4
A5
A6
A7
GND
/WR
/RD
A0
D11
D10
D8
D9
D12
D13
D14