Texas Instruments TMS320DM355 User manual

TMS320DM355 Digital MediaSystem-on-Chip (DMSoC)ARM Subsystem
User's Guide
Literature Number: SPRUFB3September 2007

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Contents
Preface .............................................................................................................................. 13
1 Introduction ............................................................................................................. 161.1 Device Overview ........................................................................................................ 161.2 Block Diagram .......................................................................................................... 161.3 ARM Subsystem in DM355 .......................................................................................... 17
2 ARM Subsystem Overview ......................................................................................... 182.1 Purpose of the ARM Subsystem .................................................................................. 182.2 Components of the ARM Subsystem ........................................................................... 182.3 References ............................................................................................................... 19
3 ARM Core ................................................................................................................ 203.1 Introduction .............................................................................................................. 203.2 Operating States/Modes ............................................................................................. 213.3 Processor Status Registers ........................................................................................ 213.4 Exceptions and Exception Vectors .............................................................................. 223.5 The 16-BIS/32-BIS Concept ......................................................................................... 223.5.1 16-BIS/32-BIS Advantages .................................................................................... 223.6 Coprocessor 15 (CP15) .............................................................................................. 233.6.1 Addresses in an ARM926EJ-S System ...................................................................... 233.6.2 Memory Management Unit .................................................................................... 243.6.3 Caches and Write Buffer ...................................................................................... 253.7 Tightly Coupled Memory ............................................................................................ 263.8 Embedded Trace Support ........................................................................................... 27
4 Memory Mapping ...................................................................................................... 294.1 Memory Map ............................................................................................................. 294.1.1 ARM Internal Memories ........................................................................................ 304.1.2 External Memories.............................................................................................. 304.1.3 MPEG/JPEG Coprocessor (MJCP) .......................................................................... 314.1.4 Peripherals ...................................................................................................... 314.2 Memory Interfaces Overview ....................................................................................... 334.2.1 DDR2 EMIF ..................................................................................................... 334.2.2 External Memory Interface .................................................................................... 33
5 Device Clocking ....................................................................................................... 355.1 Overview .................................................................................................................. 355.2 Peripheral Clocking Considerations ............................................................................ 365.2.1 Video Processing Back End Clocking ....................................................................... 375.2.2 USB Clocking ................................................................................................... 37
6 PLL Controllers (PLLCs) ............................................................................................ 386.1 PLL Controller Module ............................................................................................... 386.2 PLLC1 ...................................................................................................................... 396.3 PLLC2 ...................................................................................................................... 406.4 PLLC Functional Description ...................................................................................... 41
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6.4.1 Multipliers and Dividers ........................................................................................ 416.4.2 Bypass Mode .................................................................................................... 416.4.3 PLL Mode ........................................................................................................ 416.5 PLL Configuration ..................................................................................................... 426.5.1 PLL Mode and Bypass Mode ................................................................................. 426.5.2 Changing Divider / Multiplier Ratios .......................................................................... 426.5.3 PLL Power Down and Wakeup ............................................................................... 446.6 PLL Controller Register Map ....................................................................................... 446.6.1 Introduction ...................................................................................................... 446.6.2 Peripheral ID Register (PID) .................................................................................. 466.6.3 PLL Control (PLLCTL) ......................................................................................... 476.6.4 PLL Multiplier Control Register (PLLM) ...................................................................... 486.6.5 PLL Pre-Divider Control Register (PREDIV) ................................................................ 496.6.6 PLL Controller Divider 1 Register (PLLDIV1) ............................................................... 506.6.7 PLL Controller Divider 2 Register (PLLDIV2) ............................................................... 516.6.8 PLL Controller Divider 3 Register (PLLDIV3) ............................................................... 526.6.9 PLL Post-Divider Control Register (POSTDIV) ............................................................. 536.6.10 Bypass Divider Register (BPDIV) ........................................................................... 546.6.11 PLL Controller Command Register (PLLCMD) ............................................................ 556.6.12 PLL Controller Status Register (PLLSTAT) ................................................................ 566.6.13 PLL Controller Clock Align Control Register (ALNCTL) .................................................. 576.6.14 PLLDIV Ratio Change Status Register (DCHANGE) ..................................................... 586.6.15 Clock Enable Control Register (CKEN) ..................................................................... 596.6.16 Clock Status Register (CKSTAT) ............................................................................ 606.6.17 SYSCLK Status Register (SYSTAT) ........................................................................ 616.6.18 PLL Controller Divider 4 Register (PLLDIV4) .............................................................. 62
7 Power and Sleep Controller ....................................................................................... 637.1 Introduction .............................................................................................................. 637.2 DM355 Power Domain and Module Topolgy .................................................................. 637.3 Power Domain and Module States Defined ................................................................... 667.3.1 Power Domain States .......................................................................................... 667.3.2 Module States ................................................................................................... 667.4 Executing State Transitions ........................................................................................ 677.4.1 Power Domain State Transitions ............................................................................. 677.4.2 Module State Transitions ...................................................................................... 677.5 IcePick Emulation Support in the PSC ......................................................................... 677.6 PSC Interrupts .......................................................................................................... 687.6.1 Interrupt Events ................................................................................................. 687.6.2 Interrupt Registers .............................................................................................. 697.6.3 Interrupt Handling ............................................................................................... 697.7 PSC Registers ........................................................................................................... 717.7.1 Peripheral Revision and Class Information (PID) .......................................................... 727.7.2 Interrupt Evaluation Register (INTEVAL) .................................................................... 737.7.3 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) ............................................. 747.7.4 Module Error Pending Register 1 (mod 32 - 41) (MERRPR1) ............................................ 757.7.5 Module Error Clear Register 0 (mod 0-31) (MERRCR0) .................................................. 767.7.6 Module Error Clear Register 1 (mod 32-41) (MERRCR1)................................................. 77
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7.7.7 Power Error Pending Register (PERRPR) .................................................................. 787.7.8 Power Error Clear Register (PERRCR)...................................................................... 797.7.9 External Power Control Pending Register (EPCPR) ....................................................... 807.7.10 External Power Control Clear Register (EPCCR) ......................................................... 817.7.11 Power Domain Transition Command Register (PTCMD) ................................................ 827.7.12 Power Domain Transition Status Register (PTSTAT) .................................................... 837.7.13 Power Domain Status Register 0 (PDSTATn) ............................................................. 847.7.14 Power Domain Control n Register 0 (PDCTLn) ........................................................... 857.7.15 Module Status n Register 0-41 (MDSTATn) ............................................................... 867.7.16 Module Control n Register 0-41 (MDCTLn) ................................................................ 87
8 Interrupt Controller ................................................................................................... 888.1 Introduction .............................................................................................................. 888.2 Interrupt Mapping ...................................................................................................... 888.3 INTC Methodology ..................................................................................................... 898.3.1 Interrupt Mapping ............................................................................................... 908.3.2 Interrupt Prioritization .......................................................................................... 908.3.3 Vector Table Entry Address Generation ..................................................................... 918.3.4 Clearing Interrupts .............................................................................................. 918.3.5 Enabling and Disabling Interrupts ............................................................................ 928.4 INTC Registers .......................................................................................................... 938.4.1 Fast Interrupt Request Status Register 0 (FIQ0) ........................................................... 948.4.2 Fast Interrupt Request Status Register 1 (FIQ1) ........................................................... 958.4.3 Interrupt Request Status Register 0 (IRQ0) ................................................................. 968.4.4 Interrupt Request Status Register 1 (IRQ1) ................................................................. 978.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) ............................................ 988.4.6 Interrupt Request Entry Address Register (IRQENTRY) .................................................. 998.4.7 Interrupt Enable Register 0 (EINT0) ........................................................................ 1008.4.8 Interrupt Enable Register 1 (EINT1) ........................................................................ 1018.4.9 Interrupt Operation Control Register (INTCTL) ........................................................... 1028.4.10 EABASE ....................................................................................................... 1038.4.11 Interrupt Priority Register 0 (INTPRI0) ................................................................... 1048.4.12 Interrupt Priority Register 1 (INTPRI1) .................................................................... 1058.4.13 Interrupt Priority Register 2 (INTPRI2) .................................................................... 1068.4.14 Interrupt Priority Register 3 (INTPRI3) .................................................................... 1078.4.15 Interrupt Priority Register 4 (INTPRI4) .................................................................... 1088.4.16 Interrupt Priority Register 5 (INTPRI5) .................................................................... 1098.4.17 Interrupt Priority Register 6 (INTPRI6) .................................................................... 1108.4.18 Interrupt Priority Register 7 (INTPRI7) .................................................................... 111
9 System Control Module ........................................................................................... 1129.1 Overview of the System Control Module ..................................................................... 1129.2 Device Identification ................................................................................................. 1129.3 Device Configuration ................................................................................................ 1129.3.1 Pin Multiplexing Control ..................................................................................... 1129.3.2 Device Boot Configuration Status ........................................................................... 1139.4 ARM Interrupt and EDMA Event Multiplexing Control ................................................... 1139.5 Special Peripheral Status and Control ........................................................................ 1139.5.1 Timer64+ Control .............................................................................................. 113
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9.5.2 USB PHY Control ............................................................................................. 1149.5.3 VPSS Clock and DAC Control and Status ................................................................. 1149.5.4 DDR I/O Timing Control and Status ........................................................................ 1149.6 Clock Out Configuration Status ................................................................................. 1149.7 GIO De-Bounce Control ............................................................................................ 1149.8 Power Managment ................................................................................................... 1149.8.1 Deep Sleep Control ........................................................................................... 1149.9 Bandwidth Management ........................................................................................... 1159.9.1 Bus Master DMA Priority Control ........................................................................... 1159.10 System Control Register Descriptions ........................................................................ 1179.10.1 Introduction ................................................................................................... 1179.10.2 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register .................................................... 1189.10.3 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register ................................................... 1209.10.4 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register ...................................................... 1229.10.5 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register .................................................... 1249.10.6 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register ......................................................... 1279.10.7 BOOTCFG - Boot Configuration ........................................................................... 1289.10.8 ARM_INTMUX - ARM Interrupt Mux Control Register .................................................. 1299.10.9 EDMA_EVTMUX - EDMA Event Mux Control Register ................................................ 1309.10.10 DDR_SLEW - DDR Slew .................................................................................. 1319.10.11 CLKOUT - CLKOUT Divisor / Output Control .......................................................... 1329.10.12 DEVICE_ID - Device ID ................................................................................... 1339.10.13 VDAC_CONFIG - Video Dac Configuration ............................................................. 1349.10.14 TIMER64_CTL - Timer64+ Input Control ............................................................... 1359.10.15 USB_PHY_CTRL - USB PHY Control .................................................................. 1369.10.16 MISC - Miscellaneous Control ........................................................................... 1389.10.17 MSTPRI0 - Master Priorities 0 ........................................................................... 1399.10.18 MSTPRI1 - Master Priorities 1 ............................................................................ 1409.10.19 VPSS_CLK_CTRL - VPSS Clock Mux Control ........................................................ 1419.10.20 DEEPSLEEP - Deep Sleep Mode Configuration ...................................................... 1429.10.21 DEBOUNCE[8] - De-bounce for GIO[n] Input .......................................................... 1439.10.22 VTPIOCR - VTP IO Control Register .................................................................... 144
10 Reset ..................................................................................................................... 14510.1 Reset Overview ....................................................................................................... 14510.2 Reset Pins .............................................................................................................. 14510.3 Types of Reset ........................................................................................................ 14610.3.1 Power-On Reset (POR) ..................................................................................... 14610.3.2 Warm Reset .................................................................................................. 14610.3.3 Max Reset ..................................................................................................... 14710.3.4 System Reset ................................................................................................. 14710.3.5 Module Reset ................................................................................................. 14710.4 Default Device Configurations ................................................................................... 14710.4.1 Device Configuration Pins .................................................................................. 14710.4.2 PLL Configuration ............................................................................................ 14810.4.3 Module Configuration ........................................................................................ 14810.4.4 ARM Boot Mode Configuration ............................................................................. 14810.4.5 AEMIF Configuration ........................................................................................ 149
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11 Boot Modes ............................................................................................................ 15011.1 Boot Modes Overview .............................................................................................. 15011.1.1 Features ....................................................................................................... 15011.1.2 Functional Block Diagram ................................................................................... 15211.2 ARM ROM Boot Modes ............................................................................................. 15211.2.1 NAND Boot Mode ............................................................................................ 15211.2.2 MMC/SD Boot Mode ......................................................................................... 16211.2.3 UART Boot Mode ............................................................................................ 167
12 Power Management ................................................................................................. 17112.1 Overview ................................................................................................................ 17112.2 PSC and PLLC Overview .......................................................................................... 17112.3 Clock Management .................................................................................................. 17212.3.1 Module Clock Disable ....................................................................................... 17212.3.2 Module Clock Frequency Scaling .......................................................................... 17212.3.3 PLL Bypass and Power Down .............................................................................. 17212.4 ARM Sleep Mode Management .................................................................................. 17212.4.1 ARM Wait-For-Interrupt Sleep Mode ...................................................................... 17212.5 System Sleep Modes ................................................................................................ 17312.5.1 Deep Sleep Mode ............................................................................................ 17312.5.2 Fast NAND Boot Mode ...................................................................................... 17312.6 I/O Management ....................................................................................................... 17412.6.1 USB Phy Power Down ...................................................................................... 17412.6.2 Video DAC Power Down .................................................................................... 17412.6.3 DDR Selft-Refresh and Power Down ...................................................................... 174
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List of Figures
1-1 DM355 Functional Block Diagram ....................................................................................... 172-1 DM355 ARM Subsystem Block Diagram ................................................................................ 195-1 DM355 Clocking Architecture ............................................................................................. 366-1 PLLC1 Configuration in DM355 .......................................................................................... 406-2 PLLC2 Configuration in DM355 .......................................................................................... 416-3 Clock Ratio Change and Alignment with Go Operation ............................................................... 436-4 Peripheral ID Register (PID) .............................................................................................. 466-5 PLL Control Register (PLLCTL) .......................................................................................... 476-6 PLL Multiplier Control Register (PLLM) ................................................................................. 486-7 PLL Pre-Divider Control Register (PREDIV) ............................................................................ 496-8 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 506-9 PLL Controller Divider 2 Register (PLLDIV2) .......................................................................... 516-10 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 526-11 PLL Post-Divider Control Register (POSTDIV) ......................................................................... 536-12 Bypass Divider Register (BPDIV) ........................................................................................ 546-13 PLL Controller Command Register (PLLCMD) ......................................................................... 556-14 PLL Controller Status Register (PLLSTAT) ............................................................................. 566-15 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 576-16 PLLDIV Ratio Change Status (DCHANGE) ............................................................................. 586-17 Clock Enable Control Register (CKEN) ................................................................................. 596-18 Clock Status Register (CKSTAT) ........................................................................................ 606-19 SYSCLK Status Register (SYSTAT) ..................................................................................... 616-20 PLL Controller Divider 4 Register (PLLDIV4) .......................................................................... 627-1 DM355 Power and Sleep Controller (PSC) ............................................................................. 637-2 DM355 Power Domain and Module Topology .......................................................................... 647-3 Peripheral Revision and Class Information Register (PID) ........................................................... 727-4 Interrupt Evaluation Register (INTEVAL) ................................................................................ 737-5 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) ......................................................... 747-6 Module Error Pending Register 1 (mod 32 - 41) (MERRPR1) ....................................................... 757-7 Module Error Clear Register 0 (mod 0-31) (MERRCR0) .............................................................. 767-8 Module Error Clear Register 1 (mod 32-41) (MERRCR1) ............................................................ 777-9 Power Error Pending Register (PERRPR) .............................................................................. 787-10 Power Error Clear Register (PERRCR) ................................................................................. 797-11 External Power Control Pending Register (EPCPR) .................................................................. 807-12 External Power Control Clear Register (EPCCR) ...................................................................... 817-13 Power Domain Transition Command Register (PTCMD) ............................................................. 827-14 Power Domain Transition Status Register (PTSTAT) ................................................................. 837-15 Power Domain Status n Register (PDSTATn) .......................................................................... 847-16 Power Domain Control n Register (PDCTLn) .......................................................................... 857-17 Module Status n Register (MDSTATn) .................................................................................. 867-18 Module Control n Register 0-41 (MDCTLn) ............................................................................. 878-1 AINTC Functional Diagram ............................................................................................... 908-2 Interrupt Entry Table ...................................................................................................... 918-3 Immediate Interrupt Disable / Enable .................................................................................... 928-4 Delayed Interrupt Disable ................................................................................................. 928-5 Interrupt Status of INT[31:0] (if mapped to FIQ) ....................................................................... 948-6 Interrupt Status of INT[63:32] (if mapped to FIQ) ...................................................................... 958-7 Interrupt Status of INT[31:0] (if mapped to IRQ) ....................................................................... 968-8 Interrupt Status of INT[31:0] (if mapped to IRQ) ...................................................................... 978-9 Fast Interrupt Request Entry Address Register (FIQENTRY) ........................................................ 988-10 Interrupt Request Entry Address Register (IRQENTRY) .............................................................. 998-11 Interrupt Enable Register 0 (EINT0) .................................................................................... 100
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8-12 Interrupt Enable Register 1 (EINT1) .................................................................................... 1018-13 Interrupt Operation Control Register (INTCTL) ....................................................................... 1028-14 EABASE ................................................................................................................... 1038-15 Interrupt Priority Register 0 (INTPRI0) ................................................................................. 1048-16 Interrupt Priority Register 1 (INTPRI1) ................................................................................. 1058-17 Interrupt Priority Register 2 (INTPRI2) ................................................................................. 1068-18 Interrupt Priority Register 3 (INTPRI3) ................................................................................. 1078-19 Interrupt Priority Register 4 (INTPRI4) ................................................................................. 1088-20 Interrupt Priority Register 5 (INTPRI5) ................................................................................. 1098-21 Interrupt Priority Register 6 (INTPRI6) ................................................................................. 1108-22 Interrupt Priority Register 7 (INTPRI7) ................................................................................. 1119-1 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register .................................................................. 1189-2 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register................................................................ 1209-3 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register ................................................................... 1229-4 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register ................................................................ 1249-5 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register ...................................................................... 1279-6 BOOTCFG - Boot Configuration ........................................................................................ 1289-7 ARM_INTMUX - ARM Interrupt Mux Control Register ............................................................... 1299-8 EDMA_EVTMUX - EDMA Event Mux Control Register ............................................................. 1309-9 DDR_SLEW - DDR Slew ................................................................................................ 1319-10 CLKOUT - CLKOUT div/out Control ................................................................................... 1329-11 DEVICE_ID - Device ID .................................................................................................. 1339-12 VDAC_CONFIG - Video Dac Configuration ........................................................................... 1349-13 TIMER64_CTL - Timer64+ Input Control ............................................................................. 1359-14 USB_PHY_CTRL - USB PHY Control ................................................................................ 1369-15 MISC - Miscellaneous Control .......................................................................................... 1389-16 MSTPRI0 - Master Priorities 0 ......................................................................................... 1399-17 MSTPRI1 - Master Priorities 1 .......................................................................................... 1409-18 VPSS_CLK_CTRL - VPSS Clock Mux Control ...................................................................... 1419-19 DEEPSLEEP - Deep Sleep Mode Configuration ..................................................................... 1429-20 DEBOUNCE[8] - De-bounce for GIO[n] Input ......................................................................... 1439-21 VTP IO Control Register (VTPIOCR) .................................................................................. 14411-1 Boot Modes Overview .................................................................................................... 15111-2 Boot Mode Functional Block Diagram ................................................................................. 15211-3 NAND Boot Flow .......................................................................................................... 15311-4 4-Bit ECC Format and Bit 10 to 8-Bit Compression Algorithm ..................................................... 15511-5 4-Bit ECC Format for 2048+64 Byte Page Size ...................................................................... 15611-6 NAND Boot Mode Flow Chart ........................................................................................... 15811-7 ARM NAND ROM Boot Loader Example .............................................................................. 15911-8 Descriptor Search for ARM NAND Boot Mode ....................................................................... 16011-9 MMC/SD Boot Mode Overview ......................................................................................... 16311-10 MMC/SD Boot Mode Flow Chart ....................................................................................... 16511-11 ARM MMC/SD ROM Boot Loader Example ........................................................................... 16611-12 Descriptor Search for ARM MMC/SD Boot Mode .................................................................... 16711-13 UART Boot Mode Handshake ........................................................................................... 16811-14 Host Utility Timing ........................................................................................................ 170
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List of Tables
3-1 Exception Vector Table for ARM ......................................................................................... 223-2 Different Address Types in ARM System ............................................................................... 233-3 ITCM/DTCM Memory Map ................................................................................................ 263-4 ITCM/DTCM Size Encoding............................................................................................... 273-5 ETM Part Descriptions ..................................................................................................... 274-1 DM355 Memory Map ...................................................................................................... 294-2 DM355 ARM Configuration Bus Access to Peripherals ............................................................... 316-1 PLLC1 Output Clocks ...................................................................................................... 396-2 PLLC2 Output Clocks ...................................................................................................... 406-3 PLL and Reset Controller Module Instance Table ..................................................................... 446-4 PLLC Registers ............................................................................................................. 446-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 466-6 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 476-7 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 486-8 PLL Pre-Divider Control (PREDIV) Field Descriptions ................................................................ 496-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 506-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 516-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 526-12 PLL Post-Divider Control (POSTDIV) Field Descriptions ............................................................. 536-13 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 546-14 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 556-15 PLL Controller Status (PLLSTAT) Field Descriptions ................................................................. 566-16 PLL Controller Clock Align Control (ALNCTL) Field Descriptions ................................................... 576-17 PLLDIV Ratio Change Status (DCHANGE) Field Descriptions ...................................................... 586-18 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 596-19 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 606-20 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 616-21 PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions .................................................... 627-1 Module Configuration ...................................................................................................... 657-2 Module States .............................................................................................................. 667-3 IcePick Emulation Commands ............................................................................................ 677-4 PSC Interrupt Events ...................................................................................................... 687-5 PSC Registers .............................................................................................................. 717-6 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 727-7 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 737-8 Module Error Pending Register 0 (mod 0 - 31) (MERRPR0) Field Descriptions .................................. 747-9 Module Error Pending Register 1 (mod 32 - 41) (MERRPR1) Field Descriptions ................................. 757-10 Module Error Clear Register 0 (mod 0-31) (MERRCR0) Field Descriptions ....................................... 767-11 Module Error Clear Register 1 (mod 32-41) (MERRCR1) Field Descriptions ...................................... 777-12 Power Error Pending Register (PERRPR) Field Descriptions ........................................................ 787-13 Power Error Clear Register (PERRCR) Field Descriptions ........................................................... 797-14 External Power Control Pending Register (EPCPR) Field Descriptions ............................................ 807-15 External Power Control Clear Register (EPCCR) Field Descriptions ............................................... 817-16 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 827-17 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 837-18 Power Domain Status n Register (PDSTATn) Field Descriptions ................................................... 847-19 Power Domain Control n Register (PDCTLn) Field Descriptions .................................................... 857-20 Module Status n Register 0-41 (MDSTATn) Field Descriptions ...................................................... 867-21 Module Control n Register 0-41 (MDCTLn) Field Descriptions ...................................................... 87
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8-1 AINTC Interrupt Connections ............................................................................................. 888-2 Interrupt Controller (INTC) Registers .................................................................................... 938-3 Interrupt Status of INT[31:0] (if mapped to FIQ) Field Descriptions ................................................. 948-4 Interrupt Status of INT[63:32] (if mapped to FIQ) Field Descriptions ................................................ 958-5 Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions ................................................. 968-6 Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions ................................................. 978-7 Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions .................................. 988-8 Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions ....................................... 998-9 Interrupt Enable Register 0 (EINT0) Field Descriptions ............................................................. 1008-10 Interrupt Enable Register 1 (EINT1) Field Descriptions ............................................................. 1018-11 Interrupt Operation Control Register (INTCTL) Field Descriptions ................................................. 1028-12 EABASE Field Descriptions ............................................................................................. 1038-13 Interrupt Priority Register 0 (INTPRI0) Field Descriptions ........................................................... 1048-14 Interrupt Priority Register 1 (INTPRI1) Field Descriptions ........................................................... 1058-15 Interrupt Priority Register 2 (INTPRI2) Field Descriptions ........................................................... 1068-16 Interrupt Priority Register 3 (INTPRI3) Field Descriptions ........................................................... 1078-17 Interrupt Priority Register 4 (INTPRI4) Field Descriptions ........................................................... 1088-18 Interrupt Priority Register 5 (INTPRI5) Field Descriptions ........................................................... 1098-19 Interrupt Priority Register 6 (INTPRI6) Field Descriptions ........................................................... 1108-20 Interrupt Priority Register 7 (INTPRI7) Field Descriptions ........................................................... 1119-1 DM355 Master IDs ........................................................................................................ 1159-2 DM355 Default Master Priorities ........................................................................................ 1169-3 System Module (SYS) Registers ....................................................................................... 1179-4 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions ........................................... 1189-5 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions ......................................... 1209-6 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions ............................................. 1229-7 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions .......................................... 1249-8 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Field Descriptions ................................................ 1279-9 BOOTCFG - Boot Configuration Field Descriptions .................................................................. 1289-10 ARM_INTMUX - ARM Interrupt Mux Control Register Field Descriptions ........................................ 1299-11 EDMA_EVTMUX - EDMA Event Mux Control Register Field Descriptions ....................................... 1309-12 DDR_SLEW - DDR Slew Field Descriptions .......................................................................... 1319-13 CLKOUT - CLKOUT div/out Control Field Descriptions ............................................................. 1329-14 DEVICE_ID - Device ID Field Descriptions ........................................................................... 1339-15 VDAC_CONFIG - Video Dac Configuration Field Descriptions ..................................................... 1349-16 TIMER64_CTL - Timer64+ Input Control Field Descriptions ........................................................ 1359-17 USB_PHY_CTRL - USB PHY Control Field Descriptions ........................................................... 1369-18 MISC - Miscellaneous Control Field Descriptions .................................................................... 1389-19 MSTPRI0 - Master Priorities 0 Field Descriptions .................................................................... 1399-20 MSTPRI1 - Master Priorities 1 Field Descriptions .................................................................... 1409-21 VPSS_CLK_CTRL - VPSS Clock Mux Control Field Descriptions ................................................. 1419-22 DEEPSLEEP - Deep Sleep Mode Configuration Field Descriptions ............................................... 1429-23 DEBOUNCE[8] - De-bounce for GIO[n] Input Field Descriptions .................................................. 1439-24 VTPIOCR - VTP IO Control Field Descriptions ....................................................................... 14410-1 Reset Types ............................................................................................................... 14510-2 Reset Pins ................................................................................................................. 14510-3 Device Configuration ..................................................................................................... 14811-1 NAND UBL Descriptor ................................................................................................... 15411-2 UBL Signatures and Special Modes ................................................................................... 15411-3 NAND IDs Supported..................................................................................................... 16011-4 MMC/SD UBL Descriptor ................................................................................................ 164
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11-5 MMC/SD UBL Signatures and Special Modes ........................................................................ 16411-6 UART Data Sequences .................................................................................................. 16911-7 Host Utility Data Format ................................................................................................. 17011-8 CRC32 Table Transfer ................................................................................................... 17012-1 Power Management Features ........................................................................................... 171
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PrefaceSPRUFB3 – September 2007
Read This First
About This Manual
Describes the operation of the ARM subsystem in the TMS320DM355 Digital Media System-on-Chip(DMSoC).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
TMS320DM355 Digital Media System-on-Chip (DMSoC)
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM355 Digital Media System-on-Chip (DMSoC). Copies ofthese documents are available on the internet at www.ti.com. Contact your TI representative for Extranetaccess.
SPRS463— TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This documentdescribes the overall TMS320DM355 system, including device architecture and features, memorymap, pin descriptions, timing characteristics and requirements, device mechanicals, etc.
SPRZ264— TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functionalspecifications for the TMS320DM355 DMSoC.
SPRUFB3— TMS320DM355 ARM Subsystem Reference Guide This document describes the ARMSubsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the components of the ARMSubsystem, the peripherals, and the external memories.
SPRUED1— TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) ReferenceGuide This document describes the asynchronous external memory interface (EMIF) in theTMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface toa variety of external devices.
SPRUED2— TMS320DM35x DMSoC Universal Serial Bus (USB) Controller Reference Guide Thisdocument describes the universal serial bus (USB) controller in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. Itprovides a mechanism for data transfer between USB devices and also supports host negotiation.
SPRUED3— TMS320DM35x DMSoC Audio Serial Port (ASP) Reference Guide This documentdescribes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x DigitalMedia System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are theAC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial portreceive and transmit operation, but is not intended to be used as a high-speed interface.
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUED4— TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide Thisdocument describes the serial peripheral interface (SPI) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allowsa serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at aprogrammed bit-transfer rate. The SPI is normally used for communication between the DMSoCand external peripherals. Typical applications include an interface to external I/O or peripheralexpansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digitalconverters.
SPRUED9— TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART)Reference Guide This document describes the universal asynchronous receiver/transmitter(UART) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The UARTperipheral performs serial-to-parallel conversion on data received from a peripheral device, andparallel-to-serial conversion on data received from the CPU.
SPRUEE0— TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Peripheral Reference Guide Thisdocument describes the inter-integrated circuit (I2C) peripheral in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and otherdevices compliant with the I2C-bus specification and connected by way of an I2C-bus. Externalcomponents attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to andfrom the DMSoC through the I2C peripheral. This document assumes the reader is familiar with theI2C-bus specification.
SPRUEE2— TMS320DM35x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card ControllerReference Guide This document describes the multimedia card (MMC)/secure digital (SD) cardcontroller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The MMC/SD card isused in a number of applications to provide removable data storage. The MMC/SD controllerprovides an interface to external MMC and SD cards. The communication between the MMC/SDcontroller and MMC/SD card(s) is performed by the MMC/SD protocol.
SPRUEE4— TMS320DM35x DMSoC Enhanced Direct Memory Access (EDMA) Controller ReferenceGuide This document describes the operation of the enhanced direct memory access (EDMA3)controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The EDMA controller'sprimary purpose is to service user-programmed data transfers between two memory-mapped slaveendpoints on the DMSoC.
SPRUEE5— TMS320DM35x DMSoC 64-bit Timer Reference Guide This document describes theoperation of the software-programmable 64-bit timers in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used as general-purpose (GP) timersand can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode;Timer 2 is used only as a watchdog timer. The GP timer modes can be used to generate periodicinterrupts or enhanced direct memory access (EDMA) synchronization events and Real TimeOutput (RTO) events (Timer 3 only). The watchdog timer mode is used to provide a recoverymechanism for the device in the event of a fault condition, such as a non-exiting code loop.
SPRUEE6— TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) Reference Guide Thisdocument describes the general-purpose input/output (GPIO) peripheral in the TMS320DM35xDigital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purposepins that can be configured as either inputs or outputs. When configured as an input, you candetect the state of the input by reading the state of an internal register. When configured as anoutput, you can write to an internal register to control the state driven on the output pin.
SPRUEE7— TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This documentdescribes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUEH7— TMS320DM35x DMSoC DDR2/Mobile DDR (DDR2/mDDR) Memory ControllerReference Guide This document describes the DDR2 / mobile DDR memory controller in theTMS320DM35x Digital Media System-on-Chip (DMSoC). The DDR2 / mDDR memory controller isused to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices.
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
SPRUF71— TMS320DM35x DMSoC Video Processing Front End (VPFE) Users Guide This documentdescribes the Video Processing Front End (VPFE) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUF72— TMS320DM35x DMSoC Video Processing Back End (VPBE) Users Guide This documentdescribes the Video Processing Back End (VPBE) in the TMS320DM35x Digital MediaSystem-on-Chip (DMSoC).
SPRUF74— TMS320DM35x DMSoC Real Time Out (RTO) Controller Reference Guide This documentdescribes the Real Time Out (RTO) controller in the TMS320DM35x Digital Media System-on-Chip(DMSoC).
SPRUFC8— TMS320DM355 DMSoC Peripherals Overview Reference Guide This document providesan overview of the peripherals in the TMS320DM355 Digital Media System-on-Chip (DMSoC).
The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are notavailable by literature number. Copies of these documents are available (by title only) on the internet atwww.ti.com. Contact your TI representative for Extranet access.
—TMS320DM35x DDR2 / mDDR Board Design Application Note This provides board designrecommendations and guidelines for DDR2 and mobile DDR.
—TMS320DM35x USB Board Design and Layout Guidelines Application Note This providesboard design recommendations and guidelines for high speed USB.
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1.1 Device Overview
1.2 Block Diagram
SPRUFB3 – September 2007
Introduction
DM355 is a highly integrated, programmable Digital Media System-on-Chip (DMSoC) platform for digitalstill camera and mobile systems that require digital media encode and decode capabilities. Designed tooffer end-equipment manufacturers the ability to produce affordable DSC products with high picturequality, DM355 combines programmable image processing capability with a highly integrated set ofimaging peripherals. The chip's programmability comes from an ARM926 RISC processor core andspecialized Imaging Coprocessors.
Together, these elements enable camera manufacturers to implement proprietary image processingalgorithms in software. DM355 also enables a seamless interface to most additional external devicesrequired for a complete digital camera digital implementation. The interface is flexible enough to supportvarious types of CCD and CMOS sensors; signal conditioning circuits; power management; DDR2/mDDRSDRAM; and shutter, Iris, and auto-focus motor controls. DM355 allows camera manufacturers to meetcustomer demands by fulfilling both image quality and low cost expectations required in the volume pointand shoot digital still camera segment.
The DM355 Digital Media System-on-Chip (DMSoC) consists of the following primary components andsub-systems:
•ARM Subsystem (ARMSS), including the ARM926 RISC CPU core and associated memories•Video Processing Subsystem (VPSS), including the Video Processing Front End (VPFE), Image Inputand Image Processing Subsystem, and the Video Processing Back End (VPBE) Display Subsystem•A set of I/O peripherals•A powerful DMA Subsystem and DDR2/mDDR EMIF interface
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Peripherals
64bit DMA/Data Bus
JTAG 24 MHz 27 MHz
(optional)
CCD/
CMOS
Module
DDR2/MDDR 16
CLOCK
PLL
CLOCK ctrl
PLLs
JTA
JTAG
I/F
Clocks
ARM
z )
ARM926EJ-S_Z8
I-cach
e
16 K
B
l-cache
16KB
B
RA
M
32 K
B
RAM
32KB
B
D-cach
e
8K
D-cache
8KB
RO
M
8 K
ROM
8KB
CCD
C
CCDC
3A
3A
DMA / Data and configuration bus
DMA/Data and configuration bus
DDR
MH
z )
DDR
controller
DL
DLL/
PHY
16 bit
32bit Configuration Bus
IPIP
E
IPIPE
VPBE
Vide
o
Encod
er
Video
Encoder
10b
DAC OS
D
OSD
er
c
ARM
ARM INTC
Enhanced
channels
3PCC /TC
(100 MHz
Enhanced DMA
64 channels
Composite video
Digital RGB/YUV
Nand /
Nand/SM/
Async/One Nand
(EMIF2.3)
USB 2.0
USB2.0 PHY
Speaker
microphone
LD /
ASP (2x)
LD/CM
Buffer Logic
VPSS
MMC/SD (x2)
SPI I/F (x3)
UART (x3)
I2C
Timer/
WDT (x4 - 64)
GIO
PWM (x4)
RTO
VPFE
Enhanced
channels
3PCC /TC
(100 MHz
MPEG/JPEG
Coprocessor
1.3 ARM Subsystem in DM355
ARM Subsystem in DM355
The detailed DM355 block diagram is shown in Figure 1-1 .
Figure 1-1. DM355 Functional Block Diagram
The ARM926EJ-S 32-bit RISC processor in the ARMSS acts as the overall system controller. The ARMCPU performs general system control tasks, such as system initialization, configuration, powermanagement, user interface, and user command implementation. Chapter 2 describes the ARMSScomponents and system control functions that the ARM core performs.
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2.1 Purpose of the ARM Subsystem
2.2 Components of the ARM Subsystem
SPRUFB3 – September 2007
ARM Subsystem Overview
The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control ofthe overall DM355 system, including control over the VPSS Subsystem, the peripherals, and externalmemories.
The ARM is responsible for handling system functions such as system-level initialization, configuration,user interface, user command execution, connectivity functions, etc. The ARM is master and performsthese functions because it has a large program memory space and fast context switching capability, and isthus suitable for complex, multi-tasking, and general-purpose control tasks.
The ARM Subsystem (ARMSS) in DM355 consists of the following components:•ARM926EJ-S RISC processor, including:– Coprocessor 15 (CP15)– MMU
– 16KB Instruction cache– 8KB Data cache– Write Buffer– Java accelerator•ARM Internal Memories– 32KB Internal RAM (32-bit wide access)– 8KB Internal ROM (ARM bootloader for non-AEMIF boot options)•Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)•System Control Peripherals– ARM Interrupt Controller– PLL Controller
– Power and Sleep Controller– System Module
The ARM also manages/controls the following peripherals:•DDR2 EMIF Controller•AEMIF Controller, including the NAND flash interface•Enhanced DMA (EDMA)•UART (There are three UARTs supported in DM355.)•Timers
•Real Time Out (RTO)•Pulse Width Modulator (PWM)•Inter-IC Communication (I2C)•Multi-Media Card/Secure Digital (MMC/SD)•Audio Serial Port (ASP)•Universal Serial Bus Controller (USB)•Serial Port Interface (SPI)
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ARM926EJ-S
16K I$
8K D$ MMU
CP15
Arbiter Arbiter
I-AHB
D-AHB
Master
IF
DMA bus
I-TCM
D-TCM
16K
RAM0
RAM1
16K
ROM
8K
Arbiter
Slave
IF
Master IF
CFG bus
ARM
interrupt
controller
(AINTC)
control
System
PLLC2
PLLC1
(PSC)
controller
sleep
Power
Peripherals
...
2.3 References
References
•Video Processing Front End (VPFE)– CCD Controller (CCDC)– Image Pipe (IPIPE)– H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure)– Multiply Mask / Lens Distortion Module (CFALD)•Video Processing Back End (VPBE)– On Screen Display (OSD)– Video Encoder Engine (VENC)
Figure 2-1 shows the functional block diagram of the DM355 ARM Subsystem.
Figure 2-1. DM355 ARM Subsystem Block Diagram
See the following related documents for more information:•DM355 Data Manual (SPRS348 ): Provides a high-level overview of the DM355 system.•DM355 Peripheral Reference Guides: For various peripherals on the DM355•For more detailed information about the ARM processor core, see ARM Ltd.’s web site:–http://www.arm.com/documentation/ARMProcessor_Cores/index.html
•Particularly, see the ARM926EJ-S Technical Reference Manual
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3.1 Introduction
SPRUFB3 – September 2007
ARM Core
This chapter describes the ARM core and its associated memories. The ARM core consists of thefollowing components:
•ARM926EJ-S - 32-bit RISC processor•16-KB Instruction cache•8-KB Data cache•MMU
•CP15 to control MMU, cache, write buffer, etc.•Java accelerator
•ARM Internal Memory– 32-KB built-in RAM– 8-KB built-in ROM (boot ROM)•Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)•Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer– Support for 32/16-bit instruction sets– Fixed little endian memory format– Enhanced DSP instructions– For maximum operating clock frequency see the DM355 Data Manual (SPRS348 )
The ARM926EJ-S processor is a member of the ARM9 family of general-purpose microprocessors. TheARM926EJ-S processor targets multi-tasking applications where full memory management, highperformance, low die size, and low power are all important.
The ARM926EJ-S processor supports the 32-bit ARM and the 16-bit THUMB instruction sets, enablingyou to trade off between high performance and high code density. This includes features for efficientexecution of Java byte codes and providing Java performance similar to Just in Time (JIT) Java interpreterwithout associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in bothhardware and software debugging. The ARM926EJ-S processor has a Harvard architecture and providesa complete high performance subsystem, including the following:•An ARM926EJ-S integer core•A Memory Management Unit (MMU)•Separate instruction and data AMBA AHB bus interfaces•Separate instruction and data TCM interfaces
The ARM926EJ-S processor implements ARM architecture version 5TEJ.
The ARM926EJ-S core includes new signal processing extensions to enhance 16-bit fixed-pointperformance using a single-cycle 32 x 16 multiply-accumulate (MAC) unit. The ARM Subsystem also has16 KB of internal RAM and 8 KB of internal ROM, accessible via the I-TCM and D-TCM interfaces throughan arbiter. The same arbiter provides a slave DMA interface to the rest of the DM355 DMSoC.Furthermore, the ARM has DMA and CFG bus master ports via the AHB interface.
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