Texas Instruments CC2538 User manual

Public Version
CC2538 System-on-Chip Solution for 2.4-GHz
IEEE 802.15.4 and ZigBee®/ZigBee IP®
Applications
Texas Instruments CC2538™ Family of Products
Version B
User's Guide
Literature Number: SWRU319B
April 2012–Revised April 2013

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Public Version
Contents
Preface ...................................................................................................................................... 26
1 Architectural Overview ....................................................................................................... 32
1.1 Target Applications ........................................................................................................ 33
1.2 Overview .................................................................................................................... 33
1.3 Functional Overview ...................................................................................................... 36
1.3.1 ARM Cortex-M3 ................................................................................................... 36
1.3.1.1 Processor Core ............................................................................................. 36
1.3.1.2 Memory Map ................................................................................................ 36
1.3.1.3 System Timer (SysTick) ................................................................................... 36
1.3.1.4 Nested Vector Interrupt Controller ....................................................................... 37
1.3.1.5 System Control Block ...................................................................................... 37
1.3.1.6 MPU .......................................................................................................... 37
1.3.2 On-Chip Memory ................................................................................................. 37
1.3.2.1 SRAM ........................................................................................................ 37
1.3.2.2 Flash Memory ............................................................................................... 37
1.3.2.3 ROM ......................................................................................................... 38
1.3.3 Radio ............................................................................................................... 38
1.3.4 AES Engine with 128, 192 256 Bit Key Support ............................................................. 38
1.3.5 Programmable Timers ........................................................................................... 38
1.3.5.1 MAC Timer .................................................................................................. 39
1.3.5.2 Watchdog Timer ............................................................................................ 39
1.3.5.3 Sleep Timer ................................................................................................. 39
1.3.5.4 CCP Pins .................................................................................................... 39
1.3.6 Direct Memory Access ........................................................................................... 39
1.3.7 System Control and Clock ....................................................................................... 40
1.3.8 Serial Communications Peripherals ............................................................................ 41
1.3.8.1 USB .......................................................................................................... 41
1.3.8.2 UART ........................................................................................................ 41
1.3.8.3 I2C............................................................................................................ 42
1.3.8.4 SSI ........................................................................................................... 43
1.3.9 Programmable GPIOs ........................................................................................... 43
1.3.10 Analog ............................................................................................................ 43
1.3.10.1 ADC .......................................................................................................... 44
1.3.10.2 Analog Comparator ........................................................................................ 44
1.3.10.3 Random Number Generator .............................................................................. 44
1.3.11 cJTAG, JTAG and SWO ........................................................................................ 44
1.3.12 Packaging and Temperature ................................................................................... 44
2 The Cortex-M3 Processor ................................................................................................... 45
2.1 The Cortex-M3 Processor Introduction ................................................................................. 46
2.2 Block Diagram ............................................................................................................. 46
2.3 Overview .................................................................................................................... 47
2.3.1 System-Level Interface .......................................................................................... 47
2.3.2 Integrated Configurable Debug ................................................................................. 47
2.3.3 Trace Port Interface Unit ........................................................................................ 48
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2.3.4 Cortex-M3 System Component Details ........................................................................ 48
2.4 Programming Model ....................................................................................................... 48
2.4.1 Processor Mode and Privilege Levels for Software Execution ............................................. 49
2.4.2 Stacks .............................................................................................................. 49
2.4.3 Register Map ...................................................................................................... 49
2.4.4 Register Descriptions ............................................................................................ 51
2.4.5 Exceptions and Interrupts ....................................................................................... 61
2.4.6 Data Types ........................................................................................................ 61
2.5 Instruction Set Summary ................................................................................................. 61
3 Cortex™-M3 Peripherals ..................................................................................................... 65
3.1 Cortex™-M3 Peripherals Introduction .................................................................................. 66
3.2 Functional Description .................................................................................................... 66
3.2.1 SysTick ............................................................................................................. 66
3.2.2 NVIC ................................................................................................................ 67
3.2.2.1 Level-Sensitive and Pulse Interrupts .................................................................... 67
3.2.2.2 Hardware and Software Control of Interrupts .......................................................... 67
3.2.3 SCB ................................................................................................................ 68
3.2.4 MPU ................................................................................................................ 68
3.2.4.1 Updating an MPU Region ................................................................................. 69
3.2.4.1.1 Updating an MPU Region Using Separate Words ................................................ 69
3.2.4.1.2 Updating an MPU Region Using Multiple-Word Writes ........................................... 70
3.2.4.1.3 Subregions .............................................................................................. 70
3.2.4.2 MPU Access Permission Attributes ...................................................................... 71
3.2.4.2.1 MPU Configuration for a CC2538 Microcontroller ................................................. 72
3.2.4.3 MPU Mismatch ............................................................................................. 72
3.3 Register Map ............................................................................................................... 72
3.4 SysTick Register Descriptions ........................................................................................... 75
3.5 NVIC Register Descriptions .............................................................................................. 77
3.5.1 System Control Block (SCB) Register Descriptions ........................................................ 127
3.5.2 MPU Register Descriptions .................................................................................... 144
4 Memory Map ................................................................................................................... 157
4.1 Memory Model ............................................................................................................ 158
4.1.1 Memory Regions, Types, and Attributes ..................................................................... 159
4.1.2 Memory System Ordering of Memory Accesses ............................................................ 160
4.1.3 Behavior of Memory Accesses ................................................................................ 160
4.1.4 Software Ordering of Memory Accesses ..................................................................... 160
4.1.5 Bit-Banding ....................................................................................................... 161
4.1.5.1 Directly Accessing an Alias Region .................................................................... 163
4.1.5.2 Directly Accessing a Bit-Band Region ................................................................. 163
4.1.6 Data Storage ..................................................................................................... 163
4.1.7 Synchronization Primitives ..................................................................................... 164
5 Interrupts ........................................................................................................................ 166
5.1 Exception Model ......................................................................................................... 167
5.1.1 Exception States ................................................................................................ 167
5.1.2 Exception Types ................................................................................................ 167
5.1.3 Exception Handlers ............................................................................................. 172
5.1.4 Vector Table ..................................................................................................... 172
5.1.5 Exception Priorities ............................................................................................. 173
5.1.6 Interrupt Priority Grouping ..................................................................................... 174
5.1.7 Exception Entry and Return ................................................................................... 174
5.1.7.1 Exception Entry ........................................................................................... 174
5.1.7.2 Exception Return ......................................................................................... 175
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5.2 Fault Handling ............................................................................................................ 176
5.2.1 Fault Types ...................................................................................................... 176
5.2.2 Fault Escalation and Hard Faults ............................................................................. 177
5.2.3 Fault Status Registers and Fault Address Registers ....................................................... 177
5.2.4 Lockup ............................................................................................................ 178
5.2.5 PKA Interrupt .................................................................................................... 178
6 JTAG Interface ................................................................................................................ 179
6.1 Debug Port ................................................................................................................ 180
6.2 IEEE 1149.7 .............................................................................................................. 180
6.3 Switching Debug Interface from 2-pin cJTAG to 4-pin JTAG ...................................................... 181
6.4 Debugger Connection ................................................................................................... 183
6.4.1 ICEPick Module ................................................................................................. 183
6.4.1.1 Default Boot Mode ........................................................................................ 183
6.4.1.2 CM3 DAP Access ......................................................................................... 183
6.5 Primary Debug Support ................................................................................................. 184
6.5.1 Processor Native Debug Support ............................................................................. 184
6.5.1.1 Cortex™-M3 MPU ........................................................................................ 184
6.5.2 Suspend .......................................................................................................... 184
6.6 Debug Access Security Through ICEPick ............................................................................ 184
6.6.1 Unlocking the Debug Interface ................................................................................ 184
6.7 CM3 Debug Interrupt .................................................................................................... 185
7 System Control ................................................................................................................ 186
7.1 Power Management ..................................................................................................... 187
7.1.1 Control Inputs to Power Management ........................................................................ 187
7.1.1.1 Clock Gating Registers .................................................................................. 187
7.1.1.2 Deep Sleep Selector (SYSCTRL Register) ........................................................... 187
7.1.1.3 Power Mode Configuration Register (PMCTL Register) ............................................. 187
7.1.1.4 WFI - Operational Mode Initiator (Wait For Interrupt) ................................................ 187
7.1.2 Using Power Management ..................................................................................... 188
7.1.2.1 Sequencing when using Power Modes ................................................................ 189
7.1.2.2 Time Considerations for Active, Sleep and PM0 ..................................................... 190
7.1.2.3 Time Considerations for PM1, PM2 and PM3 ........................................................ 190
7.1.2.3.1 Enter Power Mode when Running on 16 MHz System Clock .................................. 191
7.1.2.3.2 Enter Power Mode when Running on 32 MHz System Clock .................................. 191
7.1.2.4 Exit from Power Modes .................................................................................. 193
7.1.2.4.1 32 MHz XOSC Startup Time ........................................................................ 193
7.1.2.4.2 32 MHz Qualification Time .......................................................................... 193
7.1.3 Power Consumption ............................................................................................ 193
7.2 Oscillators and Clocks ................................................................................................... 195
7.2.1 High Frequency Oscillators .................................................................................... 195
7.2.1.1 16 MHz RCOSC Calibration ............................................................................. 196
7.2.2 Low Frequency Oscillators ..................................................................................... 196
7.2.2.1 32 kHz RCOSC Calibration ............................................................................. 196
7.3 System Clock Gating .................................................................................................... 196
7.3.1 Clocks for UART and SSI ...................................................................................... 197
7.3.2 Clocks for GPT, I2C, and SEC ................................................................................. 197
7.4 Reset ...................................................................................................................... 197
7.4.1 Reset of Peripherals ............................................................................................ 198
7.4.2 Power-On Reset and Brownout Detector .................................................................... 198
7.4.3 Clock Loss Detector ............................................................................................ 198
7.5 Emulator in Power Modes .............................................................................................. 199
7.6 Chip State Retention .................................................................................................... 199
7.6.1 CRC Check on State Retention ............................................................................... 199
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7.7 System Control Registers ............................................................................................... 199
7.7.1 SYS_CTRL Registers .......................................................................................... 199
7.7.1.1 SYS_CTRL Registers Mapping Summary ............................................................. 199
7.7.1.2 SYS_CTRL Register Descriptions ...................................................................... 201
8 Internal Memory ............................................................................................................... 217
8.1 Introduction ............................................................................................................... 218
8.2 Flash Memory Organization ............................................................................................ 218
8.2.1 Information Page ................................................................................................ 218
8.2.2 Lock Bit Page .................................................................................................... 218
8.3 Flash Write ................................................................................................................ 218
8.3.1 Flash Write Procedure .......................................................................................... 218
8.3.2 Writing Multiple Times to a Word ............................................................................. 219
8.3.3 DMA Flash Write ................................................................................................ 220
8.3.4 CPU Flash Write ................................................................................................ 221
8.4 Flash DMA Trigger ....................................................................................................... 222
8.5 Flash Page Erase ........................................................................................................ 222
8.5.1 Performing Flash Erase from Flash Memory ................................................................ 222
8.6 Flash Lock Bit Page and Customer Configuration Area (CCA) .................................................... 222
8.6.1 Flash Image Valid Bits in Lock Bit Page ..................................................................... 224
8.6.2 ROM Boot Loader Backdoor Configuration in Lock Bit Page ............................................. 224
8.7 Flash Mass Erase ........................................................................................................ 225
8.7.1 Flash Mass Erase Procedure .................................................................................. 226
8.8 ROM Sub System ........................................................................................................ 227
8.9 SRAM ...................................................................................................................... 227
8.9.1 Flash Control Registers ........................................................................................ 228
8.9.1.1 FLASH_CTRL Registers ................................................................................. 228
8.9.1.1.1 FLASH_CTRL Registers Mapping Summary ..................................................... 228
8.9.1.1.2 FLASH_CTRL Register Descriptions .............................................................. 228
9 General-Purpose Inputs/Outputs ....................................................................................... 234
9.1 I/O Control ................................................................................................................ 235
9.1.1 I/O Muxing ....................................................................................................... 235
9.2 GPIO ....................................................................................................................... 236
9.2.1 General-Purpose Inputs/Outputs .............................................................................. 236
9.2.2 Functional Description .......................................................................................... 236
9.2.2.1 Data Control ............................................................................................... 237
9.2.2.1.1 Data Direction Operation ............................................................................ 238
9.2.2.1.2 Data Register Operation ............................................................................ 238
9.2.2.2 Interrupt Control ........................................................................................... 238
9.2.2.2.1 Power-Up Interrupt ................................................................................... 239
9.2.2.3 Mode Control .............................................................................................. 239
9.2.2.4 Commit Control ........................................................................................... 239
9.2.2.5 Pad Control ................................................................................................ 240
9.2.3 Configuration .................................................................................................... 241
9.2.4 Radio Test Output Signals ..................................................................................... 241
9.2.5 Power-Down Signal MUX (PMUX) ............................................................................ 241
9.3 I/O Control and GPIO Registers ....................................................................................... 241
9.3.1 GPIO Registers .................................................................................................. 241
9.3.1.1 GPIO Registers Mapping Summary .................................................................... 241
9.3.1.1.1 GPIO Common Registers Mapping ................................................................ 241
9.3.1.1.2 GPIO Instances Register Mapping Summary .................................................... 242
9.3.1.2 GPIO Common Register Descriptions ................................................................. 245
9.3.2 IOC Registers ................................................................................................... 259
9.3.2.1 IOC Registers Mapping Summary ...................................................................... 259
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9.3.2.2 IOC Register Descriptions ............................................................................... 262
10 Micro Direct Memory Access ............................................................................................. 290
10.1 μDMA Introduction ....................................................................................................... 291
10.2 Block Diagram ............................................................................................................ 291
10.3 Functional Description ................................................................................................... 292
10.3.1 Channel Assignments ......................................................................................... 292
10.3.2 Priority ........................................................................................................... 294
10.3.3 Arbitration Size ................................................................................................. 294
10.3.4 Request Types ................................................................................................. 294
10.3.4.1 Single Request ............................................................................................ 295
10.3.4.2 Burst Request ............................................................................................. 295
10.3.5 Channel Configuration ........................................................................................ 295
10.3.6 Transfer Modes ................................................................................................ 296
10.3.6.1 Stop Mode ................................................................................................. 296
10.3.6.2 Basic Mode ................................................................................................ 297
10.3.6.3 Auto Mode ................................................................................................. 297
10.3.6.4 Ping-Pong .................................................................................................. 297
10.3.6.5 Memory Scatter-Gather .................................................................................. 298
10.3.6.6 Peripheral Scatter-Gather ............................................................................... 302
10.3.7 Transfer Size and Increment ................................................................................. 305
10.3.8 Peripheral Interface ............................................................................................ 305
10.3.9 Software Request .............................................................................................. 305
10.3.10 Interrupts and Errors ......................................................................................... 306
10.4 Initialization and Configuration ......................................................................................... 306
10.4.1 Module Initialization ............................................................................................ 306
10.4.2 Configuring a Memory-to-Memory Transfer ................................................................ 306
10.4.2.1 Configure the Channel Attributes ....................................................................... 306
10.4.2.2 Configure the Channel Control Structure .............................................................. 307
10.4.2.2.1 Configure the Source and Destination ............................................................ 307
10.4.2.3 Start the Transfer ......................................................................................... 307
10.4.3 Configuring a Peripheral for Simple Transmit .............................................................. 308
10.4.3.1 Configure the Channel Attributes ....................................................................... 308
10.4.3.2 Configure the Channel Control Structure .............................................................. 308
10.4.3.2.1 Configure the Source and Destination ............................................................ 308
10.4.3.3 Start the Transfer ......................................................................................... 309
10.4.4 Configuring a Peripheral for Ping-Pong Receive .......................................................... 309
10.4.4.1 Configure the Channel Attributes ....................................................................... 309
10.4.4.2 Configure the Channel Control Structure .............................................................. 309
10.4.4.2.1 Configure the Source and Destination ............................................................ 310
10.4.4.3 Configure the Peripheral Interrupt ...................................................................... 310
10.4.4.4 Enable the μDMA Channel .............................................................................. 311
10.4.4.5 Process Interrupts ........................................................................................ 311
10.4.5 Configuring Channel Assignments .......................................................................... 311
10.5 µDMA Registers .......................................................................................................... 311
10.5.1 UDMA Registers ............................................................................................... 311
10.5.1.1 UDMA Registers Mapping Summary ................................................................... 311
10.5.1.2 UDMA Register Descriptions ............................................................................ 312
11 General-Purpose Timers ................................................................................................... 324
11.1 General-Purpose Timers ................................................................................................ 325
11.2 Block Diagram ............................................................................................................ 325
11.3 Functional Description ................................................................................................... 326
11.3.1 GPTM Reset Conditions ...................................................................................... 326
11.3.2 Timer Modes .................................................................................................... 327
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11.3.2.1 One-Shot or Periodic Timer Mode ...................................................................... 327
11.3.2.2 Input Edge-Count Mode ................................................................................. 328
11.3.2.2.1 Input Edge-Time Mode .............................................................................. 329
11.3.2.2.2 PWM Mode ........................................................................................... 330
11.3.2.2.3 Wait-for-Trigger Mode ............................................................................... 333
11.3.2.2.4 Synchronizing GP Timer Blocks ................................................................... 334
11.3.2.2.5 Accessing Concatenated 16- and 32-Bit GPTM Register Values ............................. 334
11.3.2.3 Initialization and Configuration .......................................................................... 335
11.3.2.3.1 One-Shot and Periodic Timer Modes ............................................................. 335
11.3.2.3.2 Input Edge-Count Mode ............................................................................. 335
11.3.2.3.3 Input Edge_Timing Mode ........................................................................... 336
11.3.2.3.4 PWM Mode ........................................................................................... 336
11.4 General-Purpose Timer Registers ..................................................................................... 337
11.4.1 GPTIMER Registers ........................................................................................... 337
11.4.1.1 GPTIMER Registers Mapping Summary .............................................................. 337
11.4.1.1.1 GPTIMER Common Registers Mapping .......................................................... 337
11.4.1.1.2 GPTIMER Instances Register Mapping Summary .............................................. 337
11.4.1.2 GPTIMER Common Register Descriptions ............................................................ 341
12 MAC Timer ...................................................................................................................... 356
12.1 Timer Operation .......................................................................................................... 357
12.1.1 General .......................................................................................................... 357
12.1.2 Up Counter ...................................................................................................... 357
12.1.3 Timer Overflow ................................................................................................. 357
12.1.4 Timer Delta Increment ......................................................................................... 357
12.1.5 Timer Compare ................................................................................................. 357
12.1.6 Overflow Count ................................................................................................. 358
12.1.7 Overflow-Count Update ....................................................................................... 358
12.1.8 Overflow-Count Overflow ..................................................................................... 358
12.1.9 Overflow-Count Compare ..................................................................................... 358
12.1.10 Capture Input ................................................................................................. 358
12.2 Interrupts .................................................................................................................. 358
12.3 Event Outputs (DMA Trigger and Radio Events) .................................................................... 359
12.4 Timer Start and Stop Synchronization ................................................................................ 359
12.4.1 General .......................................................................................................... 359
12.4.2 Timer Synchronous Stop ...................................................................................... 359
12.4.3 Timer Synchronous Start ..................................................................................... 360
12.5 MAC Timer Registers .................................................................................................... 361
12.5.1 RFCORE_SFR Registers ..................................................................................... 361
12.5.1.1 RFCORE_SFR Registers Mapping Summary ........................................................ 361
12.5.1.1.1 RFCORE_SFR Register Summary ................................................................ 361
12.5.1.2 RFCORE_SFR Register Descriptions ................................................................. 362
13 Sleep Timer ..................................................................................................................... 368
13.1 General .................................................................................................................... 369
13.2 Timer Compare ........................................................................................................... 369
13.3 Timer Capture ............................................................................................................ 369
13.4 Sleep Timer Registers ................................................................................................... 370
13.4.1 SMWDTHROSC Registers ................................................................................... 370
13.4.1.1 SMWDTHROSC Registers Mapping Summary ....................................................... 370
13.4.1.2 SMWDTHROSC Register Descriptions ................................................................ 371
14 Watchdog Timer .............................................................................................................. 376
14.1 Watchdog Timer .......................................................................................................... 377
14.2 Watchdog Timer Registers ............................................................................................. 377
14.2.1 SMWDTHROSC Registers ................................................................................... 377
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14.2.1.1 SMWDTHROSC Registers Mapping Summary ....................................................... 377
14.2.1.2 SMWDTHROSC Register Descriptions ................................................................ 377
15 ADC ............................................................................................................................... 379
15.1 ADC Introduction ......................................................................................................... 380
15.2 ADC Operation ........................................................................................................... 380
15.2.1 ADC Inputs ...................................................................................................... 380
15.2.2 ADC Conversion Sequences ................................................................................. 381
15.2.3 Single ADC Conversion ....................................................................................... 381
15.2.4 ADC Operating Modes ........................................................................................ 381
15.2.5 ADC Conversion Results ..................................................................................... 382
15.2.6 ADC Reference Voltage ...................................................................................... 382
15.2.7 ADC Conversion Timing ...................................................................................... 382
15.2.8 ADC Interrupts ................................................................................................. 382
15.2.9 ADC DMA Triggers ............................................................................................ 382
15.3 Analog-to-Digital Converter Registers ................................................................................. 383
15.3.1 SOC_ADC Registers .......................................................................................... 383
15.3.1.1 SOC_ADC Registers Mapping Summary ............................................................. 383
15.3.1.1.1 SOC_ADC Register Summary ..................................................................... 383
15.3.1.2 SOC_ADC Register Descriptions ....................................................................... 383
16 Random Number Generator .............................................................................................. 387
16.1 Introduction ............................................................................................................... 388
16.2 Random-Number-Generator Operation ............................................................................... 388
16.2.1 Pseudo-random Sequence Generation ..................................................................... 388
16.2.2 Seeding ......................................................................................................... 388
16.2.3 CRC16 ........................................................................................................... 389
16.3 Random Number Generator Registers ................................................................................ 389
16.3.1 SOC_ADC Registers .......................................................................................... 389
16.3.1.1 SOC_ADC Registers Mapping Summary ............................................................. 389
16.3.1.1.1 SOC_ADC Register Summary ..................................................................... 389
16.3.1.2 SOC_ADC Register Descriptions ....................................................................... 389
17 Analog Comparator .......................................................................................................... 391
17.1 Introduction ............................................................................................................... 392
17.2 Analog Comparator Registers .......................................................................................... 392
17.2.1 SOC_ADC Registers .......................................................................................... 392
17.2.1.1 SOC_ADC Registers Mapping Summary ............................................................. 392
17.2.1.1.1 SOC_ADC Register Summary ..................................................................... 393
17.2.1.2 SOC_ADC Register Descriptions ....................................................................... 393
18 Universal Asynchronous Receivers and Transmitters .......................................................... 394
18.1 Universal Asynchronous Receivers and Transmitters .............................................................. 395
18.2 Block Diagram ............................................................................................................ 395
18.3 Signal Description ........................................................................................................ 396
18.4 Functional Description ................................................................................................... 397
18.4.1 Transmit and Receive Logic .................................................................................. 397
18.4.2 Baud-Rate Generation ........................................................................................ 397
18.4.3 Data Transmission ............................................................................................. 398
18.4.4 Modem Handshake Support .................................................................................. 398
18.4.4.1 Signaling ................................................................................................... 398
18.4.4.2 Flow Control ............................................................................................... 398
18.4.4.2.1 Hardware Flow Control (RTS and CTS) .......................................................... 398
18.4.5 LIN Support ..................................................................................................... 399
18.4.5.1 LIN Master ................................................................................................. 399
18.4.5.2 LIN Slave .................................................................................................. 399
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18.4.6 9-Bit UART Mode .............................................................................................. 400
18.4.7 FIFO Operation ................................................................................................. 400
18.4.8 Interrupts ........................................................................................................ 401
18.4.9 Loopback Operation ........................................................................................... 401
18.5 Initialization and Configuration ......................................................................................... 401
18.6 UART Registers .......................................................................................................... 402
18.6.1 UART Registers ................................................................................................ 402
18.6.1.1 UART Registers Mapping Summary ................................................................... 402
18.6.1.1.1 UART Common Registers Mapping ............................................................... 402
18.6.1.1.2 UART Instances Register Mapping Summary ................................................... 403
18.6.1.2 UART Common Register Descriptions ................................................................. 404
19 Synchronous Serial Interface ............................................................................................ 422
19.1 Synchronous Serial Interface ........................................................................................... 423
19.2 Block Diagram ............................................................................................................ 423
19.3 Signal Description ........................................................................................................ 424
19.4 Functional Description ................................................................................................... 424
19.4.1 Bit Rate Generation ............................................................................................ 424
19.4.2 FIFO Operation ................................................................................................. 424
19.4.2.1 Transmit FIFO ............................................................................................. 424
19.4.2.2 Receive FIFO ............................................................................................. 425
19.4.3 Interrupts ........................................................................................................ 425
19.4.4 Frame Formats ................................................................................................. 425
19.4.4.1 Texas Instruments Synchronous Serial Frame Format .............................................. 426
19.4.4.2 Freescale SPI Frame Format ........................................................................... 426
19.4.4.2.1 SPO Clock Polarity Bit .............................................................................. 427
19.4.4.2.2 SPH Phase Control Bit .............................................................................. 427
19.4.4.3 Freescale SPI Frame Format With SPO = 0 and SPH = 0 ......................................... 427
19.4.4.4 Freescale SPI Frame Format With SPO = 0 and SPH = 1 ......................................... 428
19.4.4.5 Freescale SPI Frame Format With SPO = 1 and SPH = 0 ......................................... 428
19.4.4.6 Freescale SPI Frame Format With SPO = 1 and SPH = 1 ......................................... 429
19.4.4.7 MICROWIRE Frame Format ............................................................................ 430
19.5 DMA Operation ........................................................................................................... 431
19.6 Initialization and Configuration ......................................................................................... 431
19.7 SSI Registers ............................................................................................................. 433
19.7.1 SSI Registers ................................................................................................... 433
19.7.1.1 SSI Registers Mapping Summary ...................................................................... 433
19.7.1.1.1 SSI Common Registers Mapping .................................................................. 433
19.7.1.1.2 SSI Instances Register Mapping Summary ...................................................... 433
19.7.1.2 SSI Common Register Descriptions .................................................................... 434
20 Inter-Integrated Circuit Interface ........................................................................................ 441
20.1 Inter-Integrated Circuit Interface ....................................................................................... 442
20.2 Block Diagram ............................................................................................................ 442
20.3 Functional Description ................................................................................................... 442
20.3.1 I2C Bus Functional Overview ................................................................................. 443
20.3.1.1 Start and Stop Conditions ............................................................................... 443
20.3.1.2 Data Format With 7-Bit Address ........................................................................ 444
20.3.1.3 Data Validity ............................................................................................... 444
20.3.1.4 Acknowledge .............................................................................................. 444
20.3.1.5 Arbitration .................................................................................................. 445
20.3.2 Available Speed Modes ....................................................................................... 445
20.3.2.1 Standard and Fast Modes ............................................................................... 445
20.3.3 Interrupts ........................................................................................................ 445
20.3.3.1 I2C Master Interrupts ..................................................................................... 446
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20.3.3.2 I2C Slave Interrupts ....................................................................................... 446
20.3.4 Loopback Operation ........................................................................................... 446
20.3.5 Command Sequence Flow Charts ........................................................................... 446
20.3.5.1 I2C Master Command Sequences ...................................................................... 446
20.3.5.2 I2C Slave Command Sequences ........................................................................ 452
20.4 Initialization and Configuration ......................................................................................... 453
20.5 I2C Registers .............................................................................................................. 454
20.5.1 I2CM Registers ................................................................................................. 454
20.5.1.1 I2CM Registers Mapping Summary .................................................................... 454
20.5.1.2 I2CM Register Descriptions ............................................................................. 454
20.5.2 I2CS Registers ................................................................................................. 459
20.5.2.1 I2CS Registers Mapping Summary .................................................................... 459
20.5.2.2 I2CS Register Descriptions .............................................................................. 459
21 USB Controller ................................................................................................................ 464
21.1 USB Introduction ......................................................................................................... 465
21.2 USB Enable ............................................................................................................... 465
21.3 48-MHz USB PLL ........................................................................................................ 465
21.4 USB Interrupts ............................................................................................................ 466
21.5 USB Reset ................................................................................................................ 467
21.6 USB Index Register ...................................................................................................... 468
21.7 USB Suspend and Resume ............................................................................................ 468
21.8 Endpoint 0 ................................................................................................................ 468
21.8.1 Zero Data Requests ........................................................................................... 469
21.8.2 Write Requests ................................................................................................. 469
21.8.3 Read Requests ................................................................................................. 470
21.9 EndPoint 0 Interrupts .................................................................................................... 470
21.9.1 Error Conditions ................................................................................................ 474
21.9.2 SETUP Transactions (IDLE State) .......................................................................... 474
21.9.3 IN Transactions (TX State) ................................................................................... 476
21.9.4 OUT Transactions (RX State) ................................................................................ 479
21.10 Endpoints 1–5 ............................................................................................................ 482
21.10.1 FIFO Management ........................................................................................... 483
21.10.2 Double-Buffering .............................................................................................. 483
21.10.3 FIFO Access .................................................................................................. 484
21.10.4 Endpoint 1–5 Interrupts ...................................................................................... 484
21.10.5 Bulk and Interrupt IN Endpoint .............................................................................. 484
21.10.6 Isochronous IN Endpoint .................................................................................... 487
21.10.7 Bulk and Interrupt OUT Endpoint ........................................................................... 488
21.10.8 Isochronous OUT Endpoint ................................................................................. 490
21.11 DMA ....................................................................................................................... 492
21.12 Remote Wake-Up ........................................................................................................ 492
21.13 USB Registers Overview ............................................................................................... 493
21.14 USB Registers ........................................................................................................... 493
21.14.1 USB Registers ................................................................................................ 493
21.14.1.1 USB Registers Mapping Summary .................................................................... 493
21.14.1.2 USB Register Descriptions ............................................................................. 494
22 Security Core .................................................................................................................. 508
22.1 PKA Engine ............................................................................................................... 509
22.1.1 Terms and Conventions Used in this Manual .............................................................. 509
22.1.1.1 Acronyms .................................................................................................. 509
22.1.1.2 Formulae and Nomenclature ............................................................................ 509
22.1.2 Overview ........................................................................................................ 510
22.1.2.1 Feature List ................................................................................................ 510
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22.1.2.2 Performance ............................................................................................... 510
22.1.3 Functional Description ......................................................................................... 511
22.1.3.1 Module Architecture ...................................................................................... 511
22.1.3.2 PKA RAM .................................................................................................. 511
22.1.3.3 PKCP Operations ......................................................................................... 511
22.1.3.4 Sequencer Operations ................................................................................... 513
22.1.3.4.1 Modular Exponentiation Operations ............................................................... 513
22.1.3.4.2 PKA RAM Size Needed for Exponentiation Operations ........................................ 515
22.1.3.4.3 Modular Inversion Operation ....................................................................... 516
22.1.3.4.4 Modular Inversion With an Even Modulus ........................................................ 517
22.1.3.4.5 Modular Inversion With a Prime Modulus ......................................................... 518
22.1.3.4.6 ECC Operations ...................................................................................... 518
22.1.4 Performance .................................................................................................... 519
22.1.4.1 Basic PKCP Operations Performance ................................................................. 519
22.1.4.2 ExpMod Performance .................................................................................... 520
22.1.4.3 Modular Inversion Performance ........................................................................ 522
22.1.4.4 ECC Operation Performance ............................................................................ 522
22.1.5 Interfaces ........................................................................................................ 523
22.1.5.1 Functional Interface ...................................................................................... 523
22.1.5.1.1 External Interface Address Map .................................................................... 523
22.1.5.1.2 PKA Engine Control Registers ..................................................................... 523
22.1.5.1.3 PKA Vector_A Address (PKA_APTR) ............................................................. 523
22.1.5.1.4 PKA Vector_B Address (PKA_BPTR) ............................................................. 524
22.1.5.1.5 PKA Vector_C Address (PKA_CPTR) ............................................................ 524
22.1.5.1.6 PKA Vector_D Address (PKA_DPTR) ............................................................ 525
22.1.5.1.7 PKA Vector_A Length (PKA_ALENGTH) ......................................................... 525
22.1.5.1.8 PKA Vector_B Length (PKA_BLENGTH) ......................................................... 525
22.1.5.1.9 PKA Bit Shift Value (PKA_SHIFT) ................................................................. 526
22.1.5.1.10 PKA Function (PKA_FUNCTION) ................................................................ 526
22.1.5.1.11 PKA Compare Result (PKA_COMPARE) ....................................................... 527
22.1.5.1.12 PKA Most-Significant-Word of Result Vector (PKA_MSW) ................................... 528
22.1.5.1.13 PKA Most-Significant-Word of Divide Remainder (PKA_DIVMSW) ......................... 528
22.1.5.1.14 PKA Sequencer Control/Status Register (PKA_SEQ_CTRL) ................................ 529
22.1.5.1.15 PKA HW Options Register (PKA_OPTIONS) ................................................... 530
22.1.5.1.16 PKA Firmware Revision and Capabilities Register (PKA_SW_REV) ........................ 530
22.1.5.1.17 PKA HW Revision Register (PKA_REVISION) ................................................. 531
22.1.5.1.18 PKA Vector Ram (PKA_RAM) .................................................................... 532
22.1.5.1.19 Sequencer Program RAM (PKA_PROGRAM) .................................................. 532
22.1.5.2 Operation Sequences .................................................................................... 532
22.1.6 Appendix A: RSA, ELGAMAL, DH, AND DSA Use Cases ............................................... 534
22.1.6.1 A1: RSA Use Cases ...................................................................................... 534
22.1.6.2 A2: Diffie-Hellman Use Cases .......................................................................... 535
22.1.6.3 A3: ElGamal Use Cases ................................................................................. 535
22.1.6.4 A4: DSA Use Cases ...................................................................................... 536
22.2 AES and SHA Cryptoprocessor ........................................................................................ 537
22.2.1 Architecture Overview ......................................................................................... 537
22.2.1.1 Functional Description ................................................................................... 537
22.2.1.1.1 Basic DMA Controller With AHB Master Interface ............................................... 537
22.2.1.1.2 Key Store .............................................................................................. 537
22.2.1.1.3 AES Crypto Engine .................................................................................. 537
22.2.1.1.4 SHA-256 Hash Engine .............................................................................. 537
22.2.1.1.5 Master Control and Interrupts ...................................................................... 538
22.2.1.1.6 Debug Capabilities ................................................................................... 538
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22.2.1.1.7 Exception Handling .................................................................................. 538
22.2.2 Hardware Description ......................................................................................... 538
22.2.2.1 Slave Bus .................................................................................................. 538
22.2.2.1.1 Functional Description ............................................................................... 538
22.2.2.1.2 Endianness ........................................................................................... 538
22.2.2.1.3 Performance .......................................................................................... 538
22.2.2.2 Master Bus ................................................................................................ 539
22.2.2.3 Interrupts ................................................................................................... 539
22.2.3 Module Description ............................................................................................ 539
22.2.3.1 Introduction ................................................................................................ 539
22.2.3.2 Global and Detailed Memory Map ...................................................................... 539
22.2.3.3 DMA Controller ............................................................................................ 542
22.2.3.3.1 Operation .............................................................................................. 542
22.2.3.3.2 Channels and Arbiter ................................................................................ 544
22.2.3.3.3 Control/Status Registers ............................................................................ 546
22.2.3.4 Master Control and Select ............................................................................... 549
22.2.3.4.1 Algorithm Select ...................................................................................... 549
22.2.3.4.2 Master PROT Enable ................................................................................ 551
22.2.3.4.3 Software Reset ....................................................................................... 551
22.2.3.4.4 Interrupt ............................................................................................... 552
22.2.3.4.5 Version and Configuration Registers .............................................................. 555
22.2.3.5 AES Engine ................................................................................................ 557
22.2.3.5.1 Second Key / GHASH Key (internal, but clearable) ............................................. 557
22.2.3.5.2 AES Key Registers (internal) ....................................................................... 558
22.2.3.5.3 AES Initialization Vector Registers ................................................................ 559
22.2.3.5.4 ES Input/Output Buffer Control & Mode Register ................................................ 560
22.2.3.5.5 AES Crypto Length Registers ...................................................................... 563
22.2.3.5.6 Authentication Length Register .................................................................... 564
22.2.3.5.7 Data Input/Output Registers ........................................................................ 564
22.2.3.5.8 TAG Registers ........................................................................................ 566
22.2.3.6 HASH Core ................................................................................................ 567
22.2.3.6.1 Introduction ........................................................................................... 567
22.2.3.6.2 Data Input Registers ................................................................................. 567
22.2.3.6.3 Input/Output Buffer Control & Status Register ................................................... 568
22.2.3.6.4 Mode Registers ....................................................................................... 571
22.2.3.6.5 Length Registers ..................................................................................... 572
22.2.3.6.6 Hash Digest Registers ............................................................................... 573
22.2.3.7 Key Store .................................................................................................. 573
22.2.3.7.1 Key Store Write Area Register ..................................................................... 573
22.2.3.7.2 Key Store Written Area Register ................................................................... 574
22.2.3.7.3 Key Store Size Register ............................................................................. 575
22.2.3.7.4 Key Store Read Area Register ..................................................................... 575
22.2.4 Performance .................................................................................................... 576
22.2.4.1 Introduction ................................................................................................ 576
22.2.4.2 Performance ............................................................................................... 577
22.2.5 Programming Guidelines ...................................................................................... 578
22.2.5.1 One Time Initialization After a Reset ................................................................... 578
22.2.5.2 DMAC and Master Control .............................................................................. 578
22.2.5.2.1 Regular use ........................................................................................... 578
22.2.5.2.2 Interrupting DMA Transfers ......................................................................... 579
22.2.5.2.3 Interrupts and HW/SW Synchronization .......................................................... 579
22.2.5.3 Hashing .................................................................................................... 579
22.2.5.3.1 Data Format and Byte Order ....................................................................... 580
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22.2.5.3.2 Basic Hash With Data From the DMA ............................................................. 580
22.2.5.3.3 HMAC .................................................................................................. 582
22.2.5.3.4 Alternative Basic Hash Where Data Originates From the Slave Interface ................... 584
22.2.5.4 Encryption/Decryption .................................................................................... 586
22.2.5.4.1 Data Format and Byte Order ....................................................................... 586
22.2.5.4.2 Key Store .............................................................................................. 586
22.2.5.4.3 Basic AES Modes .................................................................................... 587
22.2.5.4.4 AES-GCM ............................................................................................. 589
22.2.5.4.5 CBC-MAC ............................................................................................. 590
22.2.5.4.6 AES-CCM ............................................................................................. 591
22.2.5.5 Exceptions Handling ...................................................................................... 593
22.2.5.5.1 Soft Reset ............................................................................................. 593
22.2.5.5.2 External Port Errors .................................................................................. 593
22.2.5.5.3 Key Store Errors ..................................................................................... 593
22.2.6 Conventions and Compliances ............................................................................... 594
22.2.6.1 Conventions Used in This Manual ...................................................................... 594
22.2.6.1.1 Acronyms ............................................................................................. 594
22.2.6.1.2 Terminology ........................................................................................... 595
22.2.6.1.3 Formulae and Nomenclature ....................................................................... 595
22.2.6.1.4 Register Information ................................................................................. 596
22.2.6.2 Compliances ............................................................................................... 596
22.3 Public Key Processor .................................................................................................... 596
22.3.1 Advanced Interrupt Controller ................................................................................ 596
22.3.2 Registers ........................................................................................................ 596
22.3.2.1 Register Address Map ................................................................................... 596
22.3.2.2 Register Description ...................................................................................... 597
22.3.2.2.1 Engine Registers ..................................................................................... 597
22.3.3 Advanced Interrupt Controller (Optional) ................................................................... 598
22.3.3.1 Introduction ................................................................................................ 598
22.3.3.2 Functional Description ................................................................................... 598
22.3.3.3 Interrupt Sources ......................................................................................... 599
22.3.3.4 AIC Registers ............................................................................................. 600
22.3.3.4.1 AIC Polarity Control Register (AIC_POL_CTRL) ................................................ 600
22.3.3.4.2 AIC Type Control Register (AIC_TYPE_CTRL) .................................................. 600
22.3.3.4.3 4.4.3 AIC Enable Control Register (AIC_ENABLE_CTRL) ..................................... 601
22.3.3.4.4 AIC Raw Source Status Register (AIC_RAW_STAT) ........................................... 601
22.3.3.4.5 AIC Enabled Status Register (AIC_ENABLED_STAT) ......................................... 602
22.3.3.4.6 AIC Acknowledge Register (AIC_ACK) ........................................................... 602
22.3.3.4.7 AIC Enable Set Register (AIC_ENABLE_SET) .................................................. 603
22.3.3.4.8 AIC Enable Clear Register (AIC_ENABLE_CLR) ................................................ 603
22.3.3.4.9 AIC Options Register (AIC_OPTIONS) ........................................................... 604
22.3.3.4.10 AIC Version Register (AIC_VERSION) .......................................................... 604
22.4 AES and PKA Registers ................................................................................................ 605
22.4.1 AES Registers .................................................................................................. 605
22.4.1.1 AES Registers Mapping Summary ..................................................................... 605
22.4.1.2 AES Register Descriptions .............................................................................. 608
22.4.2 PKA Registers .................................................................................................. 657
22.4.2.1 PKA Registers Mapping Summary ..................................................................... 657
22.4.2.2 PKA Register Descriptions .............................................................................. 658
23 Radio .............................................................................................................................. 668
23.1 RF Core ................................................................................................................... 669
23.1.1 Interrupts ........................................................................................................ 669
23.1.2 Interrupt Registers ............................................................................................. 669
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23.2 FIFO Access .............................................................................................................. 670
23.3 DMA ....................................................................................................................... 670
23.4 Memory Map .............................................................................................................. 670
23.4.1 RX FIFO ......................................................................................................... 670
23.4.2 TX FIFO ......................................................................................................... 670
23.4.3 Frame-Filtering and Source-Matching Memory Map ...................................................... 671
23.5 Frequency and Channel Programming ................................................................................ 672
23.6 IEEE 802.15.4-2006 Modulation Format .............................................................................. 673
23.7 IEEE 802.15.4-2006 Frame Format ................................................................................... 674
23.7.1 PHY Layer ...................................................................................................... 674
23.7.2 MAC Layer ...................................................................................................... 675
23.8 Transmit Mode ........................................................................................................... 675
23.8.1 TX Control ...................................................................................................... 675
23.8.2 TX State Timing ................................................................................................ 676
23.8.3 TX FIFO Access ............................................................................................... 676
23.8.4 Retransmission ................................................................................................. 676
23.8.5 Error Conditions ................................................................................................ 676
23.8.6 TX Flow Diagram .............................................................................................. 677
23.8.7 Frame Processing ............................................................................................. 679
23.8.8 Synchronization Header ....................................................................................... 679
23.8.9 Frame-Length Field ............................................................................................ 679
23.8.10 Frame-Check Sequence ..................................................................................... 679
23.8.11 Interrupts ...................................................................................................... 680
23.8.12 Clear-Channel Assessment ................................................................................. 680
23.8.13 Output Power Programming ................................................................................ 680
23.8.14 Tips and Tricks ............................................................................................... 680
23.9 Receive Mode ............................................................................................................ 680
23.9.1 RX Control ...................................................................................................... 680
23.9.2 RX State Timing ................................................................................................ 681
23.9.3 Frame Processing ............................................................................................. 681
23.9.4 Synchronization Header and Frame-Length Fields ....................................................... 681
23.9.5 Frame Filtering ................................................................................................. 682
23.9.5.1 Filtering Algorithm ........................................................................................ 682
23.9.5.2 Interrupts ................................................................................................... 683
23.9.5.3 Tips and Tricks ............................................................................................ 684
23.9.6 Source Address Matching .................................................................................... 685
23.9.6.1 Applications ................................................................................................ 685
23.9.6.2 The Source Address Table .............................................................................. 685
23.9.6.3 Address Enable Registers ............................................................................... 686
23.9.6.4 Matching Algorithm ....................................................................................... 686
23.9.6.5 Interrupts ................................................................................................... 687
23.9.6.6 Tips and Tricks ............................................................................................ 687
23.9.7 Frame-Check Sequence ...................................................................................... 688
23.9.8 Acknowledgement Transmission ............................................................................ 688
23.9.8.1 Transmission Timing ..................................................................................... 689
23.9.8.2 Manual Control ............................................................................................ 689
23.9.8.3 Automatic Control (AUTOACK) ......................................................................... 689
23.9.8.4 Automatic Setting of the Frame Pending Field (AUTOPEND) ...................................... 690
23.10 RX FIFO Access ......................................................................................................... 690
23.10.1 Using the FIFO and FIFOP Signals ........................................................................ 690
23.10.2 Error Conditions .............................................................................................. 691
23.10.3 RSSI ............................................................................................................ 691
23.10.4 Link Quality Indication ....................................................................................... 692
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23.11 Radio Control State-Machine .......................................................................................... 692
23.12 Random Number Generation .......................................................................................... 694
23.13 Packet Sniffing and Radio Test Output Signals ..................................................................... 695
23.14 Command Strobe/CSMA-CA Processor .............................................................................. 696
23.14.1 Instruction Memory ........................................................................................... 696
23.14.2 Data Registers ................................................................................................ 696
23.14.3 Program Execution ........................................................................................... 697
23.14.4 Interrupt Requests ............................................................................................ 697
23.14.5 Random Number Instruction ................................................................................ 697
23.14.6 Running CSP Programs ..................................................................................... 697
23.14.7 CSP Registers ................................................................................................ 698
23.14.8 Instruction Set Summary .................................................................................... 699
23.14.9 Instruction Set Definition ..................................................................................... 700
23.14.9.1 DECZ ...................................................................................................... 700
23.14.9.2 DECY ..................................................................................................... 701
23.14.9.3 DECX ..................................................................................................... 701
23.14.9.4 INCZ ....................................................................................................... 701
23.14.9.5 INCY ...................................................................................................... 701
23.14.9.6 INCX ...................................................................................................... 701
23.14.9.7 INCMAXY ................................................................................................. 702
23.14.9.8 RANDXY .................................................................................................. 702
23.14.9.9 INT ......................................................................................................... 702
23.14.9.10 WAITX ................................................................................................... 702
23.14.9.11 SETCMP1 ............................................................................................... 703
23.14.9.12 WAIT W ................................................................................................. 703
23.14.9.13 WEVENT1 .............................................................................................. 703
23.14.9.14 WEVENT2 .............................................................................................. 704
23.14.9.15 LABEL ................................................................................................... 704
23.14.9.16 RPT C ................................................................................................... 704
23.14.9.17 SKIP S, C ............................................................................................... 705
23.14.9.18 STOP .................................................................................................... 705
23.14.9.19 SNOP .................................................................................................... 706
23.14.9.20 SRXON .................................................................................................. 706
23.14.9.21 STXON .................................................................................................. 706
23.14.9.22 STXONCCA ............................................................................................ 706
23.14.9.23 SSAMPLECCA ......................................................................................... 707
23.14.9.24 SRFOFF ................................................................................................. 707
23.14.9.25 SFLUSHRX ............................................................................................. 707
23.14.9.26 SFLUSHTX ............................................................................................. 707
23.14.9.27 SACK .................................................................................................... 707
23.14.9.28 SACKPEND ............................................................................................. 708
23.14.9.29 SNACK .................................................................................................. 708
23.14.9.30 SRXMASKBITSET ..................................................................................... 708
23.14.9.31 SRXMASKBITCLR ..................................................................................... 708
23.14.9.32 ISSTOP .................................................................................................. 709
23.14.9.33 ISSTART ................................................................................................ 709
23.14.9.34 ISRXON ................................................................................................. 709
23.14.9.35 ISRXMASKBITSET .................................................................................... 709
23.14.9.36 ISRXMASKBITCLR .................................................................................... 710
23.14.9.37 ISTXON ................................................................................................. 710
23.14.9.38 ISTXONCCA ............................................................................................ 710
23.14.9.39 ISSAMPLECCA ........................................................................................ 710
23.14.9.40 ISRFOFF ................................................................................................ 711
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23.14.9.41 ISFLUSHRX ............................................................................................ 711
23.14.9.42 ISFLUSHTX ............................................................................................. 711
23.14.9.43 ISACK ................................................................................................... 711
23.14.9.44 ISACKPEND ............................................................................................ 711
23.14.9.45 ISNACK ................................................................................................. 712
23.14.9.46 ISCLEAR ................................................................................................ 712
23.15 Register Settings Update ............................................................................................... 712
23.16 Radio Registers .......................................................................................................... 713
23.16.1 RFCORE_FFSM Registers ................................................................................. 713
23.16.1.1 RFCORE_FFSM Registers Mapping Summary ..................................................... 713
23.16.1.2 RFCORE_FFSM Register Descriptions .............................................................. 714
23.16.2 RFCORE_XREG Registers ................................................................................. 721
23.16.2.1 RFCORE_XREG Registers Mapping Summary ..................................................... 721
23.16.2.2 RFCORE_XREG Register Descriptions .............................................................. 724
23.16.3 RFCORE_SFR Registers ................................................................................... 760
23.16.3.1 RFCORE_SFR Registers Mapping Summary ....................................................... 760
23.16.3.1.1 RFCORE_SFR Register Summary .............................................................. 761
23.16.3.2 RFCORE_SFR Register Descriptions ................................................................ 761
23.16.4 CCTEST Registers ........................................................................................... 764
23.16.4.1 CCTEST Registers Mapping Summary .............................................................. 764
23.16.4.2 CCTEST Register Descriptions ........................................................................ 764
23.16.5 ANA_REGS Registers ....................................................................................... 768
23.16.5.1 ANA_REGS Registers Mapping Summary ........................................................... 769
23.16.5.2 ANA_REGS Register Descriptions .................................................................... 769
24 Voltage Regulator ............................................................................................................ 770
A Available Software ........................................................................................................... 771
A.1 SmartRF™ Studio Software for Evaluation (www.ti.com/smartrfstudio) .......................................... 772
A.2 TIMAC Software (www.ti.com/timac) .................................................................................. 772
A.3 Z-Stack™ Software (www.ti.com/z-stack) ............................................................................ 772
B Abbreviations .................................................................................................................. 774
C Additional Information ...................................................................................................... 777
C.1 Texas Instruments Low-Power RF Web Site ......................................................................... 778
C.2 Low-Power RF Online Community ..................................................................................... 778
C.3 Texas Instruments Low-Power RF Developer Network ............................................................. 778
C.4 Low-Power RF eNewsletter ............................................................................................. 778
D References ...................................................................................................................... 779
E Revision History .............................................................................................................. 780
E.1 Revision History – External ............................................................................................. 780
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List of Figures
1-1. CC2538 Block Diagram................................................................................................... 34
2-1. CPU Block Diagram....................................................................................................... 47
2-2. TPIU Block Diagram ...................................................................................................... 48
2-3. Cortex-M3 Register Set................................................................................................... 50
3-1. SRD Use Example ........................................................................................................ 71
4-1. Bit-Band Mapping........................................................................................................ 163
4-2. Data Storage.............................................................................................................. 164
5-1. Vector Table .............................................................................................................. 173
5-2. Exception Stack Frame ................................................................................................. 175
6-1. Test/Debug System Top Level Diagram.............................................................................. 180
7-1. Flow Diagram for Operational Modes ................................................................................. 188
7-2. Simple Flow Diagram for Power Management....................................................................... 190
7-3. Timing Example for Transition from 32 MHz to PM's ............................................................... 192
7-4. Simplified Figure of Current Consumption in PM1 .................................................................. 194
7-5. Simplified Figure of Current Consumption in PM2 and PM3....................................................... 194
7-6. Block Diagram Oscillators and Clocks ................................................................................ 195
8-1. Flash Write Using DMA ................................................................................................. 221
9-1. Digital I/O Pads (The Diagram Shows One of 32 Possible I/O Pins) ............................................. 237
9-2. GPIODATA Write Example ............................................................................................. 238
9-3. GPIODATA Read Example............................................................................................. 238
9-4. PAD Configuration Override Registers................................................................................ 240
10-1. μDMA Block Diagram ................................................................................................... 292
10-2. Example of Ping-Pong μDMA Transaction ........................................................................... 298
10-3. Memory Scatter-Gather, Setup and Configuration .................................................................. 300
10-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................................... 301
10-5. Peripheral Scatter-Gather, Setup and Configuration................................................................ 303
10-6. Peripheral Scatter-Gather, μDMA Copy Sequence ................................................................. 304
11-1. GPTM Module Block Diagram.......................................................................................... 325
11-2. Input Edge-Count Mode Example, Counting Down ................................................................. 329
11-3. Input Edge-Time Mode Example....................................................................................... 330
11-4. 16-bit PWM Mode Example ............................................................................................ 332
11-5. CCP Output, GPTIMER_TnMATCHR > GPTIMER_TnILR ........................................................ 332
11-6. CCP Output, GPTIMER_TnMATCHR = GPTIMER_TnILR ........................................................ 333
11-7. CCP Output, GPTIMER_TnILR > GPTIMER_TnMATCHR ........................................................ 333
11-8. Timer Daisy-Chain....................................................................................................... 334
13-1. Sleep timer Capture ..................................................................................................... 370
15-1. ADC Block Diagram ..................................................................................................... 380
16-1. Basic Structure of the RNG............................................................................................. 388
17-1. Analog Comparator...................................................................................................... 392
18-1. UART Module Block Diagram.......................................................................................... 396
18-2. UART Character Frame................................................................................................. 397
18-3. LIN Message.............................................................................................................. 399
18-4. LIN Synchronization Field............................................................................................... 400
19-1. SSI Module Block Diagram............................................................................................. 423
19-2. TI Synchronous Serial Frame Format (Single Transfer)............................................................ 426
19-3. TI Synchronous Serial Frame Format (Continuous Transfer)...................................................... 426
19-4. Freescale SPI Format (Single Transfer) With SPO = 0 and SPH = 0 ............................................ 427
18 List of Figures SWRU319B–April 2012–Revised April 2013
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19-5. Freescale SPI Format (Continuous Transfer) With SPO = 0 and SPH = 0 ...................................... 427
19-6. Freescale SPI Frame Format With SPO = 0 and SPH = 1......................................................... 428
19-7. Freescale SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0.................................... 428
19-8. Freescale SPI Frame Format (Continuous Transfer) With SPO = 1 and SPH = 0.............................. 429
19-9. Freescale SPI Frame Format With SPO = 1 and SPH = 1......................................................... 429
19-10. MICROWIRE Frame Format (Single Frame)......................................................................... 430
19-11. MICROWIRE Frame Format (Continuous Transfer) ................................................................ 431
19-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ..................................... 431
20-1. I2C Block Diagram........................................................................................................ 442
20-2. I2C Bus Configuration.................................................................................................... 443
20-3. Start and Stop Conditions............................................................................................... 443
20-4. Complete Data Transfer With a 7-Bit Address....................................................................... 444
20-5. R/S Bit in First Byte...................................................................................................... 444
20-6. Data Validity During Bit Transfer on the I2C Bus..................................................................... 444
20-7. Master Single TRANSMIT .............................................................................................. 447
20-8. Master Single RECEIVE ................................................................................................ 448
20-9. Master TRANSMIT With Repeated Start Condition ................................................................. 449
20-10. Master RECEIVE With Repeated Start Condition ................................................................... 450
20-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition..................... 451
20-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition..................... 452
20-13. Slave Command Sequence ............................................................................................ 453
21-1. USB Controller Block Diagram......................................................................................... 465
21-2. USB Interrupt Service Routine ......................................................................................... 467
21-3. Endpoint 0 States........................................................................................................ 472
21-4. Endpoint 0 Service Routine............................................................................................. 473
21-5. SETUP Phase of Control Transfer..................................................................................... 475
21-6. SETUP Phase Control Transactions .................................................................................. 476
21-7. IN Data Phase for Control Transfer ................................................................................... 477
21-8. IN Phase Control Transactions......................................................................................... 478
21-9. Control Transactions Following Status Stage (TX Mode) .......................................................... 479
21-10. OUT Data Phase for Control Transfer ................................................................................ 480
21-11. OUT Phase Control Transactions...................................................................................... 481
21-12. Control Transactions Following Status Stage (RX Mode) .......................................................... 482
21-13. IN/OUT FIFOs............................................................................................................ 483
21-14. Bulk and Interrupt IN Transactions .................................................................................... 486
21-15. Isochronous IN Transactions........................................................................................... 488
21-16. Bulk and Interrupt OUT Transactions ................................................................................. 490
21-17. Isochronous OUT Transactions........................................................................................ 492
22-1. Operation Sequences and Main Interrupt ............................................................................ 533
22-2. DMA Controller and Its Integration .................................................................................... 542
22-3. Symmetric Crypto Processing Steps .................................................................................. 577
22-4. Implementation of Secure HMAC Operation ......................................................................... 583
22-5. AIC: Functional Logic of one Interrupt Source ....................................................................... 599
23-1. Modulation ................................................................................................................ 673
23-2. I and Q Phases When Transmitting a Zero-Symbol Chip Sequence, tC= 0.5 μs............................... 674
23-3. Schematic View of the IEEE 802.15.4 Frame Format .............................................................. 674
23-4. Format of the Frame Control Field (FCF)............................................................................. 675
23-5. Frame Data Written to the TX FIFO................................................................................... 676
23-6. TX Flow.................................................................................................................... 678
19
SWRU319B–April 2012–Revised April 2013 List of Figures
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23-7. Transmitted Synchronization Header.................................................................................. 679
23-8. FCS Hardware Implementation ........................................................................................ 680
23-9. SFD Signal Timing....................................................................................................... 682
23-10. Filtering Scenarios (Exceptions Generated During Reception).................................................... 684
23-11. Matching Algorithm for Short and Extended Addresses............................................................ 686
23-12. Interrupts Generated by Source Address Matching ................................................................. 687
23-13. Data in RX FIFO for Different Settings................................................................................ 688
23-14. Acknowledge Frame Format ........................................................................................... 688
23-15. Acknowledgement Timing............................................................................................... 689
23-16. Command Strobe Timing ............................................................................................... 689
23-17. Behavior of FIFO and FIFOP Signals ................................................................................. 691
23-18. Main FSM ................................................................................................................. 693
23-19. FFT of the Random Bytes .............................................................................................. 694
23-20. Histogram of 20 Million Bytes Generated With the RANDOM Instruction........................................ 695
23-21. Running a CSP Program................................................................................................ 698
20 List of Figures SWRU319B–April 2012–Revised April 2013
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