Toshiba TLP411E Installation guide

FIE NO. 336-9612
Dec., 1996
TECHNICAL TRAINING MANUAL
3 LCD DATA PROJECTOR
TLP411U
TLP411E

i
SECTION I
MAIN POWER SUPPLY
CIRCUIT................................. 1-1
1. OUTLINE .........................................1-2
1-1. Block Diagram ........................................... 1-2
2. DESCRIPTION ABOUT
CIRCUIT OPERATION..................1-2
2-1. Surge Absorber Circuit............................. 1-2
2-2. Noise Filter Circuit.................................... 1-3
2-3. Rush Current Protection Circuit ............. 1-3
2-4. Smoothing/Rectifying Circuit................... 1-3
2-5. Inverter Circuit (Flyback) ........................ 1-4
2-6. Primary Control Circuit ........................... 1-4
2-7. Secondary Rectification &
Smoothing Circuit ..................................... 1-5
2-8. +6V Detection Circuit ............................... 1-5
2-9. +6V, +S6V, +15.5V Overvoltage
Protection Circuit ...................................... 1-5
2-10. +6V, +S6V Over Current
Protection Circuit ................................... 1-6
2-11. Output ON/OFF Circuit........................ 1-6
2-12. ON/OFF Control Circuit ....................... 1-6
SECTION II
LAMP HIGH VOLTAGE
POWER SUPPLY
CIRCUIT................................. 2-1
1. LAMP HIGH VOLTAGE
POWER SUPPLY.............................2-2
SECTION III
OPTICAL SYSTEM .............. 3-1
1. CONFIGURATION .........................3-2
SECTION IV
RGB DRIVE CIRCUIT ......... 4-1
1. OUTLINE .........................................4-2
2. CIRCUIT DESCRIPTION..............4-2
2-1. Level Shifter (Q945 – Q953)..................... 4-2
2-2. Gamma (gg
gg
g) Circuit..................................... 4-3
CONTENTS
2-3. Level Shifter Circuit
(Q965 – Q968, R1044) ............................... 4-4
2-4. Black Limiter (Q969, Q970)..................... 4-4
2-5. Inverted Signal Amplifiers
(Q974 – Q981) ............................................ 4-4
2-6. Switch Circuit
(Q982 µPD74HC4066A)........................... 4-4
2-7. Sample & Hold Circuit ............................. 4-5
2-8. LCD Panel.................................................. 4-7
SECTION V
MICROCOMPUTER............. 5-1
1. SYSTEM OUTLINE ........................5-2
2. SYSTEM MICROCOMPUTER .....5-4
3. POWER SUPPLY RESET
PROCESS..........................................5-5
4. NON-VOLATILE MEMORY
PROCESS..........................................5-5
5. REMOTE CONTROL
RECEPTION PROCESS.................5-6
6. RS-232C TRANSMIT/
RECEIVE PROCESS ......................5-6
7. STATUS READ PROCESS .............5-7
8. STATUS DISPLAY PROCESS........5-7
9. ON-SCREEN DISPLAY
PROCESS..........................................5-8
10. VIDEO MODE FETCH
PROCESS.......................................5-8
11. VIDEO SYSTEM CONTROL
PROCESS.......................................5-9
12. PANEL SYSTEM CONTROL
PROCESS......................................5-10
13. VARIOUS DISPLAY
MODES .........................................5-11
14. APPLICABLE SIGNAL ..............5-12
15. RS-232C CONTROL
METHOD......................................5-13
16. RS-232C COMMAND LIST .......5-13

ii
SECTION VI
DIGITAL CIRCUIT............... 6-1
1. DIGITAL CIRCUIT
OPERATION ....................................6-2
1-1. Display Mode ............................................. 6-2
1-2. RGB Signal Input...................................... 6-3
1-3. NTSC Signal Input.................................... 6-4
1-4. PAL/SECAM Signal Input ....................... 6-4
2. CIRCUIT DESCRIPTION..............6-5
2-1. Clamp Circuit ............................................ 6-5
2-2. A/D Converter............................................ 6-5
2-3. Memory ...................................................... 6-7
2-4. PLD Circuit................................................ 6-9
2-5. D/A Converter.......................................... 6-11
2-6. Memory Control and
Sync Process IC ....................................... 6-13
2-7. PLL Circuit (1) ........................................ 6-14
2-8. PLL Circuit (2) ........................................ 6-15
2-9. Liquid Crystal Panel Timing
Generation Circuit .................................. 6-17
2-10. On-screen Character
Generation Circuit ............................... 6-23
SECTION VII
VIDEO SIGNAL PROCESS
CIRCUIT................................. 7-1
1. OUTLINE .........................................7-2
1-1. Circuit Configuration................................ 7-2
1-2. Video Signal Demodulation Block........... 7-2
1-3. RGB Signal Amplification
Circuit Block.............................................. 7-2
1-4. Audio Signal Amplification Block ........... 7-2
2. INPUT/OUTPUT SIGNAL
SWITCH CIRCUIT .........................7-3
2-1. Audio/Video Signal Switch Circuit.......... 7-3
2-2. Input Signals.............................................. 7-3
3. VIDEO DEMODULATION
BLOCK .............................................7-5
3-1. YC Separation Circuit .............................. 7-5
3-2. Video/Color Circuit ................................... 7-6
3-3. Luminance (Y) Signal Process Circuit .... 7-7
3-4. Color Signal Process Circuit .................... 7-8
3-5. Picture Sharpness Correction Circuit ..... 7-8
3-6. RGB Demodulation................................... 7-9
3-7. Audio Circuit ........................................... 7-11
4. RGB SIGNAL PROCESS
CIRCUIT.........................................7-11
4-1. RGB Signal SW Section ......................... 7-11
4-2. Video/RGB Signal SW Section .............. 7-12
4-3. RGB Signal Amplifier Section ............... 7-12
4-4. Microcomputer Interface........................ 7-13
SECTION VIII
CCD CAMERA CIRCUIT .... 8-1
1. OUTLINE .........................................8-2
1-1. CCD and Drive/Sync Signal
Generation Circuit (SG) ........................... 8-2
1-2. Pre-amp Circuit (CDS) ............................. 8-2
1-3. Video Signal Process Circuit
(PRO, ENC, AWB) .................................... 8-2
1-4. Power Supply Circuit................................ 8-2
SECTION IX
FLUORESCENT LAMP
INVERTER CIRCUIT........... 9-1
1. OPERATING DESCRIPTION .......9-2
2. TROUBLESHOOTING...................9-3
2-1. Fluorescent does not turn on.................... 9-3
3. CIRCUIT DIAGRAM......................9-4

1-1
SECTION I
MAIN POWER SUPPLY CIRCUIT

1-2
1. OUTLINE
The power supply circuit operates on AC as input and
outputs DC (+S6V, +6V, +10V, +12V, +15.5V) through
inverter after rectification and smoothing of theAC power.
ON/OFF function is provided for outputs other than +S6V
by the external signal. It is also capable of providing high
voltage output with inverter drive for halogen lamp. Fig.
1-1 shows the block diagram.
1-1. Block Diagram
Fig. 1-1 Block diagram
F001
F002
PC002
PC001
N
L
+S6V
+6V
+12V
+10V
+15.5V
ON/OFF
4TR
4TR
125V
ON/OFF
Inlet Switch
Surge
absorber
circuit
Noise
filter
circuit
Rush
current
protection
circuit
+6V output
detection
circuit
+6V,+S6V
excesscurrent
protection
+6V,+S6V,
+15.5V
over-voltage
protection
Output ON/OFF
circuit
Input
rectification
circuit
Rectification
switching
circuit
Inverter
circuit
flyback
Noise
filter
circuit
Transformer
T001
Primary
control
circuit
Secondary
rectification
smoothing
circuit
ON/OFF
control
circuit
Output ON/OFF
circuit
ON/OFF
control
circuit
High voltage output
315VDV
2. DESCRIPTION ABOUT CIRCUIT
OPERATION
2-1. SurgeAbsorber Circuit
The surge absorber circuit consists of protection element
(varistor) and spark gap on the pattern surface on the PC
board, making it possible to protect the power from being
destroyed by lighting stroke and impulse invaded from
external or from malfunction.

1-3
2-2. Noise Filter Circuit
The noise filter circuit only protects the noise generated
by the power source from leaking out to AC line and from
entering of the external noise inside the power. This circuit
is effective for both normal and common noise.
2-3. Rush Current Protection Circuit
When AC power is, via D001, rectified and directly ap-
plied to C011 and C012, rush current runs through C011
and C012 as shown in Fig. 1-3. The current degrades the
contact point of SW001. This rush current is controlled
by the circuit shown in Fig. 1-2, preventing the degrada-
tion of the contact point.
Before the power activation, there exists no induced volt-
age in T001. SCR001 is in the OFF state. Rectified AC
current runs through RF001 and charges C011 and C012.
Fig. 1-2
Fig. 1-3
With this, RF001 becomes charging resistance and is sup-
pressed less than 30A. Then, when the charging voltage
of C011 and C012 becomes more than the activation
voltage, the inverter starts oscillation (activation) and the
voltage is generated in the T001. This voltage is used for
trigger voltage for SCR001, turns on the SCR001 and short-
circuits the RF001. As a result, the rectified current flows
into C011 and C012, eliminating the power loss by RF001
in the normal operation state.
2-4. Smoothing/Rectifying Circuit
The input voltage of the unit is set to work in the range of
AC100 ~ 120V and AC220 ~ 240V. To keep the AC recti-
fication output voltage in almost the constant level, the
voltage doubler rectification is employed for the AC100
~ 120V input and the bridge rectification for the AC220 ~
240V input. An exclusive IC is used to switch the voltage
doubler rectification and the bridge rectification. Figs. 1-
4, 1-5 and 1-6 show the basic circuits.
When the switch is turned off, each of a positive and nega-
tive half-wave voltage of VIN (AC) is charged to C012 and
C011, and the bridge rectification voltage is developed
from the output terminal. On the other hand, when the
switch is turned on, a positive half-wave voltage of VIN
(AC) is charged to C012 through the circuit shown by
and a negative half-wave voltage ofVIN (AC) is charged to
C011 through the circuit shown by . The voltage
doubler of the half-wave rectification voltage is developed
from the output terminal.
Fig. 1-4 Bridge rectification (SW: OFF)
Fig. 1-5 Voltage doubler rectification (SW: ON)
I
T
Rush current
0
AC
AC
SCR001
~
~
+– C012
C011
T001
RF001
C012
C011
VIN(AC)
SWITCH
(IC001)
C012
C011
VIN(AC)
SWITCH
(IC001)

1-4
The half-wave rectification for VIN (AC) is carried out by
C and Di (D007) shown in the dotted line ----. When the
input voltage is low, the triac is turned on (voltage doubler
rectification) and when the input voltage high, the triac is
turned off (bridge rectification).
Fig. 1-6
2-5. Inverter Circuit (Flyback)
The current indicated with to the converter trans-
former is turned on/off by the FET switch of Q001
operation. In the OFF state, the current indicated with
flows.
Signal is supplied to gate from the primary control circuit.
With this, Q001 starts switching operation.
Gate voltage, drain voltage, and current waveform of Q001
are shown in Fig. 1-7.
Fig. 1-7
Rectification switching circuit
(IC001)
C012
C011
V
IN(AC)
Di
D007 C
Det. circuit
Latch circuit
Rectification
SW
2-6. Primary Control Circuit
The control system employs automatic flyback system by
timing capacitor.
In the circuit diagram in Fig. 1-8, when power is turned
on, input voltage VDC is applied to B point. Voltage is
applied to Q001 gate via R009 and R010. Then Q001 is
activated.When Q001 is turned on, the drain current begins
to flow as shown in Fig. 1-7 and input voltage is applied
to NPwinding.
Fig. 1-8
The voltage VNC = NC/NPxVDC is generated in the NC
winding and voltage is supplied to Q001 gate through R018
and C016. At the same time, C018 is charged through
ZD003 and R020.
When the electric potential of C018 rises up to VBE (Sat)
= approx. 0.7V, Q004 is turned on and Q001 is turned off.
That is, ON period of Q001 is determined by the time
constant of ZD003, R020 and C018. When Q001 becomes
off, the energy (flyback) accumulated in the transformer
T001 is output through D101. When this energy becomes
zero, D101 becomes off. For there exists a slight residual
energy in NSwinding, by means of which voltage is
generated in the gate winding NC, which turns on the Q001
again to resume switching operation.
On the other hand, when the voltage output through D001
is rectified by the secondary rectifying/smoothing circuit,
when the voltage is detected by +6V detection circuit,
PC002 becomes on. This shortens the time constant to
charge C018. At the same time, the ON period of Q001 is
controlled and the output voltage (+6V) becomes stable.
Q001
VGS
Q001
VDS
Q001
ID
0
0
0
T
T
T
V DC
Q001
T001
N
P
N S
VDC
Q001
T001
N
P
N S
N C
Point B
R009
R010
C016
Q004
PC002
R018
R020
ZD003
6VDC
D101
C018

1-5
2-7. Secondary Rectification & Smoothing
Circuit
High-voltage applied to NPbecomes, as mentioned previ-
ously, pulse by means of the switching operation and then
converted to low voltage at both ends of the secondary
side winding NSvia T001 and is output after rectifica-
tion/smoothing.
Fig. 1-9
2-8. +6V Detection Circuit
+6V voltage is divided by VR101, R113 and R114, it is
input to the gate of IC101 and then it is compared with
the reference voltage of that IC. This potential difference
flows into PC002 as current variation which is then
transferred to the primary side control circuit to control
output voltage.
Fig. 1-10
PC002 L101
K
AGIC101
R114
R113
VR101
+S6V
G
2-9. +6V, +S6V, +15.5V Overvoltage
Protection Circuit
As shown in Fig. 1-9, the overvoltage of +6V and +S6V
is detected by ZD101 and the overvoltage +15.5V is de-
tected by ZD401.
When the overvoltage is detected, current flows to zener
diode, the current then flows to PC001. This is transferred
to the primary control circuit and trigger signal is given
to the gate of thyristor SCR002 to short-circuit the gate of
Q001.As a result, Q001 turns off and the oscillation stops.
The circuit is put to the latch mode. Therefore, no activa-
tion is possible even overvoltage state is released. Activa-
tion is made possible by reentry of input.
Fig. 1-11
Q001
V
DS
A
I
B+6V
0
0
T001
N
P
N S
+6V
I
B
A
ZD101
D102 ZD401
+15.5V +S6V
+6V
R102
PC001
R103

1-6
2-10. +6V, +S6V Over Current Protection
Circuit
As shown in Fig. 1-12, this circuit detects the over current
by differential amplifier consisting of Q102 and Q103.
The reference voltage is produced by voltage division of
R105 and R106 using the +S6V as voltage source. This
voltage called VA (+S6V xR106/R105 + R106) is
compared withVoltageVB (Ioc xR108) generated by over
current. Q101 and Q102 turn on under the VA < VB
condition, by means of which the current is supplied to
PC001. This is transferred to the primary control circuit.
The rest of operation is the same as item 2-9.
Fig. 1-12
2-11. Output ON/OFF Circuit
+15.5V and +10V outputs can be turned on/off by 4-ter-
minal regulators IC401 and IC201. +5V and +6V outputs
can be turned on/off by POWER MOSS FET (Q106,
Q302). ON/OFF signal is given by the following ON/OFF
control circuit.
2-12. ON/OFF Control Circuit
This circuit controls the circuit of item 2-11, which de-
lays the external signal by the integration circuits (R118
and C108) to send signals to each output circuit. Signal
level is TTL level. Each output becomes off at “L” and
becomes on at “H” approximately 300 ms later.
The ON/OFF signal of +12V is input from pin 2 of CN104
and turns Q302 ON/OFF passing through Q301 and PC101.
To +15.5V
Q101
R105 R107
Q103
Q102
R106
R104
PC001 R108 G
VB
C103
+S6V, +6V line
+S6V, +6V current
VA

2-1
SECTION II
LAMP HIGH VOLTAGE
POWER SUPPLY CIRCUIT

2-2
1. LAMP HIGH VOLTAGE POWER
SUPPLY
The lamp high voltage power supply receives a DC220 to
390V (primary side) from the system power supply and
provides a DC voltage (50 to 70VDC at ever turning on the
lamp) to turn on the lamp. Fig. 2-1 shows the block dia-
gram.
The DC voltage is supplied to CN701 from the main power
supply unit through an interlock switch (S023). This volt-
age becomes AC input x2Ö2 (= 340V for AC120V input)
when the lamp is off. CN703 is a connector for the lamp on
control signal input and lamp off control signal output.
When +5V is applied to the ON/OFF input in the standby
on, Q702 FET transistor turns on, igniter develops a high
voltage pulse (13 to 18 kV), and the lamp starts to light up.
The pulse continues until the lamp turns on (for about 1 to
2s.). But if the lamp does not turn on, the OFF output is
developed. Q702 goes off after the lamp turned on, the ig-
niter circuit stops the operation, and the DC50 to 70V is
applied to the lamp.
CN701
(Pin 3)
220 - 390 VDC
STEPDOWN
TRANSFORM
CIRCUIT
FULL BRIDGE
INVERTER
CIRCUIT
IGNITER
CIRCUIT
AUXILIARY
POWER SUPPLY
CIRCUIT
CONTROL
CIRCUIT
MISLIGHT
DETECT
CIRCUIT
(PHOTO TRANSISTOR)
LAMP
CN703
1 ON/OFF input
2 GND
3 Lamp off output ( – )
4 Lamp off output ( + )
Fig. 2-1

3-1
SECTION III
OPTICAL SYSTEM

3-2
1. CONFIGURATION
No. Name Description
Lamp unit
17 Metal halide
lamp Light source of the optical system. DC system,250W, short arc length 3mm. To use light effectively in the tilt projection system, the light axis is arranged to face upward.
16 Elliptical
reflector Elliptical reflector converges light emitted from the metal halide-lamp, thereby creating light beams parallel with light axis and illuminating the beams to the liquid crystal panel.
15 Capacitor lens Converges the parallel light beams from the reflector in direction of focal point and effectively
transmits the beams through 1.3 inch liquid crystal panel.
Mirror
box unit
14, 12 Multi-lens Multi-lens allows a circular beam light emitted from the light source to illuminate the square
liquid crystal panel evenly, thus providing projected pictures with less brightness variation.
13 Cold mirror Visible light reflects at plane of incidence and goes to liquid crystal direction but infrared light and ultraviolet light penetrate, thus preventing undesired harmful light components from
entering the liquid crystal panel.
10a~
10f Dichroic mirror
Only red light component of white light emitted from the lamp transmits through 10a and
reflected by 10b, and enters liquid crystal panel (R). At the same time, only green of green
and blue light components reflected is reflected by 10c and enters G-panel. While the blue
light component transmits through and enters B-panel. Light transmitted through each liquid
crystal synthesized by the dichroic mirror 10f.
5 Field lens Light transmitted through liquid crystal panel is converged in direction of focal point and
effectively entered entrance pupil of the projection lens.
4
Phase difference
plate/ incidence
side polarized
plate
Spectral characteristics for the dichroic mirror depend on polarization directions of the light
(P-polarization, S-polarization). To use the characteristics, a place the phase difference plate
which possesses the characteristics to rotate the polarization direction of light by 45 degrees
is provided. When the spectral characteristic of S-polarization is important, the phase of S-
polarization is converted so that it matches the transmission axis of the incidence side
polarization plate for the S-polarization light to pass the panel best.
On the other hand for the P-polarization, the phase is adjusted so that the P-polarization light
passes the panel best.
In this unit, when the S-polarization characteristic takes effective for the G-light component
and when the P-polarization characteristic takes effective for the R and B light components,
thus improving the light transmission amount projected from the optical unit and the color
reproduction characteristics.
3R
3G
3B
Liquid crystal
panel
(LCD)
Light exit side polarized plate and phase difference plate are put on the light exit plane.
Polarization direction of transmission light rotates by 90 degrees when no signal voltage is
applied,but a polarizedplate has a characteristicwhich suppresses therotationwhen a voltage
is applied, To effectively use this characteristic, polarized plates, phase difference of polarized
components transmitted through incidence side and exit side of which is 90 degrees, are
located.That is, picture is displayed so thatlight transmits through most (white) when no signal
voltage is applied and the light transmits through least(black) when a signal voltage is applied.
Polarized light components transmitted through incidence side polarized plate is rotated by 45
degrees from Y axis in clockwise. This is to match aligning film of the liquid crystal panel for
increasing efficiency of the light transmission.
Phase difference plate rotates the exit side polarized plate by 45 degrees in counterclockwise
direction (that is, in the light polarizing direction of the transmitting light) to obtain S-polarization
light. This operation is to increase effect of polarized screen because, generally speaking,
transmission axis of polarized screen has the same direction as that of S-polarization.
Projection
lens 1 Projection lens
Projects pictures displayed on the liquid crystal at a wall, screen, etc. Light axis of the projection
lens is located at upper side of center of the liquid crystal panel because of a tilt projection
system employed. In a normal projection system, the projection screen is positioned at right
angle to the unit. In this case, the unit body will disturb for persons to see the screen in practice.
So, the projection will be directed upward, and this causes a trapezoidal distortion in the
picture. To prevent this, the tilt projection system which allows the users to see the pictures
projected without the trapezoidal distortion. (Figs. 3-4 and 3-5)

3-3
1
3
910 f
10 e
10 d
10 b
10 a
12
13
To Lamp
10 c
19
14
15
16
17
18
5
4
R
3G
3B
Fig. 3-2 Polarizing direction at each part (G light components)
Fig. 3-1 Optical path diagram
345
Exit side
polarizing
direction
P-polarization
light
S-polarization
light Incidence
side
polarizing
direction
S-polarization
light
Phase
difference
plate
(45 rotation)
Incidence side
polarized
plate
Liquid
crystal
panel
(90 rotation)
Exit side
polarized
plate
Phase
difference
plate
(45 rotation)
x
y
22.5 45 45 22.5
4 3
P-polarization
light
S-polarization
light
No. Part name
1 Projection lens
3R Liquid crystal panel (red)
3G Liquid crystal panel
(green)
3B Liquid crystal panel (blue)
4Phase difference plate +
polarized plate
5 Field lens
9 Mirror box unit
10a-f Dichroic mirror
12 Multi-lens B
13 Cold mirror
14 Multi-lens A
15 Capacitor lens
16 Elliptical reflector
17 Metal halide lamp
18 Lamp unit
19 High voltage supply

3-4
(a) General projection system (b) Picture by general projection system
Fig. 3-4 General projection system
(b) Picture by tilt projection system
Fig. 3-5 Tilt projection system
Screen
Reflector Field lens
Lamp
Liquid crystal panel
Projection lens Projection
lens light
axis
Fig. 3-3 Polarizing direction at each part (R/B light component)
(a) Tilt projection system
Screen
Reflector Field lens
Lamp
Liquid crystal panel
Projection lens
Exit side
polarizing
direction
P-polarization
light
S-polarization
light Incidence
side
polarizing
direction
S-polarization
light
Phase
difference
plate
(45 rotation)
Incidence side
polarized
plate
Liquid
crystal
panel
(90 rotation)
Exit side
polarized
plate
Phase
difference
plate
(45 rotation)
x
y
22.5 45 45 22.5
4 3
S-polarization
light
P-polarization
light

4-1
SECTION IV
RGB DRIVE CIRCUIT

4-2
1. OUTLINE
This circuit is described using G process as an example
and composed of level shifter, gamma (g), black limiter,
inverted signal amplifier, sample & hold circuit and liquid
crystal panel.
A block diagram of the drive circuit is shown in Fig. 4-1.
3.6V
2.3V
Q949
R976
Q945
Q946
Q947
Q948 Q950
4.8 mA 4.8 mA
Q952
Q953
Q951
R978
220
R979
15
5.36V
4.06V
1.83VDC
1
4
2
3
5 13
Q945 – Q953 Q954 – Q963 Q965 – Q970
Q971 – Q973
Q974 – Q980
SW circuit
Q982
PD74HC4066A
Q983
CXA2504N
Level
shifter Gamma
circuit Level shifter
black limiter
Normal
signal drive
Inverted
signal drive
Sample
and
hold circuit
Sample and hold pulse
Liquid
crystal
panel
Fig. 4-1
2. CIRCUIT DESCRIPTION
The following description will be given assuming thatVBE
of transistor is 0.7V.
2-1. Level Shifter (Q945 – Q953)
This circuit is composed of the emitter follower Q945, full
feedback unit gain amplifier Q946 – Q950, and the current
source circuit of sub bright for Q951 – Q953. The circuit
operates to vary only the DC level of the input signal and
develops the signal with only the DC level shifted from the
input signal at Q949. The shift level is determined by the
current flowing into R976.
When a triangular waveform of 2.3V – 3.6V shown in Fig.
4-2 is input, a triangular waveform of 3.0 – 4.3V appears at
the base of Q946.At the same time, a triangular waveform
of approx. 3.0V – 4.3V also appears at the base of Q948.
Assuming the sub brightness adjustment voltage at Q953
is 1.83VDC, a current of (1.83V – 0.7V)/(220 + 15) = 4.97
mA flows into Q951 and Q950, and this current also flows
into R976. Therefore, the emitter voltage of Q949 devel-
ops 1.06V higher than the base voltage of Q948 as shown
in the equation; 4.8 mA x 220W= 1.06V. And the triangu-
lar waveform of 4.06V – 5.36V appears at the emitter of
Q949.
Fig. 4-2 Level shifter circuit

4-3
2-2. Gamma (gg
gg
g) Circuit
The circuit consists of a current source consisting of R983,
R984, Q954, full feedback amplifier Q955 – Q960, the gain
variation circuit Q961 – Q963 and R991. (The circuit in-
cluding Q955 – Q963 is called the gamma circuit.)
A current of (12.7V – 0.7V)/(1.3 kW+ 15W) = 9.15 mA is
flown into the current source for Q954 and the same cur-
rent is also flown into Q956 (Q947). At the same time, a
current of 9.15 mA x(15/20) = 6.9 mA is flown into Q960.
The followings are described referring to Fig. 4-3.
The signal from the level shifter is supplied to the base of
Q955.If the device elements and currents of Q955 andQ957
are exactly the same, the base state of Q955 is same as that
of Q957. However, Q955 and Q957 are not paired in their
characteristics, the actual base state will be different. The
base state of Q957 is described by referring to the triangu-
lar waveform of 4.06V – 5.36V.
When the base of Q963 develops 3.55 VDC, the emitter of
Q961 develops 4.25VDC. In the signal area where the base
of Q963 is higher than 4.25V, the current of 7.7 mA is flown
into R988 because of Q961 turned off, and the emitter volt-
age of Q956 increases by amount of 1.7V, 7.7 mA x220W
= 1.7V, from the base of Q957.As the base voltage of Q957
is close to 4.25V, Q961 turns on and the current is flown
into the collector of Q960 through R991.
When the base voltage of Q957 develops 4.06V, the cur-
rent flowing into R991 is 2.8 mA, (4.25V – 4.06V)/68 =
2.8 mA. The current flowing into R998 decreases by that
amount and the voltage shifting amount also decreases by
the same amount, 2.8 mA x220W= 0.62V. The operation
is shown in Fig. 4-4.
Fig. 4-4 Gamma circuit operation
Q955
Q956Q954
9.15 mA 7.7 mA 0.5 mA
5.36V
4.06V
Q956
Q961
Q962
Q963
4.25V
R988
220
R991
68
Q957
Q960
7.06V
5.14V
5.36V
4.06V
3.55 V DC
R1004
Q968
1.3k
15
Fig. 4-3 Gamma circuit
7.06V
5.76V
5.14V
0.62V
(5.94V)
5.36V
(4.24V)
4.06V
1.7V
Q957
Base voltage
Q956
Emitter voltage

4-4
2-3. Level Shifter Circuit
(Q965 – Q968, R1044)
Q965 – Q967 works as a current source.Assuming that the
base voltage of Q965 is 1.76 VDC, the current 4.2 mA is
flown into Q967 and the same current also flown into Q968.
The current and R1044 make a voltage drop and only the
DC level is shifted.
2-4. Black Limiter (Q969, Q970)
The black limiter is a switching circuit and its operation is
as follows. When the base voltage of Q969 is higher than
that of Q970, Q969 turns on and when the base voltage of
Q969 is lower than that of Q970, Q969 turns off and Q970
turns on.
2-5. Inverted Signal Amplifiers
(Q974 – Q981)
• Q974, Q975: Emitter follower
• Q976 – Q978: Inverted signal amplifier
• Q979 – Q981: Emitter follower
The op. amplifier is composed of Q976 – Q978. Q977 base
accepts an inverted input and Q978 normal input. For easy
understanding of the op. amplifier, an op. amplifier shown
in Fig. 4-5 will be refferred.
Fig. 4-5
The output of Q977 is 7V x(1 + R1018/R1017) – 4V =
10V, so 7V x(1 + R1018/R1017) – 6V = 8V is output. (The
constant of R1017 is assumed to 1 kW, in considering the
internal emitter resistor of Q975.)
Accordingly, the output shown in Fig. 4-6 is obtained.
Fig. 4-6 Reverse output operation
2-6. Switch Circuit (Q982 µPD74HC4066A)
The normal and inverted signal outputs are switched for
every horizontal and vertical period.
The signal is inverted for one horizontal period and then
further inverted for one vertical period.
Fig. 4-7 SW circuit operation
Fig. 4-8
1
13
2
3
45
R1025
TP905
Q982
Normal
input signal
Output
signal
Inverted
input signal The signal is inverted
for one horizontal period
and then further inverted
for one vertical period.
Inverted
phase
10V
6V 7V
4V
8V
Q975 Emitter
Q977
Collector
Q978 Base
R1017
6V
4V
R1018
1k
1k
7V
10V
8V(7V)
6V
4V
Q977
Collector output
Q978 Base Input

4-5
2-7. Sample & Hold Circuit
The block diagram of the circuit is shown in Fig. 4-10 and
its connection diagram is shown in Fig. 4-11. As shown in
the block diagram in Fig. 4-9, 6CH, each consisting of the
level shifter, S/H (sample and hold) and driver circuits, are
contained in CXA2504N.
Each sample & hold operation is carried out on pins 18,
19, 20, 1, 2 & 3 and the re-sample & hold operations for
6CH are carried out together on pins 21 and 40.This means
that the serial data is converted to the parallel data and the
LCD panel operation frequency is lowered.
S/H
16 23
S/H
15 25
S/H
13 27
S/H
8 33
S/H
6 35
S/H S/H
S/H
S/H
S/H
S/H
S/H
5
18
37
19 20 1 2 321
40
SH1
SH2
SH3
SH4
SH5
SH6
Drive
Sample & hold
The timings of pins 21
and 40 are the same
as that of SH6.
Re-sample & hold
Fig. 4-9 Sample & hold operation