Trenz Electronic Spartan-6 FPGA User manual

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TE0630 Spartan-6 FPGA Industrial Micromodule
User Manual
UM-TE0630 (v 0.21) 3 July 2013 Trenz Electronic GmbH
eatures
●High-density plug-in Xilinx Spartan-6
module
●US 2.0 interface with high-speed
(480 Mbit/s) data rate
●Large SPI Flash for configuration and user
data, accessible via PGA, JTAG and USB
interfaces
●Large DDR3 SDRAM
●PGA configuration via SPI, JTAG or US
●3 high-efficiency on-board switch-mode
DC-DC converters
●Power supply from B2B connector (carrier
board) or USB connector
●lexible expansion via high-density
shockproof 2 connectors
●Most user I/Os on B2B connectors routed
as LVDS pairs
●Evenly spread supply pins for good signal
integrity
●Industrial temperature grade available
upon request
●Low-cost, versatile and ruggedized
design
●Small size
Specifications
●FPGA - XC6SLX45/75/100/150-
2CSG484C(I)
●US -controller: CY7C68013A-56LTXC(I)
●Non-volatile memory: 64 Mbit SPI lash
for configuration and user data
●Volatile memory: 1 Gb x 16 DDR3
SDRAM
●Up to 110 FPGA user I/O
●Supply voltage range: 4.0 V - 5.5 V
●1 user push-button
●4 user LEDs
●2 user DIP switches
●Dimensions: 40.5 mm x 47.5 mm
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Industrial Micromodule

UM-TE0630 (v 0.21) 3 July 2013
Table of Contents
1 Technical Specifications...............................................................................................................4
1.1 Module options.....................................................................................................................4
1.2 Dimensions...........................................................................................................................4
2 Detailed Description.....................................................................................................................5
2.1 Block Diagram......................................................................................................................5
2.2 Power Supply.......................................................................................................................5
2.2.1 Supply from B2B Connector.........................................................................................5
2.2.2 Supply from USB Connector.........................................................................................5
2.2.3 On-board Power Rails...................................................................................................6
2.2.4 Power-on Reset............................................................................................................7
2.3 PGA User I/Os....................................................................................................................8
2.4 Board-to-board Connectors..................................................................................................9
2.5 USB Connector..................................................................................................................10
2.6 JTAG connector..................................................................................................................11
2.7 Serial EEPROM..................................................................................................................11
2.8 SPI lash............................................................................................................................11
2.9 DDR3 SDRAM....................................................................................................................12
2.10 USB Controller.................................................................................................................12
2.11 Clock Oscillators...............................................................................................................13
2.12 LEDs.................................................................................................................................13
2.13 Push-Button......................................................................................................................14
2.14 DIP Switch........................................................................................................................14
2.15 Board revisions and assembly variants...........................................................................14
3 TE0300 compatibility.................................................................................................................15
3.1 Mechanical compatibility....................................................................................................15
3.2 Electrical compatibility........................................................................................................15
4 Module Configuration................................................................................................................17
4.1 JTAG PGA Configuration.................................................................................................17
4.2 SPI PGA Configuration.....................................................................................................18
4.3 e USE programming..........................................................................................................18
4.4 EZ-USB X2 irmware Programming................................................................................18
4.5 EZ-USB X2 EEPROM Programming...............................................................................19
5 USB Drivers Installation.............................................................................................................21
5.1 Generic Driver....................................................................................................................21
5.2 Dedicated Driver.................................................................................................................24
6 B2B Connectors Pin Descriptions.............................................................................................26
6.1 Pin Labelling.......................................................................................................................27
6.2 Pin Types............................................................................................................................27
6.3 J4 Pin-out...........................................................................................................................28
6.4 J5 Pin-out...........................................................................................................................29
6.5 Signal Integrity Considerations..........................................................................................30
7 Related Materials and References............................................................................................30
7.1 Data Sheets........................................................................................................................30
7.2 User Guides........................................................................................................................30
8 Glossary of Abbreviations and Acronyms..................................................................................30
9 Legal Notices.............................................................................................................................31
9.1 Document Warranty............................................................................................................31
9.2 Limitation of Liability...........................................................................................................31
9.3 Copyright Notice.................................................................................................................31
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UM-TE0630 (v 0.21) 3 July 2013
9.4 Technology Licenses..........................................................................................................32
10 Environmental Protection........................................................................................................33
10.1 REACH (Registration, Evaluation, Authorisation and Restriction of Chemicals)
Compliance Statement.............................................................................................................33
10.2 RoHS (Restriction of Hazardous Substances) compliance statement............................33
10.3 WEEE (Waste Electrical and Electronic Equipment).......................................................33
Appendix A. Indirect SPI Programming using iMPACT...............................................................35
Document Change History..........................................................................................................39
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1 Technical Specifications UM-TE0630 (v 0.21) 3 July 2013
1 Technical Specifications
1.1 Module options
FPGA options
Module can be ordered with Spartan-6 XC6SLX45, XC6SLX75, XC6SLX100,
XC6SLX150 chip1.
Temperature grade options
Module can be ordered in commercial or in extended (from -25 C° to +85 C°)
temperature grade.
1.2 Dimensions
igure 1 shows main module dimensions from top view.
Mounting hole diameter is 3.2 mm.
1 Contact Trenz Electronic support for availability
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Figure 1: Module dimensions in mm

2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
2 Detailed Description
2.1 Block Diagram
2.2 Power Supply
The module can be powered by B2B connector J5 or the USB connector. If both
power supplies are available, the B2B connector power supply takes
precedence, disabling the USB power supply automatically.
2.2.1 Supply from 2 Connector
The B2B connector power supply requires a single nominal 5 V DC power
supply. The power is usually supplied to the module through the 5 V contacts
(5Vb2b) of B2B connector J5 (see chapter 6.4 J5 Pin-out). The recommended
minimum supply voltage is 4 V. The maximum supply voltage is 5.5 V. The
recommended maximum continuous supply current is 1.5 A.
2.2.2 Supply from US Connector
The module is powered by the USB connector if the following conditions are
met:
●the module is equipped with an USB connector,
●the module is connected to a USB bus,
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Figure 2: TE0630 block diagram

2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
●no power supply is provided by B2B connectors.
In this case, other components (e.g. extension or carrier boards) may also be
powered by the corresponding 5 volt line (5V) of B2B connector J5.
2.2.3 On-board Power Rails
Three on-board voltage regulators provide the following power supply rails
needed by the components on the module:
●1.2V, 3.0 A max
●2.5V, 0.8 A max
●3.3V, 3.0 A max
●1.5V, 1.0 A max
igure 3 show power supply diagram.
Figure 3: TE0630 Power diagram
The power rails are available for the PGA and can be shared with a carrier
board by the corresponding lines of the B2B connectors J4 and J5. Please
note that the power consumption of the FPGA is highly dependent on the
design actually loaded. So please use a tool like Xilinx Xpower to estimate the
expected power consumption of your design.
Even if the provided voltages of the module are not used on the carrier board, it
is recommended to bypass them to ground with 10 n - 100 n capacitors.
PGA I/O banks power supply
Spartan-6 architecture organizes I/Os into four I/O banks, see Table 1 for supply
voltage used for each bank.
VCCIO0 voltage can be configured in 3 ways:
●2.5V - When resistor R103 is populated and resistor R102 is not
populated.
●3.3V - When R103 is not populated and resistor R102 is populated.
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●External supply - When R103 is not populated and R102 is not
populated. In this case external supply source have to be connected to pins
1, 2, 3, 4 of J4 B2B connector2.
Others options of VCCIO0 power supply are not supported and can
damage the FPGA!
See igure 4 to locate R102 and R103 on PCB.
ank Supply
Voltage
B0 VCCIO0
B1 1.5V
B2 3.3V
B3 3.3V
Table 1: FPGA banks VCCIO power supply
Note that some of Spartan-6 I/O types are partially compatible, so pins of
compatible types can be used as inputs for signal of other type. See “Spartan-6
PGA SelectIO Resources” page 38 for detailed information.
2.2.4 Power-on Reset
During power-on, the /RESET line is first asserted. Thereafter, the supply
voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET
line active (low) as long as the supply rail remains below the threshold
voltage(2.93 volt). An internal timer delays the return of the /RESET line to the
inactive state (high) to ensure proper system reset prior to a regular system
start-up. The typical delay time td of 200 ms starts after the supply rail has risen
2 See Spartan-6 documentation fo VCCIO power range.
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Figure 4: R102 and R103 location

2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
above the threshold voltage.
Figure 5: Reset on power-on
After this delay, the /RESET line is reset (high) and the PGA configuration can
start. When the supply rail voltage drops below the threshold voltage, the
/RESET line becomes active (low) again and stays active (low) as long as the
rail voltage remains below the threshold voltage (2.93 volt). Once the rail
voltage raises again and remains over the threshold voltage for more than the
typical delay time td of 200 ms, the /RESET line returns to the inactive state
(high) to allow a new system start-up.
2.3 FPGA ser I/Os
TE0630 provides user I/O signals connected to B2B connectors J4 and J5.
There are 3 types of user I/O signals:
●Single ended;
●Differential pairs (each pair is configurable as 2 single-ended digital I/Os);
●Differential pairs, which can be used as clock inputs (each pair can be used
as usual differential pair or 2 single-ended digital I/Os).
Table 2 show user I/O count for J4 and J5.
J4 J5 Total
Single ended 12 18 30
Differential 18 16 34
Differential (clock) 4 2 6
Total 56 54 110
Table 2: User I/O count by connector
Table 3 show user I/O divided by VCCIO supply voltage.
VCCIO0 3.3V Total
Single ended 1 29 30
Differential 18 16 34
Differential (clock) 4 2 6
Total 45 65 110
Table 3: User I/O count by VCCIO
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
2.4 Board-to-board Connectors
The module has two B2B (board-to-board) receptacle connectors (J4 and J5)
for a total of 160 contacts. igure 6 shows B2B connectors location on board;
USB connector is located on the top side and is shown to define module
position.
Figure 6: 2 connectors location
TE0630 uses high-density shockproof connectors shown in igure 7. Connector
part numbers are listed in Table 4.
Figure 7: Module connector
Supplier Header
Digikey
H11113CT-ND
H11113TR-ND
H11113DKR-ND
Hirose D 17(3.0)-80DS-0.5V(57)
Trenz Electronic 22684
Table 4: Module connectors part numbers
The on-board receptacles mate with their corresponding headers on the carrier
board shown in igure 8. Ordering numbers of mating connectors are listed in
Table 5.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
Figure 8: Mating (carrier board) connector
Supplier Header
Digikey
H11148DKR-ND
H11148TR-ND
H11148CT-ND
Hirose D 17(4.0)-80DP-0.5V(57)
Trenz Electronic 22938
Table 5: Carrier board headers part numbers.
igure 9 shows the definition of stacking height featured by the combination of
the TE0630 receptacle with its corresponding header.
Figure 9: 2 stacking
The stacking height of the TE0630 B2B connectors is 7 (seven) mm. The
stacking height does not include the solder paste thickness.
2.5 SB Connector
The module uses a mini-USB (B type) receptacle connector.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
Figure 10: Mini-US connector
2.6 JTAG connector
The offset holes of header J2 allow a removable press fit of standard 0.100 inch
header pins to connect flying leads without any soldering necessary. JTAG
signals are available on the dedicated header J2 through a JTAG programmer
with flying leads as described in Table 6.
TMS
TDI
TDO
TCK
GND
Vref (2.5 V)
Table 6: JTAG header J2 pin-out
2.7 Serial EEPROM
TE0630 is equipped with a Micron Technology 24LC128 128 K I2C CMOS Serial
EEPROM (U1). It is used for EZ-USB X2 firmware, vendor ID and device ID
storage. EEPROM is accessible through the EZ-USB X2 microcontroller.
2.8 SPI Flash
TE0630 is equipped with a Winbond W25Q64BV 64 Mb (8 MB) serial flash
memory chip (U14). This serial flash chip can operate as general SPI memory
mode and in double or quad modes. Usage of dual and quad modes increase
bandwidth up to 40 MB/s. or more information see Winbond W25Q64BV
product owerview.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
2.9 DDR3 SDRAM
TE0630 is equipped with a 1 Gb (128 MB) DDR3 SDRAM chip. DDR3 memory
is connected to PGA bank 1.
2.10 SB Controller
TE0630 is equipped with a Cypress EZ-USB X2 controller to provide a high-
speed USB 2.0 interface. The controller uses 4 interfaces (See chapter 2.1
Block Diagram):
●USB interface (to USB connector);
●I2C interface (to EEPROM);
●SPI interface (to PGA and lash);
●I O interface (to PGA).
The I2C interface connects the USB controller to the EEPROM chip, which
stores vendor ID and device ID. See chapter 2.14 DIP Switch for available
options.
The SPI interface id used to communicate with the PGA and to access the SPI
serial lash chip.
The I O interface provides a high-speed communication channel with the
PGA. The interface can transfer up to 48 MB/s burst rate. PGA pin-out
information can be found in Table 7.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
Signal name FPGA pin
D0 J6
D1 H8
D2 H5
D3 H6
D4 G7
D5 G8
D6 8
D7 A3
24MHZ1 G3
PA0/INT0 D1
PA1/INT1 D2
PA2/SLOE C1
PA3/WU E4
PA4/ I OADDR0 B1
PA5/ I OADDR1 C3
PA6/PKTEND B2
PA7/ LAGD/SLCS A2
RDY1/SLWR M3
RDY0/SLRD M4
CTL2/ LAGC E3
CTL1/ LAGB E1
CTL0/ LAGA 3
I CLK N4
Table 7: US controller interface: FPGA pin-out
2.11 Clock Oscillators
Two clock oscillators are installed on the TE0630.
Clock oscillator U10 generates a 24 MHz clock signal for the PGA and the
USB controller. This clock signal is used for synchronous communication
between PGA and USB controller.
Clock oscillator U11 generates a 100 MHz3 clock signal used as a main system
clock in PGA designs. See Table 8 for pin-out information.
Signal Frequency FPGA pin
24MHZ1 24 MHz G3
SYSCLK 100 MHz AA12
Table 8: Clock signals pin-out
2.12 LEDs
TE0630 is equipped with four active-high LEDs. See Table 9 for details.
3 Oscillator frequency can be changed by user request. Contact Trenz Electronic for details.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
Signal name FPGA pin LED
U_LED1 1 D3
U_LED2 2 D5
U_LED3 J4 D6
U_LED4 K8 D7
Table 9: LEDs pin-out
2.13 Push-Button
TE0630 module is equipped with one active-high push-button (signal is set to
logical "1" when button is pressed). Table 10 show push-button connection
details.
Signal name FPGA pin P
PB R7 S5
Table 10: Push button pin-out
2.14 DIP Switch
On-board 4xDIP switch S1 used for system and user settings.
Switch 1 (S1A) is used to connect the USB controller to the I2C serial EEPROM.
When S1A is "ON", serial I2C EEPROM is connected to the USB controller,
when switch is "O ", the USB controller is disconnected from the EEPROM4.
Turn S1A off when programming the USB EEPROM (storing the USB vendor ID
and device ID). This will force the USB controller to provide its default vendor ID
and device ID.
Switch 2 (S1B) is used to control DC-DC converters. When switch is "O ",
converters are controlled by the USB controller. When switch is "ON",
converters are enabled regardless of USB controller actions. At start-up, the
USB controller switches off 1.2V, 1.5V and 2.5V power rails and starts up the
module in low-power mode. After enumeration, the USB controller firmware
switches the 1.2V, 1.5V and 2.5V power rails on, if enough current is available
from the USB bus.
Switches 3 (S1C) and 4 (S1D) can be used as user switches. Switches are
active-low. Pull-up resistors should be defined in user constrains file (UC ) to
use this switches in PGA design. See Table 11 for details.
Signal name FPGA pin Switch
IO_L61_N_1 AB21 S1C
IO_L63_N_1 AA22 S1D
Table 11: DIP switch pin-out
2.15 Board revisions and assembly variants
To determine PCB revision and assembly variant from PGA, TE0630 have
dedicated user signals, which can be read by user core.
Board revision coded in 4 bits BR[3:0]
4 Zero-resistor R90 (not populated by default) short this switch and connect EEPROM regardless of S1A position.
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2 Detailed Description UM-TE0630 (v 0.21) 3 July 2013
Signal name FPGA pin
BR0 R19
BR1 V19
BR2 V20
BR3 T17
Table 12: oard revision pins
To define low (zero) level BR pin connected to ground rail, to define high (one)
level BR pin left float (open). These pins should be configured with "pullup"
option in user design.
See Table 12 for current list of board revisions.
R3 R2 R1 R0
0 0 0 0 00 Initial revision
Table 13: oard revisions
Module assembly variant encoded using AV[3:0] pins.
Signal name FPGA pin
AV0 Y20
AV1 R15
AV2 R16
AV3 R17
Table 14: Assembly variants pins
To define low (zero) level AV pin connected to ground rail through zero resistor,
to define high (one) level AV pin left float (open). These pins should be
configured with "pullup" option in user design.
Available module assembly variants listed in Table 15.
AV3 AV2 AV1 AV0
0 0 0 0 Base assembly variant
Table 15: Module assembly variants
3 TE0300 compatibility
TE0630 module designed to be compatible with TE0300 board by main
mechanical and electrical characteristics.
3.1 Mechanical compatibility
Both modules have the same board dimensions. TE0630 mount holes and B2B
connectors locations are match with TE0300. See chapter 1.2 Dimensions for
detailed information.
TE0300 and TE0630 uses same B2B connectors types. In chapter 2.4 Board-
to-board Connectors you can find B2B connectors part numbers and main
characteristics.
3.2 Electrical compatibility
TE0300 and TE0630 have similar power requirements and matched power
input pins. User signals to B2B connectors routed as differential pairs and single
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3 TE0300 compatibility UM-TE0630 (v 0.21) 3 July 2013
ended lines. Differences in pin types shown in Table 16, not listed signals have
same or compatible5 type.
Connector:Pin TE0300 pin name TE0300 Type TE0630 pin name TE0630 Type
J4:5 B3_L01_P DIO V3_IO_01 SIO
J4:7 B3_L01_N DIO V3_IO_02 SIO
J4:9 B3_L02_P DIO V3_IO_03 SIO
J4:11 B3_L02_N DIO V3_IO_04 SIO
J4:17 B0_L24_N DIO V0_IO_01 SIO
J4:19 B0_L24_P DIO V0_IO_01_N DIO
J4:6 B3_L07_P DIO V3_IO_06 SIO
J4:8 B3_L07_N DIO V3_IO_07 SIO
J4:10 B3_L03_N DIO V3_IO_08 SIO
J4:12 B3_L03_P DIO V3_IO_09 SIO
J5:13 B3_L22_P DIO V3_IO_12 SIO
J5:15 B3_L22_N DIO V3_IO_13 SIO
J5:19 B3_L20_P DIO V3_IO_14 SIO
J5:21 B3_L20_N DIO V3_IO_15 SIO
J5:16 B3_L21_N DIO V3_IO_17 SIO
J5:18 B3_L21_P DIO V3_IO_18 SIO
J5:20 B3_L23_N DIO V3_IO_19 SIO
J5:22 B3_L23_P DIO V3_IO_20 SIO
J5:32 B2_L06_P DIO V3_IO_24 SIO
J5:34 B2_L06_N DIO V3_IO_25 SIO
J5:41 B2_GCLK13 CIO V2_IO_02 SIO
J5:49 B2_GCLK_L13_N CIO V2_IO_24_P DIO
J5:51 B2_GCLK_L13_P CIO V2_IO_24_N DIO
Table 16: TE0300 and TE0630 pin types differences.
See Table 17 for pin types definitions.
Type
colour code Description
DIO Unrestricted, general-purpose differential user-I/O pin.
SIO Unrestricted, general-purpose user-I/O pin.
CIO Unrestricted, general-purpose differential user-I/O pin. This pin also can be used as PGA clock input.
Table 17: TE0300 and TE0630 pin types
Most user signals to B2B connectors routed from same PGA banks.
Differences shown in Table 18.
5 Signals routed as differential pairs can be used as single ended.
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3 TE0300 compatibility UM-TE0630 (v 0.21) 3 July 2013
Connector:Pin TE0300 ank TE0630 ank
J4:15 0 3
J4:36 0 3
J4:52 0 3
J5:33 2 3
J5:28 2 3
J5:30 2 3
J5:32 2 3
J5:34 2 3
J5:38 2 3
J5:40 3 2
J5:42 3 2
J5:50 3 2
J5:52 3 2
Table 18: TE0300 and TE0630 user signals I/O banks differences.
I/O Banks power supply for both modules shown in Table 19.
ank TE0300 TE0630
B0 VCCIO (1.2 V - 3.3 V) VCCIO (1.2 V - 3.3 V)
B1 2.5 V 1.5 V
B2 3.3 V 3.3 V
B3 3.3 V 3.3 V
Table 19: TE0300 and TE0630 FPGA I/O banks power supply.
Bank 0 I/O supply voltage at both modules can be configured by user, see
chapter 2.2.3 On-board Power Rails.
4 Module Configuration
ull module configuration cycle (for just assembled board) include steps:
1. Generic USB driver installation
2. USB microcontroller large EEPROM programming
3. EEPROM programming
4. Dedicated driver installation
5. SPI lash configuration
Steps 1-3 already performed at Trenz Electronic laboratory, and not required
to perform by end user.
To work with TE0630 module using USB interface user should install dedicated
USB driver, which provide API to work with main module functions, for complete
instructions see chapter 5.2 Dedicated driver installation.
The PGA on the TE0630 can be configured by SPI lash or by JTAG
connector.
4.1 JTAG FPGA Configuration
Programming using JTAG interface provide convenient and fast way to test
PGA project. PGA configuration programmed this way is volatile and lost
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4 Module Configuration UM-TE0630 (v 0.21) 3 July 2013
after reset or power cycle.
4.2 SPI FPGA Configuration
The bit-stream for the PGA is stored in the SPI lash. To use this bit-stream
source PGA configuration option is set to “Master Serial/SPI”. See 2.8 SPI
lash for additional information.
SPI lash can be programmed in several ways:
●Direct programming by USB controller (usually done by irmware Upgrade
Tool).
●Indirect SPI programming via PGA pins, controlled by JTAG (can be done
using Xilinx iMPACT). See Appendix A. Indirect SPI Programming using
iMPACT.
●Direct SPI programming by PGA, using an SPI core ( PGA project should
contain SPI interface core and software to work with it).
In SPI lash mode, the PGA’s internal oscillator generates the configuration
clock frequency. The PGA provides this clock on its CCLK output pin, driving
the PROM’s Slave Clock input pin. The PGA begins configuring using its
lowest frequency setting. If so specified in the configuration bitstream, the PGA
increases the CCLK frequency to the specified setting for the remainder of the
configuration process. The maximum frequency is specified using the
ConfigRate bitstream generator option. The maximum frequency supported by
the PGA configuration logic depends on the timing for the SPI lash device.
or TE0630 SPI lash PROM, use ConfigRate = 12 or lower.
This options are set graphically in Xilinx ISE Software Project Navigator by
selecting the following:
●Generate Programming ile > Process Properties > Configuration Options >
Configuration Rate > 12 (or lower)
4.3 eF SE programming
To program e USE at TE0630 module follow the steps below.
●Connect 2.5V power rail to 3.3V power rail. It can be done on B2B connector
see 6 B2B Connectors Pin Descriptions. Or if module connected to
baseboard, better to short power rails on baseboard.
●Program e USE using JTAG cable and iMPACT software.
●Disconnect 2.5V and 3.3V power rails.
4.4 EZ- SB FX2 Firmware Programming
TE0630 module supplied with already programmed X2 firmware, so this
procedure is not needed for normal work flow. This procedure is required
only if custom firmware used or to restore firmware.
If the EEPROM has never been programmed before (virgin module) Switch 1
(S1A) can be switched to EEPROM (to "ON" state). See chapter 2.14 DIP
Switch for details. The USB microcontroller will detect an empty EEPROM and
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4 Module Configuration UM-TE0630 (v 0.21) 3 July 2013
will provide its default vendor ID and device ID to the USB host. If the EEPROM
has been programmed before (EEPROM not empty), S1A must be switched to
"O ". The USB microcontroller will detect a missing EEPROM and will provide
its default vendor ID and device ID to the USB host.
4.5 EZ- SB FX2 EEPROM Programming
TE0630 module supplied with already programmed EEPROM, so this
procedure is not needed for normal work flow. This procedure is required
only if custom firmware used or to restore firmware.
irst of all, check that Switch 1 (S1A) is actually switched to EEPROM. The
USB EEPROM can be programmed by opening the dedicated software
“Cypress USB Console” (double click the “CyConsole.exe” file in the
“1st_program\CyConsole” folder).
Click “Options > EZ-USB Interface” to Open EZ-USB Interface window.
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