Trident 4DWAVE-DX Product manual

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. i
Trident 4DWAVE-DX
Technical Reference Manual

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
ii Trident Microsystems, Inc.
NOTICE
The information in this document is subject to change, as the Company may make changes to product in order to improve
reliability, design, or function, without prior written notice. No part of this manual may be reproduced or transmitted in any form or
by any means without the written permission of the company.
IN NO EVENT WILL THE COMPANY BE LIABLE FOR SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES,
WHETHER ARISING DIRECTLY OR INDIRECTLY, SUCH AS LOSS OF PROFIT OR GOOD WILL, THAT MAY BE
SUFFERED IN CONNECTION WITH THE PURCHASE OF THIS PRODUCT OR FROM THE BREACH OF ANY
REPRESENTATION OR WARRANTY.
November 1997, Rev 0.2
LIMITED WARRANTY
This product is warranted against defects in materials and workmanship for a period of one year from the date of purchase.
During the warranty period, product which the Company determines fails to meet warrant will be repaired or, at the Company’s
option, replaced at no charge. To be eligible for warranty service, product must be returned to the Company or to a Company
authorized service center, costs of shipping prepaid. This warranty does not cover results of accident, abuse, neglect, use
contrary to specifications or instructions, or repair or modification by anyone other than the Company.
THE COMPANY SPECIFICALLY DISCLAIMS ALL OTHER EXPRESS, IMPLIED OR STATUTORY WARRANTIES,
INCLUDING THE IMPLIED WARRANTIES OF FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY.
IF SUCH DISCLAIMER OF ANY IMPLIED WARRANTY IS NOT PERMITTED BY LAW, THE DURATION OF ANY SUCH
IMPLIED WARRANTIES IS LIMITED TO 90 DAYS FROM THE DATE OF DELIVERY. SOME JURISDICTIONS DO NOT
ALLOW THE EXCLUSION OF IMPLIED WARRANTIES OR LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY MAY
LAST, OR THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO SUCH LIMITATIONS
OR EXCLUSIONS MAY NOT APPLY TO YOU. THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY
ALSO HAVE OTHER RIGHTS WHICH VARY FROM JURISDICTION TO JURISDICTION.
Trident Microsystems, Inc. assumes no responsibility for the use of any circuit other than circuits embodied in a Trident
Microsystems, Inc. product.
LICENSE
The Company grants the customer a non-exclusive, non-transferable license to use the software, if any, accompanying this
product for internal use on a single computer system. The end user may make a single copy of the software solely for backup
purposes; otherwise, no copies may be made of the software or any part thereof. No other license of any kind is granted to any
part of the product or any of the intellectual property therein.
TRADEMARK ACKNOWLEDGMENTS
4DWAVE-DX Technical Reference Manual, Trident™Microsystems, Inc. 1997. All rights reserved.
Trident Microsystems, Inc. is a registered trademark of Trident Microsystems, Inc.
VirtualFM, VirtualGM, and VirtualGS are Trident trademark registrations in progress.
Direct3D, DirectX, DirectSound, DirectSound3D, DirectMusic, and DirectInput are trademarks of Microsoft Corporation;
Windows, Windows 3.1, Windows 95, Windows 98, and Windows NT are registered trademarks of Microsoft Corporation.
OPL3 is a registered trademark of Yahama Corporation.
SoundBlaster and SoundBlaster Pro are trademarks of Creative Labs, Inc.
All other product names or trademarks are the property of their respective owners.
Copyright protection claimed includes all forms and matters of copyright table material and information now allowed by statutory
or judicial law or hereinafter granted, including without limitation, material generated from the software programs which are
displayed on the screen such as icons, screen display looks, etc. Reproduction or disassembly of embedded computer programs
or algorithms is prohibited.

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
ii Trident Microsystems, Inc.
Table of Contents
1INTRODUCTION................................................................................................................................................................... 1
1.1 ADVANCED PCI DIRECTSOUND™ ACCELERATOR........................................................................................................... 1
1.2 FEATURE HIGHLIGHTS................................................................................................................................................... 2
1.2.1 Advanced PCI DirectSound Accelerator................................................................................................... 2
1.2.2 High Quality Wavetable Synthesizer......................................................................................................... 2
1.2.3 Full Legacy and DOS Games Compatibility.............................................................................................. 2
1.2.4 High Quality Audio and AC ’97 Support.................................................................................................... 2
1.2.5 Advanced Streaming Architecture............................................................................................................. 2
1.2.6 Microsoft® DirectSound™/DirectSound3D™ Support.............................................................................. 2
1.2.7 Extras........................................................................................................................................................ 3
1.2.8 Software Support....................................................................................................................................... 3
1.2.9 Power Management.................................................................................................................................. 3
1.2.10 Testability.................................................................................................................................................. 3
1.2.11 Process..................................................................................................................................................... 3
1.2.12 Package and Ordering .............................................................................................................................. 3
1.3 REFERENCE DOCUMENTS.............................................................................................................................................. 3
2SYSTEM AND ARCHITECTURE OVERVIEW...................................................................................................................... 4
2.1 PCI INTERFACE............................................................................................................................................................ 5
2.2 LEGACY........................................................................................................................................................................ 5
2.3 VOICE BUFFER/STREAM BUFFER................................................................................................................................... 5
2.4 ADDRESS ENGINE......................................................................................................................................................... 5
2.5 ENVELOPE ENGINE ....................................................................................................................................................... 5
2.6 MIXER.......................................................................................................................................................................... 5
2.7 RECORDING ENGINE..................................................................................................................................................... 6
2.8 AC ’97 INTERFACE ....................................................................................................................................................... 6
3PACKAGE AND PIN ASSIGNMENTS.................................................................................................................................. 7
3.1 PIN ASSIGNMENT TABLE AND SIGNAL DESCRIPTION........................................................................................................ 7
3.1.1 PCI Interface ............................................................................................................................................. 8
3.1.2 AC ’97 Interface......................................................................................................................................... 9
3.1.3 MIDI/Game Port ........................................................................................................................................ 9
3.1.4 Test Logic.................................................................................................................................................. 9
3.1.5 Power...................................................................................................................................................... 10
3.1.6 Forward-Compatible Signal Group.......................................................................................................... 10
3.2 PHYSICAL DIMENSIONS (MM)....................................................................................................................................... 12
4ADDRESS MAP AND REGISTER DESCRIPTION............................................................................................................. 13
4.1 PCI CONFIGURATION SPACE....................................................................................................................................... 13
4.1.1 PCI Configuration Registers Description................................................................................................. 14
4.1.1.1 Vendor ID (Offset = 00h)......................................................................................................14
4.1.1.2 Device ID (Offset = 02h).......................................................................................................14
4.1.1.3 Command (Offset = 04h)......................................................................................................14
4.1.1.4 Status (Offset = 06h)............................................................................................................15

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. iii
4.1.1.5 Revision ID (Offset = 08h)....................................................................................................15
4.1.1.6 Class Code (Offset = 10h)....................................................................................................15
4.1.1.7 Cache Line Size (Offset = 0Ch)............................................................................................16
4.1.1.8 Latency Timer (Offset = 0Dh)...............................................................................................16
4.1.1.9 Header Type (Offset = 0Eh).................................................................................................16
4.1.1.10 BIST (Offset = 0Fh)..............................................................................................................16
4.1.1.11 I/O Base Address (Offset = 10h)..........................................................................................16
4.1.1.12 Memory Base Address (Offset = 14h)..................................................................................16
4.1.1.13 Subsystem Vendor ID (Offset = 2Ch)...................................................................................16
4.1.1.14 Subsystem ID (Offset = 2Eh)................................................................................................17
4.1.1.15 Capabilities Pointer (Offset = 34h).......................................................................................17
4.1.1.16 Interrupt Line (Offset = 3Ch).................................................................................................17
4.1.1.17 Interrupt Pin (Offset = 3Dh)..................................................................................................17
4.1.1.18 Minimum Grant (Offset = 3Eh).............................................................................................17
4.1.1.19 Maximum Latency (Offset = 3Fh).........................................................................................17
4.1.2 Legacy Configuration Registers Description........................................................................................... 17
4.1.2.1 Distributed DMA Configuration (Offset = 40h)......................................................................17
4.1.2.2 Legacy I/O Base (Offset = 44h)............................................................................................18
4.1.2.3 Legacy DMA (Offset = 45h)..................................................................................................18
4.1.2.4 Legacy Control (Offset = 46h)..............................................................................................19
4.1.3 Power Management Configuration.......................................................................................................... 19
4.1.3.1 Capabilities ID (Offset = 48h)...............................................................................................19
4.1.3.2 Next Item Pointer (Offset = 49h)...........................................................................................19
4.1.3.3 Power Management Capabilities (Offset = 4Ah)..................................................................19
4.1.3.4 Power Management Control/Status (Offset = 4Ch)..............................................................20
4.1.4 Interrupt Snooping Configuration ............................................................................................................ 20
4.1.4.1 Interrupt Snooping Control (Offset = 50h)............................................................................20
4.2 WAVE ENGINE AND CONTROL REGISTERS.................................................................................................................... 21
4.2.1 Address Map and Wave Register Space................................................................................................ 21
4.2.2 Legacy Registers I/O Mapping and Wave Engine Registers.................................................................. 24
4.2.2.1 Legacy Registers I/O Address and Wave Register Space I/O Mapping..............................24
4.2.2.2 Wave Engine Registers........................................................................................................25
4.2.2.3 Channel-Specific Registers..................................................................................................27
4.2.2.4 Global Volume Control and Bank A Envelope Control Registers.........................................27
4.3 LEGACY COMPATIBILITY .............................................................................................................................................. 28
4.3.1 OS Compatibility...................................................................................................................................... 28
4.3.2 I/O Compatibility...................................................................................................................................... 28
4.3.3 Legacy Functions Compatibility............................................................................................................... 28
4.3.3.1 SoundBlaster™Pro/16 OPL3 ..............................................................................................28
4.3.3.2 SoundBlaster™Pro/16 Mixer...............................................................................................28
4.3.3.3 MIDI & MPU-401 UART .......................................................................................................29
4.3.3.4 Game Port............................................................................................................................29
4.3.3.5 SoundBlaster™ DMA...........................................................................................................29
5SYSTEM TEST FUNCTIONS.............................................................................................................................................. 30

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
iv Trident Microsystems, Inc.
5.1 TEST MODE................................................................................................................................................................ 30
5.2 GLOBAL TRISTATE ...................................................................................................................................................... 30
5.3 XOR TREE................................................................................................................................................................. 30
6AC/DC PARAMETERS....................................................................................................................................................... 31
6.1 DC PARAMETERS....................................................................................................................................................... 31
6.1.1 Core (3.3V Only) ..................................................................................................................................... 31
6.1.2 I/O – 5V Signaling Environment.............................................................................................................. 31
6.1.3 I/O – 3.3V Signaling Environment........................................................................................................... 31
6.2 AC PARAMETERS ....................................................................................................................................................... 32
6.2.1 Clocks...................................................................................................................................................... 32
6.2.1.1 PCI Clock .............................................................................................................................32
6.2.2 PCI Signals.............................................................................................................................................. 33
6.2.3 Resets..................................................................................................................................................... 34
6.2.3.1 PCI Reset.............................................................................................................................34
6.2.3 AC ’97 Reset (Cold and Warm)............................................................................................................... 34
6.2.4 AC ’97 Signals......................................................................................................................................... 35
7REFERENCE SCHEMATIC................................................................................................................................................ 36
84DWAVE-DX REFERENCE BOARD BILL OF MATERIALS (REVISED: APRIL 23, 1998).............................................. 41

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 1
1Introduction
1.1 Advanced PCI DirectSound™ Accelerator
The 4DWAVE-DX is an advanced PCI audio accelerator providing full legacy compatibility, wavetable synthesis, DirectMusic™,
DirectSound™, and DirectSound3D™ on a single chip for the high-performance, cost-sensitive consumer market. It supports full
SoundBlaster™ compatibility and is fully PC97/PC98 compliant. It is named 4DWAVE as it adds time as the 4th dimension to its
interactive 3D positional audio wave streams. The time element includes such effects processing as adding Doppler, Chorus,
and Reverb effects on top of the 3D positional audio and wavetable streams.
The 4DWAVE-DX integrates a 64-voice wavetable engine with per voice effect processing capability. It supports the upcoming
Microsoft® DirectMusic™ API and is fully compatible with the DLS Level 1 (downloadable samples) specification. The 4DWAVE-
DX is optimized for Microsoft® Windows® 98 and Windows® NT™5.0 WDM streaming architecture with re-routable endpoint
support. 4DWAVE-DX integrates DirectX™ 5 3D positional audio accelerator by incorporating QSound® Labs’ QSoft3D™
technology. It includes DirectSound3D™ acceleration hardware for ITD (Interaural Time Difference), IID (Interaural Intensity
Difference), Pan, Delay, and Doppler hardware.
VirtualFM™and VirtualGS™ technologies maintain SoundBlaster™ Pro/16 DOS games compatibility while improving gaming
audio quality. The 4DWAVE-DX utilizes a Digital Enhanced Game Port, when coupled with a DirectInput™ driver, can save up to
12% of the CPU overhead nominally required by a conventional analog game port. The 4DWAVE-DX employs a high precision
26-bit digital mixer, providing an accurate 20-bit output and higher than 90dB signal-to-noise ratio when used with a high quality
AC ’97 codec.
The 4DWAVE-DX is designed with aggressive power management in mind as well. It is both ACPI-compliant and PCI Bus Power
Management Interface (PPMI)-compliant. With a low power 3.3V process and a space conscious 100 LQFP package, the
4DWAVE-DX is well suited for Notebook systems as well.
The 4DWAVE-DX delivers an impressive combination of features and performance to end-users without burdening them on
price. By combining PCI Bus Mastering for DirectSound™ acceleration, Hardware Wavetable synthesizer, Digital Enhanced
Game Port, and interactive 3D positional audio acceleration through QSoft3D™, the 4DWAVE-DX provides up to a 40% system
level performance enhancement over an equivalent ISA audio controller. It delivers high performance, high quality audio, high-
end features with efficient power management in a single-chip in a space-efficient 100 LQFP package.
It is forward socket-compatible with future 4DWAVE family products. This document will briefly describe signals in future
products to enable system designers to accommodate the future 4DWAVE family products with one design, substantially
simplifying future design and testing efforts.
Figure 1-1. 4DWAVE-DX High Level System Block Diagram
4DWAVE-DX
PCI Wavetable
DirectSound
Accelerator
PCI Interface
PCI Bus
AC'97
Audio
Codec
AC-Link
Game Port
MIDI Port

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
2Trident Microsystems, Inc.
1.2 Feature Highlights
1.2.1 Advanced PCI DirectSound Accelerator
•PCI 2.1-compliant with Bus Mastering optimized for multiple streams operation
•On-chip per voice cache minimizes PCI bandwidth
•Up to 20X improvement over ISA DMA on PCI bus bandwidth utilization
•Hardware multi-channel digital mixer
1.2.2 High Quality Wavetable Synthesizer
•64 voices polyphony wavetable synthesizer supports all combinations wavetable samples formats :
•Stereo/mono
•8-/16-bits
•Signed/unsigned
•Per channel volume and envelope control, pitch shift, tremolo, and vibrato
•Per channel effect processing and effect volume control for reverb, chorus and echo
•Microsoft® DirectMusic™ support (upcoming) with unlimited downloadable samples in system memory
•DLS1-compliant Downloadable Samples support
1.2.3 Full Legacy and DOS Games Compatibility
•Legacy game audio support with SoundBlaster™ Pro/16 compatibility on the PCI bus
•Legacy DMA support on PCI Bus with DDMA-enabled or standard (non-DDMA) PCI chipsets
•VirtualFM™ enhances audio experience through real-time FM-to–wavetable conversion
•MPU-401 compatible UART for external or internal synthesis
•VirtualGS™ provides General MIDI/GS command interpretation for wavetable & effect synthesis
1.2.4 High Quality Audio and AC ’97 Support
•CD quality audio with better or equal to 90dB signal-to-noise ratio using an external high quality AC ’97 codec
•AC ’97 support with full duplex, independent sample rate converter for audio recording and playback
•On-chip sample rate converter ensures all internal operation at 48KHz
•High precision internal 26-bit digital mixer with 16- and 20-bit digital audio output
1.2.5 Advanced Streaming Architecture
•Microsoft® WDM Streaming architecture compliant and “Re-routable endpoint” support
•Three stereo capture channels
•AC ’97 stereo recording channel through AC-link
1.2.6 Microsoft®DirectSound™/DirectSound3D™ Support
•64 voices DirectSound™ channels
•DirectSound3D™ accelerator with IID, ITD, and Doppler effects on 3D
positional audio buffers
•DirectSound™ accelerator for volume, pan, and pitch shift control on
streaming or static buffers
•QSound® QSoft3D™-based interactive 3D positional audio accelerator for
DirectX™ 5

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 3
1.2.7 Extras
•Fully Plug and Play PCI controller and software
•Digital Enhanced Game port enables analog joystick to emulate digital joystick performance using Trident- provided
DirectInput™ driver. This eliminates up to 12% of CPU overhead wasted on joystick polling.
•DirectX™ timer for video/audio synchronization
•Forward pin-compatible with next generation PCI audio accelerators
1.2.8 Software Support
•Complete DirectX™ driver suite (DirectSound3D™, DirectSound™, DirectMusic™, and DirectInput™) for Windows®
95 and Windows® 98/NT 5.0®
•Configuration, installation, and diagnostics under real mode DOS, Windows® 95/Windows® 98 DOS box
•Windows® 3.1, 95, NT4.0, Windows® 98/NT5.0 configuration, installation, and mixer program
•2, 4, or 8 Mbytes General MIDI (GM)/General Sound (GS) compliant sample Library
1.2.9 Power Management
•Desktop ACPI & PPMI Compatible
•Software Controls AC ’97 Codec Power States
1.2.10 Testability
•NAND Tree test mode
•Tri-state all I/Os test mode
•Loop-back modes for Diagnostics
•All Mixer Channels can be captured
1.2.11 Process
•Advanced 0.35um process
•Low power 3.3V (5V-safe) operation
1.2.12 Package and Ordering
•100 LQFP (14mm x 14mm x 1.4mm)
•Ordering Part Number : 7700
1.3 Reference Documents
•PCI Local Bus Specification, Revision 2.1, June 1, 1995
•ACPI - Advanced Configuration and Power Interface Specification, Revision 1.0
•PPMI - PCI Bus Power Management Interface Specification, Revision 1.0, March 18, 1997
•OnNow - Device Class Power Management Reference Specification, Audio Device Class V1.0
•AC ’97 - Audio Codec ’97 Component Specification, Revision 1.03, September 15, 1996
•8237A High Performance Programmable DMA Controller, October 1987
•DMA on the “PCIway”, Revision 6.0
•SoundBlaster Programming Information - V0.90, January 29, 1995
•Developer Kit for SoundBlaster Series, 2nd Edition, October 1993

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
4Trident Microsystems, Inc.
2System and Architecture Overview
The 4DWAVE-DX is a 64-Voice PCI Wavetable/DirectSound™ Audio Accelerator. It is packaged in a 100-pin LQFP package
targeted for desktop and space-constrained applications such as notebook or handheld computer design. As shown in Figure 1.1
above, the 4DWAVE-DX will interface to:
•PCI bus
•AC '97 serial bus for communication with an AC '97 Codec
•Digitally Enhanced Game Port
•MIDI port
The 4DWAVE family devices are designed to enable a single driver set to support current and future generation devices. This
approach allows a stable, maintainable code base. The hardware/software combinations provide the following acceleration and
functions:
•DirectSound™acceleration
•64-voice Wavetable synthesis
•Chorus effects
•Reverb effects
•FM Synthesis via VirtualFM™technology
•General MIDI/GS command interpreter via VirtualGM™/VirtualGS™technology
•3D positional audio effects
Figure 1.2 shows the major functional blocks of the 4DWAVE-DX. The following sections provide architectural descriptions for
each of the functional blocks.
PCI
INTERFACE
LEGACY
AC '97
INTERFACE
MIXERADDRESS ENGINE
ENVELOPE ENGINE
RECORDING ENGINE
VOICE /
STREAM
BUFFER
Figure 1-2. 4DWAVE-DX Functional Block Diagram

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 5
2.1 PCI Interface
The 4DWAVE-DX PCI interface is fully PCI Rev 2.1 and Plug-n-Play compliant. It consists of separate master and slave
controllers that operate independently. Both master and slave engine support burst cycles. The slave can be programmed to
accept both I/O and Memory (memory mapped I/O) cycles for 4DWAVE-DX registers. The 4DWAVE-DX register space can be
mapped by configuring the PCI Configuration registers for I/O and Memory base addressing. The legacy register space is only
accessible through I/O cycles and cannot be remapped.
4DWAVE-DX uses a single PCI interrupt. All interrupts are combined together internally to form this single interrupt signal.
Internal registers must be accessed to determine the nature of the interrupt. This function is programmed differently if the device
is in legacy emulation mode or not.
For emulation legacy DMA operation, the device can be configured to use either the Distributed DMA (DDMA, Rev 6.0 spec.)
mechanism or a Trident proprietary DMA snooping mechanism depending on whether the system core logic supports Distributed
DMA or not.
2.2 Legacy
The 4DWAVE-DX supports both the SoundBlaster™ Pro and SoundBlaster™ 16 register sets. This includes the Adlib, OPL3,
MPU-401, and Game Port. When configured to support legacy operation, the device will respond to all I/O cycles in the legacy
address regions. It integrates an on-chip SoundBlaster™compatible command interpreter. The OPL3 and MPU-401
compatibility are handled by Trident’s VirtualFM™and VirtualGM™/VirtualGS™technologies and are based on a
hardware/software combination to provide the emulation of FM synthesis and General MIDI/GS command interpretation in DOS.
The hardware provides all the registers for reads and writes to legacy locations while the software provides the interpretation and
emulation.
The 4DWAVE-DX supports a legacy analog game port and Digitally Enhanced Game Port. When using with a bundled
DirectInput™ driver, the Digitally Enhanced Game Port allows a dramatic reduction in both bus traffic and CPU utilization by
removing the requirement of “I/O polling” for the joystick position. This can save up to 12% of CPU overhead; this substantially
enhances game performance and the gaming experience. The MIDI port is supported with an MPU-401 compatible UART. This
port can also be used in an emulation mode (VirtualGM™/VirtualGS™) to support synthesis in DOS mode games.
2.3 Voice Buffer/Stream Buffer
The voice buffer/stream buffer is used to buffer the data streams between the accelerator engine and the system memory. The
stream buffer supports up to 64 channels with a 4 Dword-deep buffer per channel. The stream buffer is used for: (a) playback of
up to 64 streams of audio and effects, and (b) to support three capture channels WDM, chorus, and reverb effects.
2.4 Address Engine
The address engine supports 64 voice channels. Stereo/mono, 8-/16-bit, and signed/unsigned formats are supported. All 64
voices are optimized for DirectX™/WDM audio streams. Each channel is sample rate converted to 48KHz. The address engine
performs all the sample address calculations including using a channel specific sample rate conversion factor.
2.5 Envelope Engine
The envelope engine controls the channel volume. For the first 32 channels, it supports two global volumes, a per/channel
volume, a left-right PAN, a chorus volume, and a reverb volume. The first set also includes two volume slope buffers to allow a
MIDI ADSR (Attack-Decay-Sustain-Release) curve to be performed. The second 32 channels support a per/channel volume, a
left-right PAN, a chorus volume, and a reverb volume. All volume controls operate in dBs (decibels) of attenuation. This allows
the attenuations to simply be summed before sending the composite to the mixer.
2.6 Mixer
The 4DWAVE-DX digital mixer supports high-precision 26-bit accumulators on three separate stereo channels. The hi-resolution
accumulation allows the 64 voices to be mixed (accumulated) without degradations such as “clipping”. The mixer supports both
16-bit and 20-bit audio outputs, when coupled with high quality AC ’97 codec, and can provide higher than 90dB signal-to-noise
ratio.

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
6Trident Microsystems, Inc.
There is a separate mixer channel for each of main (AC ’97 stereo out), reverb, and chorus output. The main mixer channel data
is buffered in a FIFO before being accessed by the AC ’97 interface. This allows the device to buffer several samples ahead and
substantially increases its tolerance for bus latency and others delays caused by other system events.
2.7 Recording Engine
The recording engine records data samples from the AC ’97 codec. All AC ’97 data is sampled at 48KHz and can be recorded in
16-bit stereo format. This requires 4-bytes per sample or 192Kbytes for 1 second of record data. The recording channel also
supports independent down sampling and format conversion. By down sampling, the bus bandwidth and memory space can be
reduced. For instance, voice function using 8-bit mono samples at 8KHz uses only 8K bytes per second.
2.8 AC ’97 Interface
The AC ’97 interface supports the 5-pin AC’Link interface to the codec. The AC ’97 interface operates at a fixed 48KHz sample
rate. It provides 20-bit stereo output for playback and supports 16-bit stereo input for recording. The interface also includes a
register set that allows access to the external AC ’97 codec registers. AC ’97 power management and AC ’97 cold and warm are
fully supported.

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 7
3Package and Pin Assignments
The 4DWAVE-DX is packaged in a space-efficient 100 pin LQFP package (14mm x 14mm x 1.4mm). The 4DWAVE-DX pins can
be classified into five functional categories and one forward-compatible category:
•PCI Interface
•AC ’97 Interface
•MIDI/Game Port Interface
•Test Logic
•Power/Ground
•Forward-Compatible signal group
3.1 Pin Assignment Table and Signal Description
The following legends are used for pin characteristics in the “Type” column in Sections 3.1.1 to 3.1.6.
I = Input O = Output T = Tri-state
PWR = Power GND = Ground PU = Internal Pull-Up
The “I/O Buffer” columns in Section 3.1.1 to 3.1.6 indicate the various I/O buffer/cells used in the 4DWAVE-DX. Table 3.1 shows
the detailed I/O buffer characteristics for each I/O buffer type used.
Table 3-1. Detailed I/O Buffer Characteristics
I/O Cell Pull-up Voltage
Level Ioh (mA) Iol (mA) Voltage (V)
IBUFT_5S TTL 5V safe
BT8_5S TTL 8 8 5V safe
BT8OD_5S TTL 8 8 5V safe
BT10U_5S √TTL 10 10 5V safe
BDT4U_5S √TTL 4 4 5V safe
BDT6U_5S √TTL 6 6 5V safe
BDT10U_5S √TTL 10 10 5V safe
BDT10_5S TTL 10 10 5V safe
V5SFPAD 5V
VDD5SPAD 3.3V
VSS5SPAD GND

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
8Trident Microsystems, Inc.
3.1.1 PCI Interface
Pin Number(s) Signal Name Type I/O Buffer Signal Description
85-87,89-93, 97-
99,2-6,20-24, 27-
29,31, 33-37, 39-
40
AD[31:0] T/I/O BDT10_5S AD[31:0] (Address-Data) is the PCI 32-bit multiplexed
address and data bus. It is used to transmit the address
during the “command” phase and is used to send or receive
data during the “data” phase.
95,8,18,30 C/BE[3:0]# T/I/O BDT10_5S C/BE[3:0]# (Command/Byte Enable) is the PCI 4-bit
multiplexed command and byte enable bus. It is used to
transmit the command during the “command” phase and is
used to send or receive the active low data byte enables
during the “data” phase.
17 PAR T/I/O BDT10_5S PAR (Parity) is even parity across AD[31:0] and C/BE[3:0]#.
It is generated one clock after the address and data phases.
The current master (delayed one clock) drives parity.
9FRAME# T/I/O BDT10_5S FRAME# (Cycle Frame) is driven by the current master
active low to indicate the beginning of a transaction. It also
can be held low to indicate that the master desires a multiple
data transaction.
11 TRDY# T/I/O BDT10_5S TRDY# (Target Ready) is driven by the current target active
low to indicate it is ready to complete the current data
phase.
10 IRDY# T/I/O BDT10_5S IRDY# (Initiator Ready) is driven by the current master
active low to indicate it is ready to complete the current data
phase.
14 STOP# T/I/O BDT10_5S STOP# (Stop) is driven by the current target to indicate that
it desires to stop the current transaction.
12 DEVSEL# T/I/O BDT10_5S DEVSEL# (Device Select) is driven active low by the
addressed target to indicate that it is the target of the current
transaction.
96 IDSEL In IBUFT_5S IDSEL (Initialization Device Select) is an active high signal
driven by the system logic to select a device during a
configuration transaction.
16 SERR# T/O BDT10_5S SERR# (System Error) is an active low signal that is used to
signal the system of parity (data or address) or other system
errors.
15 PERR# T/O BDT10_5S PERR# (Parity Error) is an active low signal that is used to
signal the system of only data parity errors.
84 REQ# T/O BT8_5S REQ# (Request) is an active low signal that is driven by a
master when it needs to request the bus for a transaction.
83 GNT# In IBUFT_5S GNT# (Grant) is an active low signal that is driven by the
system arbitration logic to signal a master that it has been
granted the bus.
77 INTA# T/O BT8OD_5S INTA# (Interrupt “A”) is an asynchronous active low signal
used to signal the processor/OS of an event that requires
handling.
(Continued on next page)

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 9
PCI Interface (Cont'd)
Pin Number(s) Signal Name Type I/O Buffer Signal Description
80 RST# In IBUFTS_5S RST# (Reset) is the PCI reset signal. It is an active low
signal. This signal may be asynchronous to CLK. It bring the
PCI sequencer and the PCI outputs to a known and defined
state. The AC ’97 reset control AC_RESET# will also be
activated.
81 CLK In IBUFT_5S CLK (Clock) is the PCI Bus operation clock. This clock is
used as a reference for all bus transactions and is used by
the audio engine as the operational clock.
3.1.2 AC ’97 Interface
Pin Number(s) Signal Name Type I/O Buffer Signal Description
49 AC_SYNC T/O BDT6U_5S AC_SYNC (AC ’97 Sync) is used as a fixed 48kHz
synchronization signal.
53 AC_BITCLK In IBUFT_5S AC_BITCLK (AC ’97 Bit Clock) is a 12.288MHz clock used
for serial data transfer between the AC ’97 and 4DWAVE-
DX.
54 AC_SDATA_OUT T/O BDT6U_5S AC_SDATA_OUT (AC ’97 Serial Data Out) is the serial, time
division multiplexed, AC ’97 output data stream.
52 AC0_SDATA_IN In IBUFT_5S AC0_SDATA_IN (Primary AC ’97 Serial Data IN) is the
serial, time division multiplexed, AC ’97 input data stream.
(Note : AC0 is used to differentiate with future secondary
codecs such as AC1, AC2, etc. in multiple AC ’97 support.)
48 AC_RESET# T/O BDT6U_5S AC_RESET# (AC ’97 Reset) is the active low master reset
signal. This signal is controlled by the PCI RST# signal and
the internal Power Management register.
3.1.3 MIDI/Game Port
Pin Number(s) Signal Name Type I/O Buffer Signal Description
55 MIDI_OUT T/O BT10U_5S MIDI_OUT (MIDI Out) is the MIDI UART serial output signal.
56 MIDI_IN In IBUFT_5S MIDI_IN (MIDI In) is the MIDI UART serial input signal.
58-61 GAMEH[3:0] In IBUFT_5S GAMEH[3:0] is the MS-nibble of the Game Port. This nibble
reads the Button values and is input only.
62,64-66 GAMEL[3:0] T/I/O BDT10U_5S GAMEL[3:0] is the LS-nibble of the Game Port. This nibble
“fires” the game port timer and applications can poll the
current position by reading GAMEL[3:0] or through the
Enhanced Game Port Position Register 1 & 2.
3.1.4 Test Logic
Pin Number(s) Signal Name Type I/O Buffer Signal Description
67,68 TEST[1:0]# In
PU BDT4U_5S TEST[1:0]# are the inputs that enable the 4DWAVE-DX into
test modes during a low-to-high RST# transition.
0 0 reserved
0 1 Global Tristate
1 0 NAND Tree test
1 1 Normal Operation
70 TDO T/O BDT4U_5S Test Data Out is the data out for the NAND Tree test mode.

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
10 Trident Microsystems, Inc.
3.1.5 Power
Pin Number(s) Signal Name Type I/O Buffer Signal Description
7VCC_5V Power V5SFPAD 5V I/O Power for 5V Safe (Tolerant) Pads
1,19,26,38,51,
57,69,76,88 VCC Power VDD5SPAD Power (3.3V)
13,25,32,44,
50,63,75,82,
94,100
VSS Power VSS5SPAD Ground
3.1.6 Forward-Compatible Signal Group
These pins are not “No Connects” in 4DWAVE-DX and are defined for future socket-compatible 4DWAVE family products.
Trident will provide applications notes and design assistance for system designs intended to accommodate future 4DWAVE
family products in the same socket. These pins are shown as “shaded” pins in Section 3.2, Pin Assignment Diagram.
Pin Number(s) Signal Name Type I/O Buffer Signal Description
79 CLKRUN# I/O TBD CLKRUN# (Clock Running) is an active low signal that
controls whether the PCI clock may be stopped or should be
kept running. This pin is intended for Notebook and
“motherboard” design as CLKRUN# is not available on PCI
slot.
78 PME# I/O TBD PME# (Power Management Event) is an active low signal
that informs the system core logic that an event has
occurred that requires a modification to the power
management state of the system. This pin is intended for
Notebook and “motherboard” design as PME# is not
available on PCI slot.
42 ROM_DATA I/O TBD Serial ROM Data signal. This pin should be connected to the
“data” pin of a 2-pin serial EEPROM.
41 ROM_CLK I/O TBD Serial ROM transfer clock. This pin should be connected to
the “clock” pin of a 2-pin serial EEPROM.
46 I2S_SCLK In TBD I2S serial bit clock. This pin is intended for Notebook design
and should be connected to the ZV-port SCLK pin.
45 I2S_LRCLK In TBD I2S word select; 0 = Left Word; 1 = Right Word. This pin is
intended for Notebook design should be connected to the
ZV-port LRCLK pin.
43 I2S_SDATA I/O TBD I2S: Serial Data In. This pin is intended for Notebook design
and should be connected to the ZV-port SDATA pin.
47 AC1_SDATA_IN In TBD AC1_SDATA_IN Secondary AC ’97 serial data in. This pin
should be connected to the secondary AC ’97 Rev 2.0
codec as recommended by AC ’97 Rev 2.0 spec.
74 XVSS In TBD Crystal Ground
71 XVCC In TBD Crystal Power
72 XTALI In TBD Crystal Input
73 XTALO In TBD Crystal Output

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 11
Figure 3-1. 4DWAVE-DX Pin Assignment
Note: The shaded pins are not functional signals in 4DWAVE-DX and belong to the “Forward-compatible Signal
Group” for future socket-compatible 4DWAVE family products. Refers to Section 3.1.6 for more details.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
VCC
AD20
VCC_5V
AD19
AD18
AD17
AD16
C/BE2#
IRDY#
FRAME#
PERR#
TRDY#
DEVSEL#
VSS
STOP#
SERR#
C/BE1#
PAR
AD12
VCC
AD15
AD14
AD13
AD11
VSS
VCC
AD10
AD8
VSS
AD5 AD9
C/BE0#
AD7 AD6 AD4 AD2 AD1
ROM_DATA
AD3
ROM_CLK
I2S_SDATA
VCC
AD0
I2S_LRCLK
VSS
I2S_SCLK
AC1_SDATA_IN
AC_RESET_N
AC_SYNC
VSS
AC0_SDATA_IN
VCC
AC_SDATA_OUT
AC_BITCLK
MIDI_OUT
GAMEH1
MIDI_IN
VCC
GAMEH3
GAMEH2
GAMEH0
VSS
GAMEL3
GAMEL2
VCC
GAMEL1
GAMEL0
TEST1#
TEST0#
VCC PME# CLK GNT# INTA# CLKRUN# RST# VSS REQ# VCC AD26 AD31 AD29 AD28 AD27 AD25 VSS AD24 C/BE3# VSS AD21 AD22 AD23 IDSEL
AD30
70
71
72
73
74
75
TDO
XVCC
XTALI
XTALO
XVSS
VSS
4DWAVE-DX

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
12 Trident Microsystems, Inc.
3.2 Physical Dimensions (mm)
0.50
TYP
14 typ.
16 typ.
0.6
0+0.15
1.60 max.
0.05 -
0.15
0°-
7°
100 LQFP
76
75 51
50
26
25
100
10.20+ 0.07
- 0.03
12.00 typ.
12.00 typ.
14 typ.
16 typ.
1.00 ref.
1.40 +0.05

4DWAVE-DX
TECHNICAL REFERENCE MANUAL Document
Rev 1.1
Trident Microsystems, Inc. 13
4Address Map and Register Description
The 4DWAVE-DX is a standalone single function PCI audio device. It has registers in three address spaces: PCI Configuration
Header 0 space, I/O Space, and Memory Space. These spaces are initialized through Plug-n-Play system software routines by
configuring the registers in the 256-byte PCI Configuration Register space.
The 4DWAVE-DX has three major groups of registers and are described in the following sections :
Section 4.1 PCI Configuration Registers
Section 4.2 Wave Engine and Control Registers
Section 4.3 Legacy Registers (SoundBlaster™, Adlib, MPU-401, Game Port)
4.1 PCI Configuration Space
The device is both PPMI and DDMA compatible, which requires additional registers for set-up. The Cap_Ptr points to offset 48h
where additional registers defines the power management capabilities of 4DWAVE-DX.
Table 4-1. 4DWAVE-DX PCI Configuration Register Space
Offset (Hex) Byte 3 Byte 2 Byte 1 Byte 0
00h Device ID (Read Only = 2000h) Vendor ID (Read Only = 1023h)
04h Status Command
08h Class Code (Read Only = 040100h) Revision ID
(Read Only = 00h)
0Ch BIST
(Read Only = 0000h) Header Type (Read Only = 00h) Latency Timer Cache Line Size (Read Only = 0000h)
10h Audio IO Base Address Register
14h Audio Memory Base Address Register
18-28h RSVD (Read Only = 00000000h)
2Ch Subsystem ID (Read Only = 2000h) Subsystem Vendor ID (Read Only = 1023h)
30h RSVD (Read Only = 00000000h)
34h RSVD (Read Only = 000000h) Cap_Ptr
(Read Only = 48h)
38h RSVD (Read Only = 00000000h)
3Ch MAX_LAT
(Read Only = 05h) MIN_GNT (Read Only = 02h) Interrupt Pin (Read Only = 01h) Interrupt Line
40h DDMA_CFG
44h RSVD
(Read Only = 00h) LEGACY_CTRL LEGACY_DMA LEGACY_IOBASE
48h Power Management Capabilities
(Read Only = 0601h) Next_Ptr (Read Only = 00h) Cap_ID (Read Only = 01h)
4Ch Power Value Data
(Read Only = 00h) PMCSR_BSE (Read Only – 00h) Power Management Control/Status
50h RSVD (Read Only = 0000h) Interrupt Snooping Control

Document
Rev 1.1 4DWAVE-DX
TECHNICAL REFERENCE MANUAL
14 Trident Microsystems, Inc.
4.1.1 PCI Configuration Registers Description
4.1.1.1 Vendor ID (Offset = 00h)
Bits POR Read/Write Description
[15:0] 1023h RTrident Microsystems’ PCI Vendor ID
4.1.1.2 Device ID (Offset = 02h)
Bits POR Read/Write Description
[15:0] 2000h R4DWAVE-DX Device ID
4.1.1.3 Command (Offset = 04h)
Bits POR Read/Write Description
[15:10] 000000b RReserved
[9] 0RFast Back-to-Back enable for master transactions. The 4DWAVE-DX does not
support this feature. This bit is hardwired to a ‘0’.
[8] 0R/W SERR# enable
0 = Disables the SERR# Driver
1 = Enables the SERR# Driver
[7] 0RAddress/Data stepping or Wait cycle control. The 4DWAVE-DX does not support
this feature. This bit is hard wired to a ‘0’.
[6] 0R/W Parity Enable
0 = Ignores parity errors.
1 = Report parity errors.
[5] 0RVGA palette snoop. The 4DWAVE-DX does not support this feature. This bit is
hard wired to a ‘0’.
[4] 0REnable the “Memory Write and Invalidate” command. The 4DWAVE-DX does not
support this feature. This bit is hard wired to a ‘0’.
[3] 0REnable the device to monitor Special Cycle commands. The 4DWAVE-DX does
not support this feature. This bit is hard wired to a ‘0’.
[2] 0R/W Bus Master Enable
0 = Disables the Bus Master Operation
1 = Enables the Bus Master Operation
[1] 0R/W Memory Space Enable
0 = Disables the device to respond to Memory Space cycles
1 = Enables the device to respond to Memory Space cycles
[0] 0R/W I/O Space Enable
0 = Disables the device to respond to I/O Space cycles
1 = Enables the device to respond to I/O Space cycles