Toshiba TLCS-870/C Series User manual

8 Bit Microcontroller
TLCS-870/C Series
TMP86FH09NG
November 10, 2005

Page 2
TMP86FH09NG
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of TOSHIBA or others.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
The Toshiba products listed in this document are intended for usage in general electronics applications
( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk.
The products described in this document may include products subject to the foreign exchange and
foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be
produced and sold, under any law and regulations.
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
© 2005 TOSHIBA CORPORATION
All Rights Reserved

Page 3
030619EBP1
TMP86FH09NG
CMOS 8-Bit Microcontroller
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli-
cation or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,”or “TOSHIBA Semiconductor Reliability Handbook”etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equip-
ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instru-
ments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medi-
cal instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the
customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions.
tentative
This product uses the Super Flash®technology under the licence of Sillicon Storage Technology, Inc. Super Flash®is registered trademark of Sillicon
Storage Technology, Inc.
TMP86FH09NG
The TMP86FH09 is a high-speed, high-performance 8-bit microcomputer built around the TLCS-870/C Series
core with built-in 16-Kbyte flash memory and it is pin compatible with its mask ROM version, the TMP86CH09/
809. Writing programs in the built-in flash memory enables this microcomputer to perform the same operations as
the TMP86C809/H09. The built-in flash memory can be rewritten on board (without removing it from the PCB) by a
built-in boot program.
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 18 interrupt sources (External : 5 Internal : 13)
3. Input / Output ports (26pins)
- Large current output: 8pins (Typ. 20mA)
4. Time Base Timer
5. Watchdog Timer
6. 16-bit timer counter : 1ch
- Timer, External trigger, Window, Pulse width measurement, Event counter, PPG(Programmable Pulse
Generator) output modes
7. 8-bit timer counter : 2ch
- Timer, Event counter, PWM(Pulse width modulation) output, PDO(Programmable Divider Output)
output and PPG(Programmable Pulse Generator) modes
8. Divider output function
9. SEI : 1ch
10. UART : 1ch
Product No. ROM(FLASH) RAM PACKAGE
TMP86FH09NG 16384 bytes 512 bytes P-SDIP32-400-1.78

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1.1 Features TMP86FH09NG
tentative
11. 10-bit successive approximation type AD converter
- Analog inputs: 6ch
12. Key On Wake Up : 4ch
13. Clock operation
Single clock mode
Dual clock mode
14. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-
quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-
puts(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-
ruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-
quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-
put.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by
interruput.

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TMP86FH09NG
tentative
1.2 Pin Assignment
Figure 1-1 Pin Assignment
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
XIN
XOUT
TEST
(VAREF/AVDD) VDD
(XTIN) P21
(XTOUT) P22
RESET
(STOP/INT5) P20
(TXD) P00
(RXD) P01
(SCLK) P02
(MOSI) P03
(MISO) P04
P14
P16
P37 (AIN5/STOP5)
P36 (AIN4/STOP4)
P35 (AIN3/STOP3)
P34 (AIN2/STOP2)
P33 (AIN1)
P32 (AIN0)
P31 (TC4/PDO4/PWM4/PPG4)
P30 (TC3/PDO3/PWM3)
P12 (DVO)
P11 (INT1)
P10 (INT0)
P07 (TC1/INT4)
P06 (INT3/PPG)
P05 (SS)
P13
P15
P-SDIP32-400-1.78

Page 6
1.3 Block Diagram TMP86FH09NG
tentative
1.3 Block Diagram
Program memory
(Flash memory)
Flash memory I/F
Standby control
circuit
System control
circuit
Timing generator
High
frequency
Low
frequency
Clock
generator
Time base
timer
Watchdog
timer
16-bit
timer/counter
TC1
8-bit
timer/counter
TC3 TC4
8-bit AD
converter
Interrupt controller
TLCS-870/C
CPU
Data memory
(RAM)
Boot program
(ROM)
Address/data bus
Address/data bus
Serial
interface
SEI UART
P0
P07 to P00P37 to P30
P1
P16 to P10
P2
P22 to P20
Key-on
wake up P3
XIN
XOUT
RESET
TEST
I/O ports

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TMP86FH09NG
tentative
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1 Memory Address Map
The TMP86FH09NG memory is composed Flash, RAM SFR (Special function register) and DBR(Data
buffer register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86FH09NG memory
address map.
Figure 2-1 Memory Address Map
2.1.2 Program Memory (Flash)
The TMP86FH09NG has a 16384 bytes (Address C000H to FFFFH) of program memory (Flash ).
2.1.3 Data Memory (RAM)
The TMP86FH09NG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H
to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available
against such an area.
SFR
0000H
64 bytes SFR:
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
003FH
RAM
0040H
512
bytes
023FH
DBR
0F80H
128
bytes
DBR: Data buffer register includes:
Peripheral control registers
Peripheral status registers
0FFFH
C000HFlash: Program memory
Flash 16384
bytes
FFC0HVector table for vector call instructions
(32 bytes)
FFDFH
FFE0HVector table for interrupts
(32 bytes)
FFFFH

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2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Figure 2-2 System Colck Control
2.2.1 Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Example :Clears RAM to “00H”. (TMP86FH09NG)
LD HL, 0040H ; Start address setup
LD A, H ; Initial value (00H) setup
LD BC, 01FFH
SRAMCLR: LD (HL), A
INC HL
DEC BC
JRS F, SRAMCLR
TBTCR
SYSCR2SYSCR1
XIN
XOUT
XTIN
XTOUT
fc
0036H
0038H0039H
fs
Timing generator control register
Timing
generator
Standby controller
System clocks
Clock generator control
High-frequency
clock oscillator
Low-frequency
clock oscillator
Clock
generator
System control registers

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TMP86FH09NG
tentative
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis-
abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjust-
ment in advance.
XOUTXIN
(Open)
XOUTXIN XTOUT
XTIN
(Open)
XTOUT
XTIN
(a) Crystal/Ceramic
resonator
(b) External oscillator (c) Crystal (d) External oscillator
High-frequency clock Low-frequency clock

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2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
2.2.2 Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
2.2.2.1 Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
Figure 2-4 Configuration of Timing Generator
Multi-
plexer
High-frequency
clock fc
Low-frequency
clock fs
Divider
SYSCK
fc/4
fc or fs Machine cycle countersMain system clock generator
1 21 432 87 109 1211 1413 1615
DV7CK
Multiplexer
Warm-up
controller
Watchdog
timer
AS
B
Y
S
B0
A0 Y0
B1
A1 Y1
5 6 17 18 19 20 21
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

Page 11
TMP86FH09NG
tentative
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2 Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
Figure 2-5 Machine Cycle
2.2.3 Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1 Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1) NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86FH09NG is placed in this mode after reset.
Timing Generator Control Register
TBTCR
(0036H)
76543210
(DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000)
DV7CK Selection of input to the 7th stage
of the divider
0: fc/28[Hz]
1: fs R/W
Main system clock
State
Machine cycle
S3S2S1S0 S3S2S1S0
1/fc or 1/fs [s]

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2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
(2) IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3) IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-
cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2 Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the low-
frequency oscillator should be turned on at the start of a program.
(1) NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
(2) SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hard-
ware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3) SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-fre-
quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

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TMP86FH09NG
tentative
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4) IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5) SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how-
ever, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releas-
ing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6) SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-
frequency clock.
(7) SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-
cessing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
2.2.3.3 STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.

Page 14
2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Operating Mode
Oscillator
CPU Core TBT Other
Peripherals
Machine Cycle
Time
High
Frequency
Low
Frequency
Single clock
RESET
Oscillation Stop
Reset Reset Reset
4/fc [s]NORMAL1 Operate
Operate Operate IDLE1
HaltIDLE0 Halt –
STOP Stop Halt
Dual clock
NORMAL2
Oscillation
Oscillation
Operate with
high frequency
Operate Operate
4/fc [s]
IDLE2 Halt
SLOW2 Operate with
low frequency
4/fs [s]
SLEEP2 Halt
SLOW1
Stop
Operate with
low frequency
SLEEP1
HaltSLEEP0 Halt –
STOP Stop Halt
Note 2
SYSCR2<XEN> = "1"
STOP pin input
STOP pin input
STOP pin input
Interrupt
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<SYSCK> = "1"
SYSCR2<XTEN> = "0"
SYSCR2<SYSCK> = "0"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
Interrupt
SYSCR2<IDLE> = "1"
SYSCR2<IDLE> = "1"
Interrupt
SYSCR2<TGHALT> = "1"
Reset release
NORMAL1
mode
IDLE0
mode
(a) Single-clock mode
IDLE1
mode
NORMAL2
mode
IDLE2
mode
SYSCR2<XTEN> = "1"
SLOW2
mode
SLEEP2
mode
SLOW1
mode
SLEEP1
mode
SLEEP0
mode
RESET
(b) Dual-clock mode
STOP
SYSCR2<TGHALT> = "1"
Note 2

Page 15
TMP86FH09NG
tentative
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
System Control Register 1
SYSCR176543210
(0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 000*)
STOP STOP mode start 0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode) R/W
RELM Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release R/W
RETM Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode R/W
OUTEN Port output during STOP mode 0: High impedance
1: Output kept R/W
WUT Warm-up time at releasing
STOP mode
Return to NORMAL mode Return to SLOW mode
R/W
000
010
100
110
3 x 216/fc
216/fc
3 x 214/fc
214/fc
3 x 213/fs
213/fs
3 x 26/fs
26/fs
System Control Register 2
SYSCR2
(0039H)
76543210
XEN XTEN SYSCK IDLE TGHALT (Initial value: 1000 *0**)
XEN High-frequency oscillator control 0: Turn off oscillation
1: Turn on oscillation
R/W
XTEN Low-frequency oscillator control 0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock moni-
tor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
R/W
TGHALT TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)

Page 16
2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
2.2.4 Operating Mode Control
2.2.4.1 STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to 2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to 2) for releasing
STOP mode in edge-sensitive mode.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to 2). However,
because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the
STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1) Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to 2 pin
input which is enabled by STOPCR. This mode is used for capacitor backup when the main power
supply is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5
to 2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately.
Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first
confirm that the STOP pin input is low or STOP5 to 2 input is high. The following two methods can
be used for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode
SSTOPH: TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level
JRS F, SSTOPH
DI ; IMF ←0
SET (SYSCR1). 7 ; Starts STOP mode

Page 17
TMP86FH09NG
tentative
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
(2) Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in appli-
cations where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP5 to 2 pin input for releasing STOP mode in edge-sensitive release mode.
Figure 2-8 Edge-sensitive Release Mode
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if
JRS F, SINT5 port P20 is at high
LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode.
DI ; IMF ←0
SET (SYSCR1). 7 ; Starts STOP mode
SINT5: RETI
Example :Starting STOP mode from NORMAL mode
DI ; IMF ←0
LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode
VIH
NORMAL
operation Warm up
STOP
operation
Confirm by program that the
STOP pin input is low and start
STOP mode. Always released if the STOP
pin input is high.
STOP pin
XOUT pin
STOP mode is released by the hardware.
NORMAL
operation
NORMAL
operation
NORMAL
operation
V
IH
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Warm up
STOP mode started
by the program.
STOP
operation
STOP
operation
STOP pin
XOUT pin

Page 18
2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low-
frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low-
frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the warm-up time has elapsed, normal operation resumes with the instruction follow-
ing the STOP mode start instruction.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Note 2: The CPU wait period for FLASH is shown in parentheses.
Table 2-1 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
WUT
Warm-up Time [ms]
Return to NORMAL Mode Return to SLOW Mode
00
01
10
11
12.288
4.096
3.072
1.024
750
250
5.85
1.95

Page 19
TMP86FH09NG
tentative
Figure 2-9 STOP Mode Start/Release
Instruction address a + 4
0
Instruction address a + 3
Turn on
Turn on
Warm up
0n
Halt
SET (SYSCR1). 7
Turn off
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
a + 6
a + 5
a + 4
a + 3
a + 2
n + 2 n + 3 n + 4
a + 3
n + 1
Instruction address a + 2
2
1
03
(b) STOP mode release
Count up
Turn off
Halt
Oscillator circuit Program counter Instruction execution Divider Main system clock Oscillator circuit STOP pin input Program counter Instruction execution Divider Main system clock

Page 20
2. Operational Description
2.2 System Clock Controller TMP86FH09NG
tentative
2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
Reset
Reset input
“0”
“1” (Interrupt release mode)
Yes
No
No
CPU and WDT are halted
Interrupt request
IMF
Interrupt processing
Normal
release mode
Yes
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
Execution of the instruc-
tion which follows the
IDLE1/2 and SLEEP1/2
modes start instruction