TENX TECHNOLOGY 82314BW User manual

TM59PA80
8 bit
Microcontroller
0tenx technology, inc.
Rev 1.2, 2007/03/06
TM59PA80
User’s Manual
tenx technology, inc.

UM-TM59PA80_E
1tenx technology, inc.
Rev 1.2, 2007/03/06
Contents
1. Overview .............................................................................................. 2
1-1. FEATURES .........................................................................................................2
1-2. Clock Scheme and Instruction Cycle.............................................................10
1-3. Addressing Mode.............................................................................................11
1-4. ALU and Working (W) Register.......................................................................12
1-5. STATUS Register .............................................................................................13
1-6. Interrupt............................................................................................................13
1-7. Reset.................................................................................................................14
1-8. Power-Down Mode ..........................................................................................15
1-9. Instruction Set .................................................................................................15
2. Control Registers ............................................................................ 29
3. 8-Bit Timer......................................................................................... 61
4. 8-Bit PWM........................................................................................... 65
5. Analog to Digital Converter.......................................................... 67
6. I/O Ports.............................................................................................. 69
7. LCD Controller.................................................................................. 75
8. Buzzer Out ......................................................................................... 80
9. Serial I/O............................................................................................. 82
10. Electrical Characteristics.......................................................... 86
11. Packaging Information................................................................ 92

UM-TM59PA80_E
2tenx technology, inc.
Rev 1.2, 2007/03/06
1. Overview
1-1. FEATURES
1. Memory
• 212-byte general purpose register include LCD-Buffer (RAM)
• 8Kx14 internal program memory (OTP ROM)
2. Oscillation Sources
• Crystal, Ceramic, Ext RC, SUB Clock
• CPU clock divider (1, 1/4, 1/8, 1/16)
3. Instruction Set
• 35 instructions
4. Instruction Execution Time
• 167 ns at 12 MHz fSYS (minimum)
5. Interrupts
• 15 interrupt sources with one vector / one level
6. I/O Ports
• Total 36 bit-programmable pins (44QFP)
• Total 34 bit-programmable pins (42SDIP)
7. Timers
• Two 8-bit timer/counter. Interval mode. (Timer0, 1)
Configurable as one 16-bit timer/counter.
• One Real-time and interval time measurement (Timer2)
8. PWM
• 8-bit PWM 1-ch (6-bit base + 2-bit extension)
9. Watchdog Timer
• 221 oscillator’s clock reset period
10. Buzzer Out
• Frequency Selectable Buzzer Output
11. LCD Controller/Driver
• 8 COM X 16 SEG
• 4 COM X 20 SEG
• 3 COM X 20 SEG

UM-TM59PA80_E
3tenx technology, inc.
Rev 1.2, 2007/03/06
12. A/D Converter
• 6 analog input channels
• 12.5μs conversion speed at 4MHz fADC clock
13. 8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• LSB-first or MSB-first transmission selectable
• Internal or external clock source
14. Low Voltage Detector (LVD)
• Voltage level detection
• Low Voltage Check to make system reset(LVR)
• VLVD = 2.3V/3.0V/3.9V
15. Operating Temperature Range
• -40°C to + 85°C
16. Operating Voltage Range
• 2.0 V to 5.5 V at 0.4 ~ 4.2 MHz
• 2.5 V to 5.5 V at 0.4 ~ 12 MHz
17. Package Type
• 44-pin QFP
• 44-pin LQFP
• 42-pin SDIP
• 40-pin DIP

UM-TM59PA80_E
4tenx technology, inc.
Rev 1.2, 2007/03/06
8K(14Bit)
Program
Memory
192 Byte
SRAM
Port A
CORE
Port B
10 bit ADC
6 ch
8-bit Timer0
WDT Timer
OSC
External RC
Port I/O
Interrupt Control
20 Byte
LCD
Buffer
8-bit Timer1
8-bit Timer2
SIO LCD
Controller
Port C
Port G
Port F
Port E
Port D
Buzzer
Out
8-bit
PWM
< Figure 1-1. Block Diagram >

UM-TM59PA80_E
5tenx technology, inc.
Rev 1.2, 2007/03/06
< Figure 1-2. Pin Assignment Diagram (44-Pin QFP Package) >

UM-TM59PA80_E
6tenx technology, inc.
Rev 1.2, 2007/03/06
< Figure 1-3. Pin Assignment Diagram (44-Pin LQFP Package) >

UM-TM59PA80_E
7tenx technology, inc.
Rev 1.2, 2007/03/06
42 SDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
COM0/PG.3
T0OUT/INT0/PA.0
T0CLK/INT1/PA.1
CLO/INT2/PA.2
BUZ/INT3/PA.3
AD0/INT4/PB.0
AD1/INT5/PB.1
AD2/INT6/PB.2
AD3/INT7/PB.3
VDD
VSS
XOUT
XIN
nTEST
XTIN
XTOUT
nRESET
PWM0/PC.3
SI/PC.2
SO/SEG0/PC.1
SCLK/SEG1/PC.0
PG.2/COM1
PG.1/COM2
PG.0/COM3
PF.7/COM4/SEG19
PF.6/COM5/SEG18
PF.5/COM6/SEG17
PF.4/COM7/SEG16
PF.3/SEG15
PF.2/SEG14
PF.1/SEG13
PF.0/SEG12
PE.7/SEG11
PE.6/SEG10
PE.5/SEG9
PE.4/SEG8
PE.3/SEG7
PE.2/SEG6
PE.1/SEG5
PE.0/SEG4
PD.0/SEG3/INT9
PD.1/SEG2/INT8
< Figure 1-4. Pin Assignment Diagram (42-Pin SDIP Package) >

UM-TM59PA80_E
8tenx technology, inc.
Rev 1.2, 2007/03/06
< Figure 1-5. Pin Assignment Diagram (40-Pin DIP Package) >

UM-TM59PA80_E
9tenx technology, inc.
Rev 1.2, 2007/03/06
Pin Name I/O Pin Description Shared Function
VDD, VSS P Power input pins for internal power block -
XIN, XOUT −Main oscillator pins for main clock -
XTIN, XTOUT −Sub oscillator pins for sub clock -
nTEST −Chip test input pin. Hold VDD when the device is operating -
nRESET −Reset signal input pin. Schmitt trigger input with internal pull-
up resistor. -
PA.0—PA.5 I/O
Schmitt trigger input, Push-pull Output, Open-Drain Output,
External Interrupt 0-3, Timer 0 Output, Timer 0 external
clock input, Clock Output, Buzzer Out, ADC4-5
INT0-3, ADC4-5,
T0CLK, T0OUT,
Buzzer, CLO
PB.0—PB.3 I/O
Schmitt trigger input, Push-pull Output, Open-Drain Output,
ADC0-3, External Interrupt 4-7 ADC0-3, INT4-7
PC.0—PC.3 I/O
Schmitt trigger input, Push-pull output, Open-Drain output,
SEG0-1, SCLK, SO, SI, PWM0
SCLK, SO,
SEG0-1, SI,
PWM0
PD.0, PD.1 I/O Schmitt trigger input, Push-pull output, Open-Drain output,
External Interrupt 8-9, SEG2-3 INT8-9, SEG2-3
PE.0—PE.7 I/O
Schmitt trigger Input, Push-pull output, Open-Drain output,
SEG4-11, Input mode with pull-up SEG4-11
PF.0—PF.7 I/O
Schmitt trigger Input, Push-pull output, Open-Drain output,
SEG12-19, COM4-7, Input mode with pull-up
SEG12-19,
COM4-7
PG.0—PG.3 I/O
Schmitt trigger Input, Push-pull output, Open-Drain output,
COM0-3, Input mode with pull-up COM0-3
CLO O System clock output port PA.2
INT0-INT9 I External interrupt input port PA.0-3, PB.0-3,
PD.0-1
PWM0 O 8-Bit high speed PWM output PC.3
T0OUT O Timer0 match output PA.0
ADC0-ADC5 I A/D converter input PB.0-3, PA.4-5
<Table 1-1. PIN Description> < I: Input; O: Output; I/O: Bi-direction; P: Power >

UM-TM59PA80_E
10 tenx technology, inc.
Rev 1.2, 2007/03/06
1-2. Clock Scheme and Instruction Cycle
The TM59PA80 has two oscillator circuits, main clock and sub clock circuit.
The notation of clock source is as following:
fOSC : Main Oscillator clock (XIN, XOUT)
fSUB : Sub Oscillator clock (XTIN, XTOUT)
fSYS : System Clock which is selected by OSCCON (fOSC or fSUB)
fCPU : CPU Clock. Divided fSYS by CLKCON (/1, /4, /8, /16)
1. OSCILLATOR CONTROL REGISTER (OSCCON)
The oscillator control register (OSCCON) has the following functions:
— System clock selection and check clock switching status
— Main oscillator start/stop control
— Sub oscillator start/stop control
— Idle mode control
OSCCON.1 register settings select Main clock or Sub clock as system clock. After a
reset, Main clock is selected for system clock and it can be switched to Sub clock
by user program. System Clock switching is described in section ‘Switching CPU
Clock’. The main oscillator can be stopped or run by setting OSCCON.3 and the
sub oscillator can be stopped or run by setting OSCCON.2.
Idle mode control is described in section in 1.8 Power-Down mode.
2. SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register (CLKCON) has the following functions:
Oscillator frequency divider
After a reset, the main oscillator is activated, and the fSYS/16 (the slowest clock
speed) is selected as the CPU clock. If necessary, you can then increase the CPU
clock speed to fSYS/1, fSYS/4, or fSYS/8 by setting the CLKCON.
3. SWITCHING THE CPU CLOCK
The oscillator control register (OSCCON) determine whether a main or a sub clock
is selected as the CPU clock, and also how this frequency is to be divided by setting
CLKCON. This makes it possible to switch dynamically between main and sub
clocks and to modify operating frequencies.
OSCCON.1 selects the main clock (fOSC) or the sub clock (fSUB) for the system clock.
OSCCON.3 control main clock oscillation, and OSCCON.2 control sub clock
oscillation. OSCCON.4 shows clock switching status.
For example, you are using the default system clock (fOSC) and you want to switch
from the main clock (fOSC) to a sub clock (fSUB) and to stop the main clock. To do
this, the following steps must be taken to switch from a sub clock to the main clock.

UM-TM59PA80_E
11 tenx technology, inc.
Rev 1.2, 2007/03/06
Step-1: If sub clock is disabled, set OSCCON.2 = 0 to enable sub clock and
wait oscillation stabilization time.
Step-2: Set OSCCON.1 = 1 to select sub clock (fSUB) as system clock (fSYS).
Step-3: Check OSCCON.4 is set to ‘1’ (switched to sub clock)
Step-4: If you want to stop main clock, set OSCCON.3 = 1.
4. INSTRUCTION CYCLE
The CPU clock input is internally divided by two to generate Q1 state and Q2 state
for each instruction cycle. The Programming Counter (PC) is updated at Q1 and the
instruction is fetched from program ROM and latched into the instruction register in
Q2. It is then decoded and executed during the following Q1-Q2 cycle.
< Figure 1-6. Clock/Instruction cycle and pipeline >
Branch instructions take two cycles since the fetch instruction is ‘flushed’ from the
pipeline, while the new instruction is being fetched and then executed.
1-3. Addressing Mode
The Programming Counter is 13-bit wide capable of addressing a 8K x 14 program
ROM. As a program instruction is executed, the PC will contain the address of the
next program instruction to be executed. The PC value is normally increased by one
except the followings. The reset Vector (000h) and the Interrupt Vector (001h) are
provided for PC initialization and Interrupt. For CALL/GOTO instructions, PC loads
its lower 12 bits from instruction word and the MSB from STATUS’s bit 6. For
RET/RETI/RETLW instructions, PC retrieves its content from the top level STACK.
For the other instructions updating PC[7:0], the PC[12:8] keeps unchanged. The
STACK is 13-bit wide and 6-level in depth. The CALL instruction and Hardware
interrupt will push STACK level in order, while the RET/RETI/RETLW instruction
pops the STACK level in order.

UM-TM59PA80_E
12 tenx technology, inc.
Rev 1.2, 2007/03/06
The data memory is partitioned into three banks, which contain the General
Purpose Data Memory, LCD Data Buffer and the Special Function Registers (SFR).
STAT.5-4 is the bank select bits. Each bank extends up to 7Fh (128 bytes). The
lower locations of each bank (00h-1Fh) are reserved for the SFR. Above the SFR
are General Purpose Data Memory, implemented as static RAM. Some SFR area is
mirrored in all banks for code reduction and quicker access. The first half of RAM
(00h −3Fh) is bit-addressable.
Data memory can be addressed directly or indirectly. Indirect Addressing is made
by INDF register. The INDF register is not a physical register. Addressing INDF
actually addresses the register whose address is contained in the FSR register
(FSR is a pointer). Reading INDF itself indirectly (FSR=0) will produce 00h. Writing
to the INDF register indirectly results in a no-operation.
Program Memory
0000 Reset Vector
0001 Interrupt Vector
0FFF
Program ROM Page0
1000
1FFF
Program ROM Page1
< Figure 1-7. Address space >
1-4. ALU and Working (W) Register
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical
operations. In two-operand instructions, typically one operand is the W register,
which is an 8-bit non-addressable register used for ALU operations. The other
operand is either a file register or an immediate constant. In single operand
instructions, the operand is either W register or a file register.
Depending on the instruction executed, the ALU may affect the values of Carry(C),
Digit Carry (DC), and Zero (Z) Flags in the STAT register. The C and DC flags
operate as a /Borrow and /Digit Borrow, respectively, in subtraction.
Data Memory
Bank0 Bank1 Bank2
00
1F
Special Function Registers
Bit addressable
STAT.54 = 10
LCD Buffer
20
3F
STAT.54=00
Bit
addressable
STAT.54=01
Bit
addressable
40
7F
RAM
STAT.54=00
RAM
STAT.54=01

UM-TM59PA80_E
13 tenx technology, inc.
Rev 1.2, 2007/03/06
1-5. STATUS Register
This register contains the arithmetic status of ALU, the page select for Program
ROM and RAM and global interrupt enable/disable control. The STATUS register
can be the destination for any instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects the Z, DC or C bits, then the
write to these three bits is disabled. These bits are set or cleared according to the
device logic. It is recommended, therefore, that only BCF, BSF and MOVWF
instructions be used to alter the STATUS Register because these instructions do
not affect those bits.
1-6. Interrupt
The TM59PA80 has 1 level, 1 vector and 15 sources. Each interrupt source has its
own enable control bit. An interrupt event will set its individual flag. Because
TM59PA80 has only 1 vector, there is not a interrupt priority register. The interrupt
priority is determined by F/W.
Interrupt
Vector
Interrupt Pending
i-Flag
Interrupt
Enable
Interrupt
Source
< Figure 1-8. Interrupt Function Diagram >
If the corresponding interrupt enable bit has been set, it would trigger CPU to
service the interrupt. CPU accepts interrupt in the end of current executed
instruction cycle. In the mean while, A “CALL 0001” instruction is inserted to CPU,
and the i-flag is set to prevent recursive interrupt nesting. The i-flag is cleared in the
instruction after the “RETI” instruction. That is, at least one instruction in main
program is executed before service the pending interrupt. The interrupt event is
edge trigged. F/W must clear the interrupt event register while serves the interrupt
routine.

UM-TM59PA80_E
14 tenx technology, inc.
Rev 1.2, 2007/03/06
1-7. Reset
The TM59PA80 can be reset in four ways:
zPower-On-Reset
zHardware Reset by nRESET pin
zLow Voltage Reset (LVR)
zWatchdog Reset
LVR
Watchdog
RESET
Internal
RESET
nRESET
< Figure 1-9. Reset Circuit Diagram >
The nRESET pin must be held to Low level for a minimum time interval after the
power supply comes within tolerance in order to allow time for internal CPU clock
oscillation to stabilize. The minimum required oscillation stabilization time for a reset
is approximately 2.5 ms (fOSC = 10 MHz). When the CPU is operating in normal
state (VDD and nRESET at High level), if the signal at the nRESET pin is forced Low
then the reset operation starts. All system and peripheral control registers are then
set to their default hardware reset values.
The Low Voltage Reset features static reset when supply voltage is below a
reference value. LVDCON is used to select reference voltage, LVD enable control,
reset enable control and check voltage level status.
The Watchdog Timer is disabled after reset. F/W can use the CLRWDT instruction
to clear and enable the Watchdog Timer. If once enabled, the Watchdog Timer
overflow and generate a chip reset signal if no CLRWDT executed in a period of 221
oscillator’s cycle (256 msec for 8.192MHz crystal). The Watchdog Timer does not
work in Power-down mode to provide wake-up function. It is only designed to
prevent F/W goes into endless loop.

UM-TM59PA80_E
15 tenx technology, inc.
Rev 1.2, 2007/03/06
1-8. Power-Down Mode
The TM59PA80 has two kind of Power-down mode: STOP mode and IDLE mode.
The STOP mode is activated by SLEEP instruction. During the STOP mode, the
selected system clock (fSYS) oscillation stops to minimize power consumption and all
the peripherals which the same oscillator is selected as clock source are not
working. Therefore, The Power down mode can be terminated by reset, enabled
external Interrupts and timers which the other oscillator is selected as a clock
source. When the Power down mode is released, the clock circuit requires
oscillation stabilization time also. The STOPCON register must be set to
‘10100101b’ before enter STOP mode. If the STOPCON is not set to ‘10100101b’,
the SLEEP instruction cause system reset. Idle mode is activated by OSCCON.0.
During the Idle mode, only the internal CPU clock is stops. Therefore, Idle mode
can be terminated by reset and all of interrupt.
1-9. Instruction Set
Each instruction is a 14-bit word divided into an OPCODE, which specified the
instruction type, and one or more operands, which further specify the operation of
the instruction. The instructions can be categorized as byte-oriented, bit-oriented
and literal operations list in the following table. For byte-oriented instructions, “f”
represents address designator and “d” represents destination designator. The
address designator is used to specify which address in Program memory is to be
used by the instruction. The destination designator specifies where the result of the
operation is to be placed. If “d” is “0”, the result is placed in the W register. If “d” is
“1”, the result is placed in the address specified in the instruction. For bit-oriented
instructions, “b” represents a bit field designator, which selects the number of the bit
affected by the operation, while “f” represents the address designator. For literal
operations, “k” represents the literal or constant value.
Field Description
f Register File Address
b Bit address
k Literal. Constant data or label
d Destination selection field. 0 : Working register 1 : Register file
W Working Register
Z Aero Flag
C Carry Flag
DC Decimal Carry Flag
PC Program Counter
TOS Top Of Stack
GIE Global Interrupt Enable Flag (i-Flag)
[ ] Option Field
( ) Contents
. Bit Field
←Assign direction
< List 1-1 OP-CODE Field Description >

UM-TM59PA80_E
16 tenx technology, inc.
Rev 1.2, 2007/03/06
Mnemonic Op Code Cycles Flag Affect Description
Byte-Oriented File Register Instruction
ADDWF f,d 00 0111 dfff ffff 1 C,DC,Z Add W and "f"
ANDWF f,d 00 0101 dfff ffff 1 Z AND W with "f"
CLRF f 00 0001 1fff ffff 1 Z Clear "f"
CLRW 00 0001 0100 0000 1 Z Clear W
COMF f,d 00 1001 dfff ffff 1 Z Complement "f"
DECF f,d 00 0011 dfff ffff 1 Z Decrement "f"
DECFSZ f,d 00 1011 dfff ffff 1 or 2 - Decrement "f", skip if zero
INCF f,d 00 1010 dfff ffff 1 Z Increment "f"
INCFSZ f,d 00 1111 dfff ffff 1 or 2 - Increment "f", skip if zero
IORWF f,d 00 0100 dfff ffff 1 Z OR W with "f"
MOVFW f 00 1000 0fff ffff 1 - Move "f" to "w"
MOVWF f 00 0000 1fff ffff 1 - Move W to "f"
RLF f,d 00 1101 dfff ffff 1 C Rotate left "f" through carry
RRF f,d 00 1100 dfff ffff 1 C Rotate right "f" through carry
SUBWF f,d 00 0010 dfff ffff 1 C,DC,Z Subtract W from "f"
SWAPF f,d 00 1110 dfff ffff 1 - Swap nibble of "f"
TESTZ f 00 1000 1fff ffff 1 Z Test if "f" is zero
XORWF f,d 00 0110 dfff ffff 1 Z XOR W with "f"
Bit-Oriented File Register Instruction
BCF f,b 01 000b bbff ffff 1 - Clear "b" bit of "f"
BSF f,b 01 001b bbff ffff 1 - Set "b" bit of "f"
BTFSC f,b 01 010b bbff ffff 1 or 2 - Test "b" bit of "f", skip if clear
BTFSS f,b 01 011b bbff ffff 1 or 2 - Test "b" bit of "f", skip if set
Literal and Control Instruction
ADDLW k 01 1100 kkkk kkkk 1 C,DC,Z Add Literal "k" and W
ANDLW k 01 1011 kkkk kkkk 1 Z AND Literal "k" with W
CALL k 10 kkkk kkkk kkkk 2 - Call subroutine "k"
CLRWDT 00 0000 1000 1001 1 - Clear and enable Watch Dog Timer
GOTO k 11 kkkk kkkk kkkk 2 - Jump to branch "k"
IORLW k 01 1010 kkkk kkkk 1 Z OR Literal "k" with W
MOVLW k 01 1001 kkkk kkkk 1 - Move Literal "k" to W
NOP 00 0000 0000 0000 1 - No operation
RET 00 0000 0100 0000 2 - Return from Subroutine
RETI 00 0000 0110 0000 2 - Return from interrupt
RETLW k 01 1000 kkkk kkkk 2 - Return with Literal "k" in W
SLEEP 00 0000 1000 1010 1 -
Enter STOP mode, Clock oscillation
stops
XORLW k 01 1111 kkkk kkkk 1 Z XOR Literal "k" with W
< List 1-2 Instruction Summary >

UM-TM59PA80_E
17 tenx technology, inc.
Rev 1.2, 2007/03/06
ADDLW Add Literal “k” and W
Syntax ADDLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) + k
Status Affected C, DC, Z
OP-Code 01 1100 kkkk kkkk
Description The contents of the W register are added to the eight-bit literal ’k’ and
the result is placed in the W register.
Cycle 1
Example ADDLW 0x15 B : W = 0x10
A : W = 0x25
ADDWF Add W and ‘f’
Syntax ADDWF f [,d]
Operands f : 00h ~ 7Fh d : 0, 1
Operation (Destination) ←(W) + (f)
Status Affected C, DC, Z
OP-Code 00 0111 dfff ffff
Description Add the contents of the W register with register ‘f’. If ‘d’ is 0, the result
is stored in the W register. If ‘d’ is 1, the result is stored back in
register ‘f’.
Cycle 1
Example ADDWF FSR, 0 B : W = 0x17, FSR = 0xC2
A : W = 0xD9, FSR = 0xC2
ANDLW Logical AND Literal "k" with W
Syntax ANDLW k
Operands k : 00h ~ FFh
Operation (W) ←(W) ‘AND’ (f)
Status Affected Z
OP-Code 01 1011 kkkk kkkk
Description The contents of W register are AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Cycle 1
Example ANDLW 0x5F B : W = 0xA3
A : W = 0x03

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18 tenx technology, inc.
Rev 1.2, 2007/03/06
ANDWF AND W with f
Syntax AND f [,d]
Operands f : 00h ~ 7Fh d : 0, 1
Operation (Destination) ←(W) ‘AND’ (f)
Status Affected Z
OP-Code 00 0101 dfff ffff
Description AND the W register with register ’f’. If ’d’ is 0, the result is stored in the
W register. If ’d’ is 1, the result is stored back in register ’f’.
Cycle 1
Example ANDWF FSR, 1 B : W = 0x17, FSR = 0xC2
A : W = 0x17, FSR = 0x02
BCF Clear "b" bit of "f"
Syntax BCF f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation (f.b) ←0
Status Affected -
OP-Code 01 000b bbff ffff
Description Bit ’b’ in register ’f’ is cleared.
Cycle 1
Example BCF FLAG_REG, 7 B : FLAG_REG = 0xC7
A : FLAG_REG = 0x47
BSF Set "b" bit of "f"
Syntax BCF f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation (f.b) ←1
Status Affected -
OP-Code 01 001b bbff ffff
Description Bit ’b’ in register ’f’ is set.
Cycle 1
Example BSF FLAG_REG, 7 B : FLAG_REG = 0x0A
A : FLAG_REG = 0x8A

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Rev 1.2, 2007/03/06
BTFSC Test ‘b’ bit of ‘f’, skip if clear(0)
Syntax BTFSC f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation Skip next instruction if (f.b) = 0
Status Affected -
OP-Code 01 010b bbff ffff
Description If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is executed. If bit
‘b’ in register ‘f’ is ‘0’, then the next instruction is discarded, and a NO
P is executed instead, making this a 2nd cycle instruction.
Cycle 1 or 2
Example LABEL1 BTFSC FLAG, 1
TRUE GOTO SUB1
FALSE ...
B : PC = LABEL1
A : if FLAG.1 = 0, PC = FALSE
if FLAG.1 = 1, PC = TRUE
BTFSS Test "b" bit of "f", skip if set(1)
Syntax BTFSC f [,b]
Operands f : 00h ~ 3Fh b : 0 ~ 7
Operation Skip next instruction if (f.b) = 1
Status Affected -
OP-Code 01 011b bbff ffff
Description If bit ’b’ in register ’f’ is ’0’, then the next instruction is executed.
If bit ’b’ in register ’f’ is ’1’, then the next instruction is discarded,
and a NOP is executed instead, making this a 2nd cycle instruction.
Cycle
Example LABEL1 BTFSS FLAG, 1
TRUE GOTO SUB1
FALSE ...
B : PC = LABEL1
A : if FLAG.1 = 0, PC = TRUE
if FLAG.1 = 1, PC = FALSE
CALL Call subroutine "k"
Syntax CALL k
Operands K : 00h ~ FFFh
Operation Operation: TOS ←(PC)+ 1, PC.11~0 ←k
Status Affected -
OP-Code 10 kkkk kkkk kkkk
Description Call Subroutine. First, return address (PC+1) is pushed onto the
stack. The eleven-bit immediate address is loaded into PC bits
<11:0>. CALL is a two-cycle instruction.
Cycle 2
Example LABEL1 CALL SUB1 B : PC = LABEL1
A : PC = SUB1,
TOS = LABEL1+1