Texas Instruments Serial Programming Adapter MSP430 User manual

User’s Guide
MSP430™ Flash Devices Bootloader (BSL)
ABSTRACT
The MSP430™ bootloader (BSL) (formerly known as the bootstrap loader) allows users to communicate with
embedded memory in the MSP430 microcontroller (MCU) during the prototyping phase, final production, and in
service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as
required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal
processors (DSPs) that automatically load program code (and data) from external memory to the internal
memory of the DSP.
To use the bootloader, a specific BSL entry sequence must be applied. An added sequence of commands
initiates the desired function. A bootloading session can be exited by continuing operation at a defined user
program address or by the reset condition.
If the device is secured by disabling JTAG, it is still possible to use the BSL. Access to the MSP430 MCU
memory through the BSL is protected against misuse by the BSL password. The BSL password is equal to the
content of the interrupt vector table on the device.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Supplementary Online Information.....................................................................................................................................3
1.2 Overview of BSL Features................................................................................................................................................. 4
1.3 BSL Invocation................................................................................................................................................................... 5
1.4 UART Protocol................................................................................................................................................................... 7
1.5 USB Protocol......................................................................................................................................................................7
2 Bootloader Protocol – 1xx, 2xx, and 4xx Families.............................................................................................................. 8
2.1 Synchronization Sequence................................................................................................................................................ 8
2.2 Commands.........................................................................................................................................................................8
2.3 Programming Flow............................................................................................................................................................. 8
2.4 Data Frame........................................................................................................................................................................ 9
2.5 Loadable BSL...................................................................................................................................................................14
2.6 Exiting the BSL.................................................................................................................................................................15
2.7 Password Protection........................................................................................................................................................ 15
2.8 Code Protection Fuse...................................................................................................................................................... 15
2.9 BSL Internal Settings and Resources.............................................................................................................................. 16
3 Bootloader Protocol – F5xx and F6xx Families................................................................................................................. 19
3.1 BSL Data Packet..............................................................................................................................................................19
3.2 UART Peripheral Interface (PI)........................................................................................................................................ 19
3.3 I2C Peripheral Interface....................................................................................................................................................20
3.4 USB Peripheral Interface................................................................................................................................................. 22
3.5 BSL Core Command Structure........................................................................................................................................ 22
3.6 BSL Security.................................................................................................................................................................... 24
3.7 BSL Core Responses.......................................................................................................................................................25
3.8 BSL Public Functions and Z-Area.................................................................................................................................... 27
4 Bootloader Hardware............................................................................................................................................................29
4.1 Hardware Description.......................................................................................................................................................29
5 Differences Between Devices and Bootloader Versions.................................................................................................. 33
5.1 1xx, 2xx, and 4xx BSL Versions.......................................................................................................................................33
5.2 Special Consideration for ROM BSL Version 1.10...........................................................................................................40
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5.3 1xx, 2xx, and 4xx BSL Known Issues.............................................................................................................................. 41
5.4 Special Note on the MSP430F14x Device Family BSL....................................................................................................41
5.5 F5xx and F6xx Flash-Based BSL Versions......................................................................................................................42
6 Bootloader PCB Layout Suggestion...................................................................................................................................48
7 Revision History................................................................................................................................................................... 51
List of Figures
Figure 1-1. Standard RESET Sequence......................................................................................................................................5
Figure 1-2. BSL Entry Sequence at Shared JTAG Pins...............................................................................................................5
Figure 1-3. BSL Entry Sequence at Dedicated JTAG Pins..........................................................................................................6
Figure 3-1. Basic Protocol - Byte Level ACK............................................................................................................................. 20
Figure 3-2. Byte Level ACK....................................................................................................................................................... 21
Figure 4-1. Bootloader Interface Schematic.............................................................................................................................. 29
Figure 6-1. Universal BSL Interface PCB Layout, Top...............................................................................................................48
Figure 6-2. Universal BSL Interface PCB Layout, Bottom......................................................................................................... 48
Figure 6-3. Universal BSL Interface Component Placement..................................................................................................... 49
Figure 6-4. Universal BSL Interface Component Placement..................................................................................................... 50
Trademarks
MSP430™ and TI E2E™ are trademarks of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
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1 Introduction
The bootloader provides a method to program the flash memory during MSP430 project development and
updates. It can be activated by a utility that sends commands using the UART protocol. The BSL enables the
user to control the activity of the MSP430 MCU and to exchange data using a personal computer or other
device.
To avoid accidental overwriting of the BSL code, this code is stored in a secure memory location, either ROM or
specially protected flash. To prevent unwanted source readout, any BSL command that directly or indirectly
allows data reading is password protected.
To invoke the bootloader, a BSL entry sequence must be applied to dedicated pins. After that, a synchronization
character, followed by the data frame of a specific command, initiates the desired function.
1.1 Supplementary Online Information
As a compliment to this document, visit Bootloader (BSL) for MSP low-power microcontrollers. This page
contains links to additional BSL user's guides, source code, firmware images, and the BSL scripter with
documentation and code examples.
Additional support is provided by the TI E2E™ support forums.
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1.2 Overview of BSL Features
Table 1-1 summarizes the BSL features of the MSP430 MCUs, organized by device family.
Table 1-1. BSL Overview
MSP430 MSP432
F20xx,
G2xx0,
G2xx1,
G2xx2,
I20xx
F1xx,
F2xx,
F4xx,
G2xx3
F5xx, F6xx(1) FR5xx, FR6xx FR231x,
FR242x,
FR243x
FR25xx,
FR263x
FR215x,
FR235x,
FR247x,
FR267x
FR20xx,
FR21xx,
FR41xx
P4xx
Non-
USB USB Factory
Crypto-
Boot-
loader(5)
General
BSL memory type No BSL ROM Flash(2) Flash(2) ROM FRAM ROM ROM ROM Flash(2)
BSL memory size N/A 1 KB 2 KB 2 KB 2 KB 4 KB 3 KB 3 KB 1 KB 8 KB
Peripheral configured by TLV ✔ ✔ ✔ ✔
User configuration ✔ ✔
UART ✔✔ ✔✔✔✔✔✔
I2C✔ ✔ ✔ ✔ ✔ ✔
SPI ✔
USB ✔
Protocol
'1xx, 2xx, 4xx' protocol ✔
'5xx, 6xx' protocol ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔
Invoke mechanism
Entry
sequence on
I/Os
Sequence on TEST/RST ✔✔ ✔✔✔✔✔
PUR pin tied to VUSB ✔
Sequence on defined I/O ✔ ✔
Empty reset vector invokes BSL ✔ ✔ ✔ ✔ ✔
Calling BSL from software application ✔✔✔✔✔✔✔✔✔
Invalid or incomplete application ✔
Tools Support
Hardware
MSP-BSL 'Rocket' ✔✔ ✔✔✔✔✔✔
MSP-FET ✔ ✔ ✔ ✔ ✔ ✔ ✔(3)
USB cable ✔
USB-to-Serial
Converter(4) ✔
Software(5)
BSL Scripter ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔
BSLDEMO ✔
MSPBSL library ✔UART
only ✔UART only ✔
Security
Password protection 32 byte 32 byte(6) 32 byte 32 byte 32 byte 32 byte 32 byte 256 byte
Mass erase on incorrect password(7) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔
Completely disable the BSL using
signature or erasing the BSL ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔
BSL payload encryption ✔ ✔(8)
Update of IP protected regions through
boot code ✔
Authenticated encryption ✔
Additional security ✔(9)
(1) Refer to the device-specific data sheet for the available TI BSL protocol on these devices. TI provides a specific BSL protocol for each
flash device.
(2) BSL in flash memory allows to replace the BSL with a custom version.
(3) MSP-FET supports UART and I2C BSL communication only.
(4) The USB-to-Serial Converter is compatible with BSLDEMO. The invocation signal is generated on the DTR pin for the RESET pin, and
on the RTS pin for the TEST pin.
(5) All BSL software collateral (application, examples, source code, and firmware images) is available in the BSL tool folder.
The MSP430 USB developers package includes additional USB BSL sample applications.
(6) F543x (non A) has a 16-byte password.
(7) Some devices can disable mass erase on incorrect password. See the device family user's guide.
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(8) The decryption of the payload is performed by the device bootcode.
(9) Firmware validation through CRC.
1.3 BSL Invocation
1.3.1 Hardware BSL Invocation
1.3.1.1 MSP430 Devices With Shared JTAG Pins
Applying an appropriate entry sequence on the RST/NMI and TEST pins forces the MSP430 MCU to start
program execution at the BSL RESET vector instead of at the RESET vector located at address FFFEh.
If the application interfaces with a computer UART, these two pins can be driven by the DTR and RTS signals of
the serial communication port (RS232) after passing level shifters. Detailed descriptions of the hardware and
related considerations can be found in Section 4. The normal user reset vector at FFFEh is used if TEST is kept
low while RST/NMI rises from low to high (standard method, see Figure 1-1).
RST DTR/NMI ( )
TEST ( )RTS
User Program Starts
Figure 1-1. Standard RESET Sequence
The BSL program execution starts when the TEST pin has received a minimum of two rising edges (low-to-high
transitions) and if TEST is high while RST/NMI rises from low to high (BSL entry method, see Figure 1-2). This
level transition triggering improves BSL start-up reliability. The first high level of the TEST pin must be at least
tSBW, En (see device-specific data sheet for tSBW, En parameter).
Bootloader Starts
RST DTR/NMI ( )
TEST ( )RTS
tSBW,en
Figure 1-2. BSL Entry Sequence at Shared JTAG Pins
Note
For the MSP430F522x and MSP430F521x split-rail devices with DVIO supply, the entry sequence is
applied on the RST/NMI and BSLEN pins. For pin information, refer to the device-specific data sheet.
For additional information, refer to the bootloader section in Designing With MSP430F522x and
MSP430F521x Devices.
Note
The recommended minimum time for pin states is 250 ns. See the device-specific errata for any
differences, because some 5xx and 6xx device revisions require specific entry sequences.
The TEST signal is normally used to switch the port pins between their application function and the JTAG
function. In devices with BSL functionality, the TEST and RST/NMI pins are also used to invoke the BSL. To
invoke the BSL, the RST/NMI pin must be configured as RST and must be kept low while pulling the TEST pin
high and while applying the next two edges (falling and rising) on the TEST pin. The BSL is started after the
TEST pin is held low after the RST/NMI pin is released (see Figure 1-2).
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1.3.1.1.1 Factors That Prevent BSL Invocation With Shared JTAG Pins
The BSL is not started by the BSL RESET vector if:
• There are fewer than two rising edges at the TEST pin while RST/NMI is low.
• The TEST pin does not stay high after the TEST pin second rising edge when RST/NMI rises from low to
high.
• JTAG has control over the MSP430 MCU resources.
• The supply voltage, VCC, drops below its threshold, and a power-on reset (POR) is executed.
• The RST/NMI pin is configured for NMI functionality (the NMI bit is set).
• If the TCK and TMS pins are left floating, the device can unintentionally enter JTAG mode. To avoid this
issue, apply the recommended external termination. Add a 47-kΩ pullup resistor and a 1-nF pulldown
capacitor on TCK and TMS. Stronger termination might be needed depending on noise in the system.
1.3.1.2 MSP430 Flash Devices With Dedicated JTAG Pins
Devices with dedicated JTAG pins use the TCK pin instead of the TEST pin.
The BSL program execution starts whenever the TCK pin has received a minimum of two falling edges and TCK
is low while RST/NMI rises from low to high (BSL entry method, see Figure 1-3). This level transition triggering
improves BSL start-up reliability.
RST DTR/NMI ( )
TCK ( )RTS
Bootloader Starts
Figure 1-3. BSL Entry Sequence at Dedicated JTAG Pins
Note
The recommended minimum time for pin states is 250 ns. See the device-specific errata for any
differences, because some 5xx and 6xx device revisions have specific entry sequence requirements.
1.3.1.2.1 Factors That Prevent BSL Invocation With Dedicated JTAG Pins
The BSL is not started by the BSL RESET vector if:
• There are fewer than two falling edges at the TCK pin while RST/NMI is low.
• TCK is high if RST/NMI rises from low to high.
• JTAG has control over the MSP430 MCU resources.
• The supply voltage, VCC, drops below its threshold, and a power-on reset (POR) is executed.
• The RST/NMI pin is configured for NMI functionality (the NMI bit is set).
1.3.1.3 Devices With USB
Devices with USB are invoked when either of the following two conditions are met while the device is powered
by VBUS:
• The device is powered up by USB and the reset vector is blank.
• The device powers up with the PUR pin tied to VUSB.
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1.3.2 Software BSL Invocation
To invoke the BSL from a running application, set the program counter to the address where the BSL is located.
For the MSP430F5xx and MSP430F6xx devices, the BSL is in memory location 0x1000. For the MSP430x1xx,
MSP430x2xx, and MSP430x4xx devices, see Section 5.
When the BSL runs, the stack is always reset, and RAM is cleared. Interrupts are not disabled by the BSL, so
the application must disable interrupts before invoking the BSL. TI recommends clearing the configuration of any
module registers that are used in the BSL application, because the configuration for the external application can
interrupt the BSL application and cause unexpected behavior. One example is that in the USB-enabled MCUs
with an USB BSL, the Timer_B module is used to identify the frequency of the high-frequency crystal. If Timer_B
is also used in the external application and is not cleared before jumping to the BSL application, unexpected
behavior can occur.
The location 0x1000 can be called as a C function, as in the following example code:
__disable_interrupt(); // disable interrupts
((void ( * )())0x1000)(); // jump to BSL
1.4 UART Protocol
The UART protocol applied here is defined as:
• Baud rate is fixed to 9600 baud in half-duplex mode (one sender at a time).
• Start bit, 8 data bits (LSB first), an even parity bit, 1 stop bit.
• Handshake is performed by an acknowledge character.
• Minimum time delay before sending new characters after characters have been received from the MSP430
BSL: 1.2 ms
Note
Applying baud rates other than 9600 baud at initialization results in communication problems or
violates the flash memory write timing specification. The flash memory can be extensively stressed or
can react with unreliable program or erase operations.
1.5 USB Protocol
The USB protocol applied here is defined as:
• HID protocol with one input endpoint and one output endpoint. Each endpoint has a length of 64 bytes.
• VID: 0x2047
• PID: 0x0200
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2 Bootloader Protocol – 1xx, 2xx, and 4xx Families
2.1 Synchronization Sequence
Before sending any command to the BSL, a synchronization character (SYNC) with its value of 80h must be sent
to the BSL. This character is necessary to calculate all the essential internal parameters, which maintain UART
and flash memory program and erase timings. It provides the BSL system time reference. When this is received,
an acknowledge DATA_ACK = 90h is sent back by the BSL to confirm successful reception.
This sequence must be done before every command that is sent to the BSL.
Note
The synchronization character is not part of the Data Frame described in Section 2.4.
2.2 Commands
Two categories of commands are available: commands that require a password and commands that do not
require a password. The password protection safeguards every command that potentially allows direct or indirect
data access.
2.2.1 Unprotected Commands
• Receive password
• Mass erase (erase entire flash memory, main as well as information memory)
• Transmit BSL version (V1.50 or higher or in loadable BL_150S_14x.txt but not V2.x BSLs)
• Change baud rate (V1.60 or V1.61 or V2.0x or in loadable BL_150S_14x.txt)
2.2.2 Password Protected Commands
• Receive data block to program flash memory, RAM, or peripherals
• Transmit data block
• Erase segment
• Erase check (present in V1.60 or higher or in loadable BL_150S_14x.txt)
• Set Memory Offset (present in V2.12 or higher)
• Load program counter and start user program
• Change baud rate (BSL versions lower than V1.60 and higher than V2.10)
2.3 Programming Flow
The write access (RX data block command) to the flash memory, RAM, or peripheral modules area is executed
online. That means a data byte or word is processed immediately after receipt, and the write cycle is finished
before a following byte or word has completely arrived. Therefore, the entire write time is determined by the baud
rate, and no buffering mechanism is necessary.
Data sections located below the flash memory area address are assumed to be loaded into the RAM or
peripheral module area and, thus, no specific flash control bits are affected.
Note
If control over the UART protocol is lost, either by line faults or by violating the data frame
conventions, the only way to recover is to rerun the BSL entry sequence to initiate another BSL
session.
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2.4 Data Frame
To ensure high data security during the data transmission, a data frame protocol called serial standard protocol
(SSP) is used. The BSL is considered the receiver in Table 2-1.
2.4.1 Data-Stream Structure
• The first eight bytes (HDR through LH) are mandatory (xx represents dummy data).
• Data bytes D1 to Dn are optional.
• Two bytes (CKL and CKH) for checksum are mandatory.
• Acknowledge done by the BSL is mandatory, except with the TX data block and TX BSL version commands.
Table 2-1. Data Frame of BSL Commands
Received
BSL
Command
HDR CMD L1 L2 AL AH LL LH D1 D2…Dn CKL CKH ACK
RX data block 80 12 n n AL AH n–4 0 D1 D2 … Dn–4 CKL CKH ACK
RX password 80 10 24 24 xx xx xx xx D1 D2 … D20 CKL CKH ACK
Erase segment 80 16 04 04 AL AH 02 A5 – – – – CKL CKH ACK
Erase main or info 80 16 04 04 AL AH 04 A5 – – – – CKL CKH ACK
Mass erase 80 18 04 04 xx xx 06 A5 – – – – CKL CKH ACK
Erase check 80 1C 04 04 AL AH LL LH – – – – CKL CKH ACK
Change baud rate 80 20 04 04 D1 D2 D3 xx – – – – CKL CKH ACK
Set mem offset 80 21 04 04 xx xx AL AH – – – – CKL CKH ACK
Load PC 80 1A 04 04 AL AH xx xx – – – – CKL CKH ACK
TX data block 80 14 04 04 AL AH n 0 – – – – CKL CKH –
BSL responds 80 xx n n D1 D2 ... ... … ... … Dn CKL CKH –
TX BSL version 80 1E 04 04 xx xx xx xx – – – – CKL CKH –
BSL responds 80 xx 10 10 D1 D2 ... ... … … … D10 CKL CKH –
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2.4.2 Checksum
The 16-bit (2-byte) checksum is calculated over all received or transmitted bytes B1 to Bn in the data frame,
except the checksum bytes themselves, by XORing words (two successive bytes) and inverting the result.
This means that B1 is always the HDR byte and Bn is the last data byte just before the CKL byte.
Formula
CHECKSUM = INV [ (B1 + 256 × B2) XOR (B3 + 256 × B4) XOR … XOR (Bn–1 + 256 × Bn) ]
or
CKL = INV [ B1 XOR B3 XOR … XOR Bn–1 ]
CKH = INV [ B2 XOR B4 XOR … XOR Bn ]
2.4.3 Example Sequence
The following example shows a request to read the memory of the MSP430 MCU from location 0x0F00. All
values shown below are represented in hexadecimal format.
TO BSL: 80
(Synchronization character sent to the BSL)
FROM BSL: 90
(Acknowledge from BSL)
TO BSL: 80 14 04 04 00 0F 0E 00 75 E0
(Send Command to read memory from 0x0F00, length 0x000E)
FROM BSL: 80 00 0E 0E F2 13 40 40 00 00 00 00 00 00 02 01 01 01 C0 A2
(Returned values from BSL)
2.4.4 Commands – Detailed Description
See Table 2-1.
2.4.4.1 General
Following the header byte HDR (80h) and the command identification CMD, the frame length bytes L1 and L2
(which must be equal) hold the number of bytes following L2, excluding the checksum bytes CKL and CKH.
Bytes AL, AH, LL, LH, D1...Dn are command-specific. However, the checksum bytes CKL (low byte) and CKH
(high byte) are mandatory.
If the data frame has been received correctly and the command execution was successful, an acknowledge
character DATA_ACK = 90h is sent back by the BSL. Incorrectly received data frames, unsuccessful operations,
and commands that are locked or not defined are confirmed with a DATA_NAK = A0h.
Note
BSL versions lower than V1.30 support only byte-access operations. Therefore, the peripheral module
addresses at 0100h to 01FFh cannot be accessed correctly, because they are word-oriented. In
version V1.30 and higher, addresses 0000h to 00FFh are accessed in byte mode; all others are
accessed in word mode.
2.4.4.2 RX Data Block
The receive data block command is used for any write access to the flash memory, RAM, or peripheral module
control registers at 0000h to 01FFh. It is password protected.
The 16-bit even-numbered block start address is defined in AL (low byte) and AH (high byte). The 16-bit even-
numbered block length is defined in LL (low byte) and LH (high byte). Because pure data bytes are limited to a
maximum of 250, LH is always 0.
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The following data bytes are succeeded by the checksum bytes CKL (low byte) and CKH (high byte). If the
receipt and programming of the appropriate data block was successful, an acknowledge character DATA_ACK is
sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK.
Note
BSL versions V1.40 and higher support online verification inside the MSP430 MCU for addresses
0200h to FFFFh, which reduces programming and verification time by 50%. Online verification means
that the data is immediately verified with the data that is written into the flash without transmitting it
again. In case of an error, the loadable bootloader BL_150S_14x.txt additionally stores the first
incorrectly written location address+3 into the error address buffer in the RAM at address 0200h
(021Eh for F14x devices).
2.4.4.3 RX Password
The receive password command is used to unlock the password-protected commands, which perform reading,
writing, or segment-erasing memory access. It is not password protected.
Neither start address nor block length information is necessary, because the 32-byte password is always located
at addresses FFE0h to FFFFh. Data bytes D1 to D20h hold the password information starting with D1 at address
FFE0h.
The BSL responds with DATA_ACK when the package from the host is received correctly and has valid content
as shown in Table 2-1. The DATA_ACK does not reflect that the password is correct (that is, it matches the
content of FFE0h to FFFFh) or incorrect. If an incorrect password is sent, other commands will respond with
DATA_NAK, because the BSL is still locked.
After the protected commands are unlocked, they remain unlocked until another BSL entry is initiated.
2.4.4.4 Mass Erase
The mass erase command erases the entire flash memory area (main memory plus information memory, see
corresponding data sheet). This command is not password protected.
All parameters shown in Table 2-1 are mandatory. After erasing, an acknowledge character DATA_ACK is sent
back by the BSL.
Mass erase initializes the password area to 32 times 0FFh.
Note
BSL versions 2.01 and higher support automatic clearing of the LOCKA bit, which protects information
memory.
When entering the BSL by cold start (that is, by applying the BSL hardware entry sequence on the
RST and TST pins), the LOCKA bit is automatically unlocked. A mass erase that is executed during
BSL communication erases all parts of information memory and also main memory.
When entering the BSL by warm start (that is, by jumping to the BSL application from a software
function), the LOCKA bit is not automatically unlocked. A mass erase performed in this state does not
erase the information memory. Therefore, when the BSL is called by software, the user application
must ensure that LOCKA is cleared before initialization of the BSL, so a mass erase command can
erase the information memory.
2.4.4.5 Erase Segment
The erase segment command erases specific flash memory segments. It is password protected.
The address bytes AL (low byte) and AH (high byte) select the appropriate segment. Any even-numbered
address within the segment to be erased is valid. After segment erasing, an acknowledge character DATA_ACK
is sent back by the BSL (V1.40 or lower).
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BSL versions V1.60 or higher perform a subsequent erase check of the corresponding segment and respond
with a DATA_NAK if the erasure was not successful. In this case, the first non-erased location address + 1 is
stored in the error address buffer in the RAM at address 0200h (021Eh for F14x devices). In this version, a
problem occurs if only one of the information memory segments is erased. In this case, an error is reported,
because an automatic erase check over the whole information memory is performed. As a solution, either erase
the whole information memory or do a separate erase check after the erase, even if the erase reported an error.
Erase segment 0 clears the password area and, therefore, the remaining password is 32 times 0FFh.
When applying LL = 0x04 and LH = 0xA5, a mass erasure of only the main memory is performed. Indeed, this
command must be executed a minimum of 12 times to achieve a total erasure time of >200 ms. No subsequent
erase check of the entire main memory is done. Use the erase check command additionally. Check the device
data sheet for more information on the cumulative (mass) erase time that must be met and the number of erase
cycles required.
2.4.4.6 Erase Main or Info
The erase main or info command erases specific flash memory section. It is password protected.
The address bytes AL (low byte) and AH (high byte) select the appropriate section of flash (main or information).
Any even-numbered address within the section to be erased is valid.
2.4.4.7 Erase Check
The erase check command verifies the erasure of flash memory within a certain address range. It is password
protected.
The 16-bit block start address is defined in AL (low byte) and AH (high byte). The 16-bit block length is defined in
LL (low byte) and LH (high byte). Both can be either even or odd numbered to allow odd boundary checking.
If the erase check of the appropriate data block was successful (all bytes contain 0FFh), an acknowledge
character DATA_ACK is sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK and the first non-
erased location address + 1 is stored in the error address buffer at address 0200h (021Eh for F14x devices).
Note
This command is not a member of the standard command set. It is implemented in BSL version V1.60
and higher or in the loadable bootloader BL_150S_14x.txt.
2.4.4.8 Change Baud Rate
The change baud rate command offers the capability of transmissions at higher baud rates than the default 9600
baud. With faster data transition, shorter programming cycles can be achieved, which is especially important with
large flash memory devices. This command is not password protected.
Three control bytes (D1 to D3) determine the selected baud rate. D1 and D2 set the processor frequency
(f ≥ fmin), D3 indirectly sets the flash timing generator frequency (fFTGmin ≤ fFTG ≤ fFTGmax). In detail:
D1: F1xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)
F2xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)
F4xx: FLL+ system clock control register SCFI0 (D, FN_8 to FN_2)
D2: F1xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)
F2xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)
F4xx: FLL+ system clock control register SCFI1 (NDCO)
D3 0: 9600 baud
1: 19200 baud
2: 38400 baud
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After receiving the data frame, an acknowledge character DATA_ACK is sent back, and the BSL becomes
prepared for the selected baud rate. TI recommends that the BSL communication program wait approximately
10 ms between baud rate alteration and the next data transmission to give the BSL clock system time to
stabilize.
Note
The highest achievable baud rate depends on various system and environment parameters like supply
voltage, temperature range, and minimum and maximum processor frequency. See the device-specific
data sheet.
Note
This command is implemented on BSL versions V1.60 or higher or available in the loadable
bootloader BL_150S_14x.txt.
Table 2-2. Recommendations for MSP430F149 [MSP430F449]
(TA = 25°C, VCC = 3.0 V, fmax = 6.7 MHz)
Baud Rate
(baud)
Processor
Frequency, fmin
(MHz)(3)
D1 DCOCTL
[SCFI0](1)
D2 BCSCTL1
[SCFI1](1) D3(1)
Program and Verify
60 KB
(sec)(2)
9600 (init) 1.05 0x80 [00] 0x85 [98] 00 [00] 78 + 3.7 [0.0]
19200 2.1 0xE0 [00] 0x86 [B0] 01 [01] 39 + 3.7 [2.4]
38400 4.2 0xE0 [00] 0x87 [C8] 02 [02] 20 + 3.7 [2.4]
(1) D1 to D3 are bytes in hexadecimal notation.
(2) Additional 3.7 [2.4] seconds result from loading, verifying, and launching the loadable BSL.
(3) The minimum processor frequency is lower than in the standard ROM BSL (see Section 2.9.3, Initialization Status).
Table 2-3. Recommendations for MSP430F2131
(TA = 25°C, VCC = 3.0 V, fmax = 6.7 MHz)
Baud Rate
(baud)
Processor
Frequency, fmin
(MHz)(2)
D1 DCOCTL
[SCFI0](1)
D2 BCSCTL1
[SCFI1](1) D3(1)
Program and Verify
60 KB
(sec)
9600 (init) 1.05 0x80 0x85 00 78
19200 2.1 0x00 0x8B 01 39
38400 4.2 0x80 0x8C 02 20
(1) D1 to D3 are bytes in hexadecimal notation.
(2) The minimum processor frequency is lower than in the standard ROM BSL (see Section 2.9.3, Initialization Status).
2.4.4.9 Set Memory Offset
An offset for the memory pointer can be set for devices that have more than 64KB of memory, specifically
MSP430X architecture devices. The value for the memory offset is used as the memory pointer’s upper word.
Memory Address = Offset Value << 16 + Actual Address
Note
This command is implemented on BSL versions V2.12 and higher.
2.4.4.10 Load PC
The load program counter command directs the program counter (register R0) to any location within the entire
address range. It is password protected.
After receiving the data frame, an acknowledge character (DATA_ACK) is sent back by the BSL. Then the
selected address is moved into the program counter. The program flow continues operation there, and the BSL
session is terminated.
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Be aware that password protection is not active at this time. Jumping to the user application does not reset the
device and, therefore, the register configuration from the BSL application is kept. This might cause unexpected
behavior in the user application. One example is the blink LED application, which does not have any clock
module configuration (so it uses the default 1-MHz clock) and will blink faster, because the clock module is set
by the BSL application to run at 8 MHz.
2.4.4.11 TX Data Block
The transmit data block command is used for any read access to the flash memory, RAM, or peripheral module
control registers at 0000h to 01FFh. It is password protected.
The 16-bit block start address is defined in AL (low byte) and AH (high byte). The 16-bit block length is defined in
LL (low byte) and LH (high byte). Because pure data bytes are limited to a maximum of 250, LH is always 0. The
checksum bytes CKL (low byte) and CKH (high byte) immediately follow this information.
Now the BSL responds with the requested data block. After transmitting HDR, dummy CMD, L1 and L2, The
BSL sends data bytes D1 through Dn, followed by the checksum bytes CKL (low byte) and CKH (high byte). No
acknowledge character is necessary.
2.4.4.12 TX BSL Version
The transmit BSL version command gives the user information about chip identification and bootloader software
version. It is not password protected.
The values for AL, AH, LL, and LH can be any data, but must be transmitted to meet the protocol requirements.
The checksum bytes CKL (low byte) and CKH (high byte) follow this information.
After that, the BSL responds with a 16-byte data block. After transmitting HDR, dummy CMD, L1 and L2, the
BSL sends data bytes D1 through D16 (decimal), followed by the checksum bytes CKL (low byte) and CKH (high
byte). No acknowledge character is necessary.
D1, D2 and D11, D12 (decimal) hold the specific information:
• D1: Device family type (high byte)
• D2: Device family type (low byte)
• D11: BSL version (high byte)
• D12: BSL version (low byte)
The remaining 12 bytes are for internal use only.
2.5 Loadable BSL
For upgrading the BSL functionality, sometimes it is suitable to load a higher version of BSL into the RAM of a
device and apply the latest innovations. To do so, use the following BSL commands:
• RX password (unlock password protection for following commands)
• RX data block (code of loadable BSL, code section address ≥ 220h)
• TX data block (for verification)
• RX data block (get start address from first code section address)
• Load program counter PC (with start address of loadable BSL)
• Wait at least 5 ms until the new loaded BSL has executed the initialized routine
• RX password (unlock password protection for loaded BSL)
• Perform any command (with loaded BSL)
The following loadable BSLs are available:
•BL_150S_14x.txt is a complete BSL for the F14x and F13x family with BSL version 1.10. All features of BSL
version V1.60 are supported. Because its code size is larger than 1KB, it can be used only in F1x8 and F1x9
devices. The error address buffer address for RX Block, Erase Segment, and Erase Check commands is
021Eh. BL_150S_14x.txt could also be used as a replacement for PATCH.txt.
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•BS_150S_14x.txt is a small BSL with reduced command set for the F14x and F13x family with BSL version
1.10. Because its code size is smaller than 512B, it can be used in F1x4 up to F1x9 devices. The following
commands of BSL version V1.60 are supported: Change Baud Rate, RX Block (with online verification),
Erase Check, and Load PC. If a TX Block command (redirected to ROM BSL) is needed (for example, for
transmitting error address or standalone Verify), the RAM BSL must be invoked again by the Load PC
command. The error address buffer address for RX Block and Erase Check commands is 021Eh.
BS_150S_14x.txt could also be used as a partial replacement for PATCH.txt. No password is required, as the
RX password command is removed.
For more information on downloading a different bootloader, see Application of Bootloader in MSP430 With
Flash Hardware and Software Proposal.
Third-party software normally uses loadable BSLs to perform most functions, like online verification, and to
improve speed for appropriate devices.
2.6 Exiting the BSL
To exit the BSL mode, two possibilities are provided:
• The microcontroller continues operation at a defined program address invoked by the load program counter
command. Be aware that the password protection is not active at this time. In this case, the user application
should ensure that the flash is locked, as this is not done by the BSL. Leaving the BSL unlocked increases
the risk of erroneously modifying the flash due to system or software errors. On 2xx devices, the correct
setting of the LOCKA bit should also be checked.
• Applying the standard RESET sequence (see Figure 1-1) forces the microcontroller to start with the user
reset vector at address 0FFFEh.
2.7 Password Protection
The password protection prohibits every command that potentially allows direct or indirect data access. Only the
unprotected commands like mass erase and RX password (optionally, TX BSL version and change baud rate)
can be performed without prior receipt of the correct password after BSL entry.
Applying the RX password command for receiving the correct password unlocks the remaining commands.
After it is unlocked, it remains unlocked until initiating another BSL entry.
The password itself consists of the 16 interrupt vectors located at addresses FFE0h to FFFFh (256 bits), starting
with the first byte at address FFE0h. After mass erase and with unprogrammed devices, all password bits are
logical high (1).
BSL versions 2.00 and higher have enhanced security features. These features are controlled by the flash data
word located beneath the interrupt vector table addresses (for example, for the MSP430F2131, address
0xFFDE). If this word contains:
• 0x0000: The flash memory is not erased if an incorrect BSL password has been received by the target.
• 0xAA55: The BSL is disabled. This means that the BSL is not started with the default initialization sequence
shown in Section 1.3.1.
• All other values: If an incorrect password is transmitted, the entire flash memory address space is erased
automatically.
Note
The user must take care of password update after modifying the interrupt vectors and initiating
another BSL session. TI strongly recommends initializing unused interrupt vectors to increase data
security.
2.8 Code Protection Fuse
After the JTAG fuse (code protection fuse) is blown, no further access to the JTAG test feature is possible. The
only way to get any memory read or write access is through the bootloader by applying the correct password.
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However, it is not possible for the BSL to blow the JTAG fuse. If fuse blowing is needed, use JTAG programming
techniques.
2.9 BSL Internal Settings and Resources
The following paragraphs describe BSL internal settings and resources. Because the same device can have
implemented different BSL versions, it is very important for the BSL communication program to know the settings
and resources. Resources could be either device dependent (for example, RX or TX pins) or BSL-version
dependent (for example, byte or word access). The following sections describe the possible variations.
2.9.1 Chip Identification and BSL Version
The upper 16 bytes of the boot-ROM (0FF0h to 0FFFh) hold information about the device and BSL version
number in BCD representation. This is common for all devices and BSL versions:
• 0FF0h to 0FF1h: Chip identification (for example, F413h for an F41x device).
• 0FFAh to 0FFBh: BSL version number (for example, 0130h for BSL version V1.30).
See the MSP430 device to BSL version assignment in Section 5.
2.9.2 Vectors to Call the BSL Externally
The entry part of the boot ROM holds the calling vectors for BSL access by program:
• 0C00h: Vector for cold start (mnemonic: BR &0C00h ) (recommended)
• 0C02h: Vector for warm start (mnemonic: BR &0C02h ). V1.30 or higher.
• 0C04h: Vectors for future use. This table is expandable.
Note
A warm start does not modify the stack pointer. Additionally, the status register for the BSL is not
cleared, which could cause a warm started BSL to come up in an unlocked state. Warm start
possibility exists only for highly specialized instances where it is absolutely mandatory that a running
application be returned to after a BSL session without resetting the device. In almost all cases, it is
better to start the BSL from user code by calling the cold start vector.
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2.9.3 Initialization Status
When activating the BSL, the following settings take effect:
• Stop watchdog timer
• Disable all interrupts (GIE = 0)
•V1.10
The stack pointer is not modified, except when it points to an excluded memory area. If so, it is initialized to
021Ah.
V1.30 or higher
The stack pointer is not modified if the BSL is called by the program through the warm-start vector. It is
initialized to 0220h if the BSL starts by the BSL RESET sequence or is called by the program through the
cold-start vector.
•F1xx
Determine basic clock module so that minimum frequency is 1.5 MHz:
BCSCTL1 = 85h (RSEL = 5, XT2Off = 1)
DCOCTL = 80h (DCO = 4, MOD = 0)
BCSCTL2 = 00h only at cold start
SR: SCG1 = 00h (SMCLK on) only at cold start
F2xx
Determine basic clock module so that minimum frequency is 1.5 MHz:
BCSCTL1 = 88h (RSEL = 8, XT2Off = 1)
DCOCTL = 80h (DCO = 4, MOD = 0)
BCSCTL2 = 00h only at cold start
SR: SCG1 = 00h (SMCLK on) only at cold start
F4xx
Determine FLL oscillator and system clock so that minimum frequency is 1.5 MHz:
SCFI0 = 00h (D = 0, FN_x = 0)
SCFI1 = 98h (N_DCO)
SCFQCTL: (M = 0)
SR: SCG0 = 1 (FLL loop control off)
FLL_CTL1 = 00h only at cold start
• SW-UART: Timer_A operates in continuous mode with MCLK source (Div = 1)
CCR0 used for compare
CCTL0 used for polling of CCIFG0
• TX pin is set to output high for RS232 idle state
• RX pin is set to input
• Password-protected commands are locked (only at cold start)
After system initialization, the BSL is ready for operation and waits for the first synchronization sequence (SS)
followed by a data frame containing the first BSL command.
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2.9.4 Memory Allocation and Resources
• The BSL program code is located in the boot-ROM area 0C00h to 0FEFh.
• Addresses 0FF0h to 0FFFh hold the device identification.
• The BSL variables occupy the RAM area
– 0200h to 0213h (V1.10)
– 0200h to 0219h (V1.30 or higher)
• The BSL stack occupies the RAM area
– 0214h to 0219h (V1.10)
– 021Ah to 021Fh (V1.30 or higher, only at cold start)
• The working registers used are:
– R5 to R9 (V1.30 or lower) or
– R5 to R10 (V1.40) or
– R5 to R11 (V1.60) or
– R5 to R14 (V2.00 or higher)
Their contents are not buffered.
– F1xx and F2xx:
• The basic clock module registers used are:
– DCOCTL at address 056h
– BCSCTL1 at address 057h
– F4xx:
• The FLL oscillator and system clock registers used are:
– SCFI0 at address 050h
– SCFI1 at address 051h
– SCFQCTL at address 052h
• The Timer_A control registers used are:
– TACTL at address 0160h
– CCTL0 at address 0162h
– TAR at address 0170h
– CCR0 at address 0172h
• The flash control registers used are:
– FCTL1 at address 0128h
– FCTL2 at address 012Ah
– FCTL3 at address 012Ch
• No interrupt service is affected.
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3 Bootloader Protocol – F5xx and F6xx Families
3.1 BSL Data Packet
The BSL data packet has a layered structure. The BSL core command contains the actual command data to be
processed by the BSL. In addition the standard BSL commands, there can be wrapper data before and after
each core command known as the peripheral interface code (PI Code). This wrapper data is information that is
specific to the peripheral and protocol being used, and it contains information that allows for correct transmission
of the BSL core command. Taken together, the wrapper and core command constitute a BSL data packet.
PI Code BSL Core Command PI Code
3.2 UART Peripheral Interface (PI)
3.2.1 Wrapper
The default BSL430 programmed in each non-USB MSP430F5xx device communicates using a UART
peripheral interface (PI). The UART protocol interface has the format shown in Table 3-1. All numbers are in
hexadecimal format.
Table 3-1. UART Protocol Interface
Header Length Length BSL Core Command CKL CKH ACK
0x80 NL NH See Table 3-5 CKL CKH (ACK)
from BSL
3.2.2 Abbreviations
CKL, CKH
CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command section only.
The CRC is computed using the MSP430F5xx CRC module specification (see the CRC chapter of the
MSP430F5xx and MSP430F6xx Family User's Guide for implementation details).
NL, NH
Number of bytes in BSL core data packet, broken into high and low bytes.
ACK
Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not imply the
BSL core data is a correct command or that it was executed correctly. ACK signifies only that the packet was
formatted as expected and had a correct checksum.
Note
If the PI encounters an error at any stage of receiving the packet, it immediately responds with the
appropriate error message.
3.2.3 Messages
The peripheral interface section of the BSL430 software parses the wrapper section of the BSL data packet. If
there are errors with the data transmission, an error message is sent immediately. An ACK is sent after all data
has been successfully received and does not mean that the command has been correctly executed (or even that
the command was valid) but, rather, that the data packet was formatted correctly and passed on to the BSL core
software for interpretation.
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Table 3-2. UART Error Messages
Data Meaning
0x00 ACK
0x51 Header incorrect. The packet did not begin with the required 0x80 value.
0x52 Checksum incorrect. The packet did not have the correct checksum value.
0x53 Packet size zero. The size for the BSL core command was given as 0.
0x54 Packet size exceeds buffer. The packet size given is too big for the RX buffer.
0x55 Unknown error
0x56 Unknown baud rate. The supplied data for baud rate change is not a known value.
3.2.4 Interface Specific Commands
The Timer UART protocol interface also accepts the following command when it is transmitted as BSL core data.
BSL Command CMD AL AM AH Data
Change baud rate 0x52 – – – D1
3.2.4.1 Change Baud Rate
This command changes the baud rate for all subsequently received data packets. The command is
acknowledged with either a single ACK (sent at the current, not the newly selected, baud rate) or an error byte.
No subsequent message packets can be expected.
D1: Valid values
• 0x02: 9600
• 0x03: 19200
• 0x04: 38400
• 0x05: 57600
• 0x06: 115200
3.3 I2C Peripheral Interface
3.3.1 I2C Protocol Definition
The I2C protocol used by the BSL is defined as:
• Master must request data from BSL slave.
• 7-bit addressing mode is used, and the slave listens to address 0x48.
• Handshake is performed by an acknowledge character in addition to the hardware ACK.
• Minimum time delay before sending new characters after characters have been received from the MSP430
BSL is 1.2 ms.
• Repeated starts are not required by the BSL but can be used.
3.3.2 Basic Protocol With Byte Level Acknowledge
START ADDRESS W ACK DATA PACK DATA ACK
Sent by master
Sent by slave
Figure 3-1. Basic Protocol - Byte Level ACK
1. Send the START bit
2. Send the slave address
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