Varian DATA 620/i User manual

DATA 620/i
SYSTEM
REFERENCE
MANUAL .
- --~

DATA 620/i
SYSTEM
REFERENCE
MANUAL
va~ian data machines fa varian subsidiary
.......... 2722 michelson drive/irvine/california/92664/(714)833·2400
C 1968 printed in USA

VDM-3000
Revision A
March 1968

CONTENTS'
Page
SECTION 1 INTRODUCTION
1. 1 General
1-1
1
.2
Specifications
1-2
1.3
Use of this Manual
1-6
SECTION 2 SYSTEM DESCRIPTION
2. 1 Computer Organization 2-1
2.2 Computer Word Formats
2-6
2.3 Computer Options 2-11
SECTION 3 OPERATIONAL INSTRUCTIONS
3. 1 General
3-1
3.2
Sing Ie-Word Instructions 3-1
3.3
Double-Word Instructions 3-31
SECTION 4 INPUT/OUTPUT
SYSTEM
4.1 Introducti on
4-1
4.2 Organizati on
4-1
4.3
Program Control Functions
4-3
4.4 Optional Automatic Control Functions 4-11

Page
SECTION 5
CONTROL CONSOLE OPERATION
5.1
Controls and Indicators
5-1
5.2 Manual Operation 5-1
APPENDICES A
DA TA 620/i Number System A-1
B
Standard DATA 620/i Subroutines
B-1
C
Table of Powers of Two
C-1
D Octal-Decimal Integer Conversion Table
D-1
E
Octal-Decimal Fraction Conversion Table
E-1
F DATA
620/i Instructions (Alphabetical Order)
F-1
G
DATA 620/i Instructions (By Type)
G-l
H DATA
620/i Reserved Instruction Codes
H-1
I
Standard Character Codes
1-1
ii

1.1 GENERAL
SECTION 1
INTRODUCTION
The DATA 620/i is a high-speed, parallel, binary computer.
Its flexible design and modular packaging make it ideal for
operation both as a general-purpose machine and for applica-
tion as an on-line system component. Its features include:
Fast opera tion:
Large
instruction
repertoire:
Word length:
Modu lar memory:
Multiple addressing
modes:
Flexible I/O:
Extensive software:
Modu lar packag ing:
1 .
8-mi crosecond memory cycle.
107 standard, 18 optional; with
approxima te Iy 200 addi ti ona I
instruction configurations which
can be microcoded.
16- or 18-bi t configurations.
4096 word minimum, 32,768 words
maximum.
Direct, indirect, relative, index,
immediate, and extended (optional).
Up to 10 devi ces may be placed on
the I/O bus. The I/O system is
easily expandable to include
features such as automatic block
tra nsfer, priori ty interru pt, and
"cycle-stealing" data transfers.
Complete package includes an
assembler, mathematics and I/O
library, AID diagnostics, and an
ASA FORTRAN subset.
Mounts in a standard 19-inch
cabinet. No special mechanical
or environmental facilities are
required.
The advanced design techniques used throughout the DA TA
620/i system provide solutions to real-time data acquisition,
telemetry processing, process control, and simulation prob-
lems. In addition, the DATA 620/i is well suited for scientific
computations. Special attention has been given to the inter-
fac i ng probl ems usua 1\ y e ncoun tered in integra ti ng a di g ita I
compu ter into a system. As a resu It, the DATA 620/i ca n be
joined to a system with unparalleled efficiency.
1-1

1.2 SPECIFICATIONS
1-2
The unique design of the DA TA 620/i makes it easy to program,
operate and maintain. The entire mainframe includes the
processor, all processor options, and a 4096-word core memory
in a
convenient 10-1/2 inch high rack-mountable package.
Only 17 circuit boards of 11 different types are used in the
basic 16-bit configuration.
Power suppl ies for the processor and up to 8192 words of core
memory are a separate 10-1/2 inch high package that mounts
behind the mainframe. Thus, the entire computer requires
only 10-1/2 inches of a standard 19-inch rack. Installation
is easy, requiring no special mounting, cabling, or air
conditioning provisions.
Maintainability of the DATA 620/i is enhanced by easy front
access to all wiring, making it unnecessary to remove panels
on the computer rack to obtain access to the modu les, con-
nectors, and wiring.
A complete set of software provided with the DATA 620/i
permits rapid preparation of application programs. The system
software includes:
FORTRAN:
DATA 620/i Assembly
System (DAS):
AID:
MAINTAIN:
Subroutine Library:
Subset of ASA FORTRAN.
Two-pass symbolic assembler.
On-line debugging and utility
package.
Complete set of computer and
peripheral diagnostics.
Complete library of transcendental
functions, sing le- and double-
precision and floating-point
ari thmeti c, forma t conversion,
and peripheral service routines.
A wide variety of peripheral equipment is available to provide
the DATA 620/i user with a complete system suited to specific
needs.
Specifications of the DATA 620/i computer are listed in
table 1-1.

Specification
Type
Memory
Arithmetic
Table 1-1. DATA 620/i Specifications
Characteristics
General-purpose digital computer for on-I ine data system
applications. Magnetic core memory: binary, parallel,
single-address, with bus organization.
Magnetic core, 16 bits (18 bits optional); 1.8 micro-
seconds fu II-cycle, 700-nanosecond access time, 4096
words minimum, expandable in 4096-word modules to
32,768 words. Power-fai lure protection optional, non-
volatile. Thermal over-load protection is standard.
Parallel, binary, fixed point, 21s complement.
Word Length
Speed (fetch and
execute)
Add or Subtract
16 bits standard; 18 bits optional.
3.6 microseconds.
Multiply (optional) 16 bits - 18.0 microseconds.
18 bits - 19.8 microseconds.
Divide (optional) 16 bits - 18.0fo25.2 microseconds.
18 bits - 19.8to28.8 microseconds.
Register Change
Input/Output
Registers
A Register
B Reg ister
X Register
1.8 microseconds.
From A or B register - 3.6 micro-
seconds.
From memory
seconds.
- 5.4 micro-
Accumulator, input/output, 16
or 18 bits.
Low-order accumulator, input/
output, index register, 16 or
18 bits.
Index register, multi-purpose
register, 16 or 18 bits.
1-3

1-4
Specifi cati on
Instruction Types
Instructions
Micro-EXEC
(optional)
Table 1-1. (Continued)
P Register
U Register
L Register
W Register
S Register
R Register
Control
Characteristi cs
Instruction counter, 16 or 18 bits.
Instruction register, 16 bits.
Memory address register, 16 bits.
Memory word register, 16 or 18
bits.
Shift register, 5 bits.
Operand register, 16 or 18 bits.
Addressing Modes Six as follows:
Direct: to 2048 words.
Relative to P register: to 512 words.
Index with X register hardware: to 32,768 words (does not
add to execution time).
Index with B register hardware: to 32,768 words (does not
add to execution ti me).
Multilevel indirect: to 32,768 words.
Immediate: operand immediately follows instruction.
Extended: operand address immediately follows instruc-
tion
(optional): to 32,768 words.
Four, as follows:
Single word, addressing.
Single word, non-addressing.
DoubIe word, addressing •
DoubIe word, non-add ressing .
107 standard, approximately 200 microinstructions, plus
18 optional.
Faci I ity and hardware to construct a hardwired program
external to the DATA 620/i. Eliminates stored program
memory
accessing for hardwired programs.

Specifi cati on
Control Panel
Input Output
Data Transfer
External Control
(select)
Program Sense
Interrupts
(optional)
Physical
Characteri stics
Dimensions
Weight
Power
Expansion
Installation
Environment
Table 1-1. (Continued)
Characteri stics
Selectable display and data entry switches, three sense
switches, instruction repeat, single step, run, power
on/off, system reset.
Three types as follows:
Single word to/from memory (program control).
Single word to/from A and B registers (program control).
Optional direct memory access (cycle-steal).
Up to 512 external control lines.
Up to 512 status Iines may be sensed.
Power fai lure, priority interrupts {expandable in groups
of eight} with group enable/disable and individual arm/
disarm. Each interrupt line is associated with a unique
memory location.
10-1/2 inches high, 13 inches deep.
90 pounds, including power supplies.
360 watts, single phase, 115 vac ± 10 vac, 48-62 Hz.
Power supplies are regulated. Additional regulation is
not required with normal commercial power sources.
Mainframe package contains a 4096-word memory, the
processor, and space for processor options. Addi tiona I
memory requires an additional 10-1/2 inches of rack
height for up to 8192 words of additional storage.
Peripheral controllers are mounted external to the main-
frame.
Mainframe and power supply packages require 10-1/2
inches of standard 19-inch racks. No air-conditioning,
subflooring, special wiring, or site preparation is
required.
100C to 45
0
C, 10%to 90% relative humidity.
1-S

Specifi cation
Logic and Signals
Software
DAS Assembler
FORTRAN
AID
MAINTAIN
Subroutines
1.3 USE OF THIS MANUAL
1-6
Table 1-1. (Continued)
Characteri stics
The logic
of the computer utiI izes DTL and TTL integrated
circuits employing 5-volt levels. The logic levels on
the transmission buses (I/O bus, interrupt bus, etc.) are
a Iso +3 v to reduce cross ta Ik and current requi rements.
Internal logic conventions are 5 v for logical 1, and 0 v
for logical O. Logic conventions on the buses are +3 v
for logical 0, and 0 v for logical 1.
Modular two-pass symbolic assembler which operates within
the base 4096-word memory. It inc I udes 17 basic pseudo-
ops. The 8192-word memory version includes over 30
pseudo-ops for programming ease.
Modul ar one-pass compileri subset of ASA FORTRAN for
8192-word memory.
Program analysis package which assists programmers in
operating the machine and debugging other programs.
Includes basic operationa I executive subroutines.
Modular, two-mode diagnostic package which provides fast
verifi cation of central processor and peri pheral operation,
and assists in isolating and correcting suspected faults.
Compl ete I ibrary of basic mathemati ca I, fixed- and
floating-point, single- and double-precision, number
conversion and peripheral communication subroutines
plus provisions for adding appl i cation-oriented routines.
This manual provides the basic information required for
programming
and using the DATA 620/i, and is intended to
be used in con junction with other publi cations for the 620-
series computers. These publications are I isted in table
1-2.
The interface reference manua I provides detailed informa-
tion for integrating the DATA 620/i with special system
components.

Publication Number
VDM-3000
VDM-3001
VDM-3002
VDM-3003
VDM-3004
VDM-300S
VDM-3006
VDM-3007
VDM-300B
VDM-3009
VDM-3010
VDM-3011
VDM-3013
VDM-3014
VDM-301S
VDM-3016
VDM-3017
VDM-301B
VDM-3019
VDM-3020
Table 1-2. DATA 620/i Documents
Title
System Reference Manua I
Interface Reference Manual
Programming Reference Manual
FORTRAN Manual
Subroutine Manual
Maintenance Manuals
ASR-33 Teletype Controller Reference Manual
Buffer I nterlace Controller Reference Manua I
Magnetic Tape Controller Reference Manual
600 LPM Line Printer Controller Reference Manua I
300 LPM Line Printer Controller Reference Manua I
Paper Tape System Controller Reference Manual
Priority I nterrupt Reference Manua I
A/D Converter Reference Manua I
Optical Scanner Controller Manual
ASR-3S Teletype Controller Reference Manual
Digital Plotter Controller Reference
DDC Disc Controller Reference Manual
Console Printer Controller Reference Manua I
InstalIati
on Ma nua I
Information required by the programmer for using the software
packages is contained in the programming reference,
FORTRAN, and subroutine manuals.
The maintenance manuals contain detailed design theory,
logic and timing diagrams, circuit board data, maintenance
procedures, and diagnosti c programs.
1-7

1-8
Detailed design and maintenance information on peripheral
device controllers is contained in individual reference
manuals for these units. Operation and maintenance proce-
dures for optiona I peri phera I devi ces (tape transports,
printers, etc.) are contained in the manufacturers' reference
manuals furnished with the equipment.
Section 2 of this manual contains an overall description of
the DATA 620/i system, and describes the word formats used
in
the computer. Section 3 describes the complete instruc-
tion set for the computer. The input/output system, including
all input/output, sense, control, and interrupt instructions is
described in section 4. Section 5 provides information
required for using the control console of the computer.

2. 1 COMPUTER
ORGANIZATION
SECTION 2
SYSTEM DESCRIPTION
The DATA 620/i is organized with a unique bus structure,
selection logic, and nine registers. The organization
provides universal information routing, buffered processing,
microprogramming capabiiity, indexing without time penalty,
and buffered input/output data transfer. A unique optional
facility, Micro-EXEC, is also available which permits
complex algorithms to be implemented with external control
hardware. This capability provides increases in processing
speed in excess of 400 percent over norma I programmed
operations.
The organization of the DA TA 620/i is shown in figure 2-1 •
This diagram shows the major functional elements of the
machine, including the registers and buses provided for
informati
on transfer.
The major functional elements of the DATA 620/i, indicated
in figure 2-1, are: control section, arithmetic/logic
secti on, operationa I regi sters, i nterna I buses, i nput/ ou tput
(I/O) bus, and memory.
2. 1•1 Control Secti on
The control. section provides the timing and control signals
required to perform all operations in the computer. The
major elements in this section are the U register, the timing
and decoding logic, and the shift control.
The U register (instruction register) is 16 bits long. This
register receives each instruction from memory through the
W bus and holds the instruction during its execution. The
con trol fi e Ids of the instru cti on word are rou ted to the decod-
ing and timing logic where the codes determine the required
timing and control signals. The address field from the U
register, used for various addressing operations, is also routed
to the arithmetic/logic section.
The decoding logic decodes the fields of the instruction word
held in the U register to determine the control signal levels
required to perform the operations specified by the instruction.
These levels select the timing signals generated by the timing
unit.
2-1

r--- ---l
I I
I
DATA I
I DISPLAY I
I I
I I
I I
I DATA I
I SWITCHES I
I I
L ___ ___ -l
SET R.,
SET U'" J
R U TIMING
AND
-:> CONTROL
REGISTER REGISTER
LOGIC
SLR I \!rSLR 1
SLU
{ I I
CONTROL BUS
f---- -+-....-- - - --
I I E-BUS
I: ~
L_J
I
FIRST
J
TTY
UNIT
~
0 1l D
.,
1
~
CONTROL &
~
FIRST
E-BUS
VO
110
ARITHMETIC
ADDER
TTY
INTERFACE
DEVICE DEVICE
LOGIC
CONTROLLER
OPTION OPTION
t L
~
'7
V
"'-
C-BUS
C-BUS
SET L.
.,
SETW_ ... ,
SET A...
.,
SET B'" 1
SET X.
SET '1
,
L W A B X P
REGISTER REGISTER REGISTER
REGISTER REGISTER REGISTER
MSC '. I ,,-J---'-'----,
MEMORY
FIRST
4K
,
IjI
SLA
SLB
}
S-BUS
W-8US (MEMORY DATA)
L-BUS (MEMORY ADDRESS)
MSC 2.
,..z..._ ........ _--..,
MEMORY
SECOND
4K
Fig. 2-1. DATA 620/i Organ ization
SLX J
SLP
POI 26801A

Timing logic generates the basic 4.4-MHz system clock.
From this clock, timing logic derives the timing pulses which
control the sequence of all operations in the computer.
The shift control contains the shift counter and logic to
control operations performed by the shift, multiply, and
divide instructions.
2.1.2 Airthmetic/Logic Section
This section consists of two elements; the R register and the
ari thmeti c un it.
The R register receives operands from memory and holds them
during instruction execution. The operand may be either data
or address words. Th is reg i ster permits transfers be tween
memory and I/O bus during the execution of extended-cycle
instructions.
The arithmetic unit contains gating required for all arith-
metic, logic, and shifting operations performed by the
computer. Indexed and relative address modifications are
performed in this section without increased instruction
execution time.
The arithmetic unit also controls the gating of words from
the operational registers and the I/O bus onto the C bus
where they are distributed to the operational registers or
to memory registers. This facility is used to implement
many of the microinstructions of the computer.
2.1.3 Operational Registers
The
basic DATA 620/i computer contains nine registers.
The operational registers consist of the A, B, X, and P
registers. The A, B, and X registers are directly accessible
to the programmer. The P register is indirectly accessible
through use of the jump-class instructions which modify the
program seque nce. The operati ona I reg is ters are descri bed
in the following paragraphs.
2-3

2-4
A register. This full-length register is the upper half of the
accumulator. This register accumulates the results of logical
and addition/subtraction operations, the most-significant
half of the double-length product in multiplication, and the
remainder in division. It may also be used for input/output
transfers under program control.
B register. This full-length register is the lower half of the
accumulator. This register accumulates the least-significant
half of the double-length product in multiplication, and the
quotient in division. It may also be used for input/output
transfers under program control and as a second hardware
index reg i ster .
X
register. This full-length register permits indexing of
operand addresses without adding time to execution of
indexed instructions.
P register. This full-length register holds the address of the
current instruction and is incremented before each new
instruction is fetched. A full complement of instructions is
available for conditional and unconditional modification of
this register.
S register. This five-bit register controls the length of shift
instructions in combination with the U register.
2. 1.4 I nterna I Buses
The basic
computer contains five buses. These are the
(, S, W, L, and I/O buses. Buses (, S, W, and Lore
described in the following paragraphs. The I/O bus is
descri bed in paragraph 2. 1 .5.
(bus. This bus provides the parallel path and selection logic
for routing data between the arithmetic unit, the I/O bus,
the operational registers, and the memory registers. The
console display indicators are also driven from the ( bus.
Distribution of data simultaneously to multiple operational
registers is facilitated by this bus.
S bus. Th is bus provides the parallel path and selection log ic
for routing data from the operational registers to the
ari thmeti c uni t.

W bus. The memory word (W) register is directly connected
to all memory modules through the W bus. The bus is
bidirectional and time-shared among memory modules.
L bus. The memory address (L) register is directly connected
to all memory modules through the L bus. The bus is
unidirectional.
2.1.5 Input/Output Bus
The standard DATA 620/i is provided with a bidirectional
input/output (I/O) bus that permits programmed data transfers
between periphera I devi ces and the computer.
2.1.6 Memory
The internal storage of the computer consists of 4096-word
modules connected to the Land W buses. The mainframe
can accommodate one 4096-word module. Additiona I
modules are added in an additional frame that is attached to
the mainframe. The computer memory can be expanded to
a maximum of 32,768 words using 4096-word modules.
I nstruction words read from memory are transferred to the
control section for execution. Words may be transferred,
under program control, from memory to the arithmetic/logic
section, to the operational registers, or to the I/O bus.
Words may be transferred, under program control, to memory
from
the operational registers or the I/O bus. When the
direct memory access option is used, the system is capable
of direct transfer between memory and peripheral devices
on the I/O bus, concurrent with computations.
2.1.7 Direct Memory Access
The direct-memory-access (DMA) option allows data transfer
into or out of memory modules without disturbing the con-
tents of the operational registers. Only the Land W registers
are altered. Access to memory using the DMA facility is
on a
IIcycle-steal" basis and requires 2.7 microseconds of
processor time per transfer .
2. 1 .8 Mi era-EXEC
The Micro-EXEC option is a unique hardware technique for
microstep sequencing of the computer. This option provides
hardware logic in which all computer control signals are
2-5

made available on an external cable connector so that
special hardware routines can be constructed. External
control and special return instructions are provided for easy
program entry and exit.
2.2 COMPUTER WORD
FORMATS
There are three basic word formats used in the DATA 620/i:
data, indirect address, and instruction. The instruction
word format is further divided into four types: single-word
addressing, single-word non-addressing, double-word
addressing, and double-word non-addressing.
2-6
2.2. 1 Data Word Format
The data word format is shown in figure 2-2. This word
may be either 16 or 18 bits depending upon the word length
configuration of the particular machine.
In the 16-bit format, the data occupy bit positions 0-14,
with the sign in position 15. Negative numbers are
represented in 21s complement form. In the 18-bit format,
the data occupy bits 0-16, with the sign in position 17.
2.2.2 Indirect Address Word Format
The indirect address word format is shown in figure 2-3.
This word occupies a location in memory which is accessed
by an instruction in the indirect address mode. Bit 15 con-
tains the I Bit. If I = 0, bits 0-14 contain the location of
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0
15'-1 S
L_~ _ ..L. _....L.- __________________ ~
1-------- Data (16) ----------'
1.--_+-- ____ Data (18) ------------'
fSign (negative numbers in 21s complement form).
-l.Logical data represented in true form.
1------ Sign (18-bit word length option).
Figure 2-2. Data Word Format

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a
r-T- II I Address
L_L_ .L._.....J.L.- _________________ ----'
118-.b~ L
option
{I =
0, word contains operand location
I = 1, word contains indirect address word location
Figure 2-3. Indirect Address Word Format
an operand or instruction in memory. If I = 1, bits 0-14
contain the locati on of another indirect address word.
Indirect addressi ng may be extended to any desired leve I.
Each level of indirect addressing adds one cycle (1 .8 micro-
seconds) to the basic execution time of an instruction.
2.2.3 Single-Word Instruction Formats
Single-word instructions may be either addressing or non-
addressing, as described in the following paragraphs.
Addressing instructions. The single-word addressing
instruction format is shown in figure 2-4. This type of word
contains three fields, as follows:
o - Opera tion code
M - Addressing mode
A -
Address field
All single-word addressing instructions may be executed in
anyone of five addressing modes: direct, relative to P
register, index with X register, index with B register, and
indirect.
Single-word addressing instruction groups are as follows:
LOAD/STORE
ARITHMETIC
LOGICAL
2-7