Vector Graphic Prom Ram III User manual

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U)E=i) mAnUAL .

PROM RAM III BOARD
Revision 1
PROM PROGRAMMING PROGRAM
Revision 1
USERS MANUAL
Revision A"
July 16, 1979

Copyright 1979 by Vector Graphic Inc.
All rights reserved.
Disclaimer
Vector Graphic makes no representations or warranties with respect to the
contents of this manual itself, even if the product it describes is covered
by a warranty or repair agreement. Further, Vector Graphic reserves the
right to revise this publication and to make changes from time to time in
the content hereof without obligation of Vector Graphic to notify any person
of such revision or changes, except when an agreement to the contrary
exists.
Revision Numbers
The date and revision of each page herein appears at the bottom of each
page. The revision letter such as A or B changes if the manual has been
improved but the product itself has not been significantly modified. The
da~e and revision on the Title Page corresponds to that of the page most
.recently revised. When the product itself is modified significantly, the
product will get a new revision number, as shown on the manual's title page,
and the manual will revert to revision A, as if it were treating a brand new
product. THIS MANUAL SHOULD ONLY BE USED WITH THE PRODUCT(S) IDENTIFIED ON
THE TITLE PAGE. (-/'
""-"--~ .

The PROM RAM III Board sold hereunder is sold as is , with all faults and
without any warranty, either expressed or implied, including any implied
warranty of fitness for intended use or merchantability. However, the above
notwithstanding, VECTOR GRAPHIC, INC., will, for a period of ninety (90)
days following delivery to customer, repair or replace any PROM RAM III
Board that is found to contain defects in materials or workmanship,
provided:
1. Such defect in material or workmanship existed at the time the
PROM RAM III Board left the VECTOR GRAPHIC, INC., factory,
2. VECTOR GRAPHIC, INC., is given notice of the precise defect
claimed within ten (10) days after its discovery,
3. The PROM RAM III Board is promptly returned to VECTOR GRAPHIC,
INC., at customer's expense, for examination by VECTOR GRAPHIC, INC., to
confirm the alleged defect, and for subsequent repair or replacement if
found to be in order.
Repair, replacement or correction of any defects in material or workmanship
which are discovered after expiration of the period set forth above will be
performed by VECTOR GRAPHIC, INC., at Buyer's expense, provided the PROM RAM
III Board is returned, also at Buyer's expense, to VECTOR GRAPHIC, INC., for
such repair, replacement or correction. In performing any repair,
replacement or correction after expiration of the period set forth above,
Buyer will be charged in addition to the cost of parts the then-current
VECTOR GRAPHIC, INC., repair rate. At the present time the applicable rate
is $35.00 for the first hour, and $18.00 per hour for every hour of work
required thereafter. Prior to commencing any repair, replacement or
correction of defects in material or workmanship discovered after expiration
of the period for no-cost-to-Buyer repairs, VECTOR GRAPHIC, INC., will
submit to Buyer a written estimate of the expected charges, and VECTOR ·
GRAPHIC, INC., will not commence repair until such time as the written
estimate of charges has been returned by Buyer to VECTOR GRAPHIC, INC.,
signed by duly authorized representative authorizing VECTOR GRAPHIC, INC.,
to commence with the repair work involved. VECTOR GRAPHIC, INC., shall have
no obligation to repair, replace or correct any PROM RAM III Board until the
written estimate has been returned with approval to proceed, and VECTOR
GRAPHIC, INC., may at its option also require prepayment of the estimated
repair charges prior to commencing work.
Repair Agreement void if the enclosed card is not returned to VECTOR
GRAPHIC, INC. within ten (10) days of end consumer purchase.

Repair Agreement
Table of Contents
Specifications •...•••••.••.•.••••.•.••••.•••••.•..•••..•.••••. 1 1
Description of the PROM/RAM III Board ••••••••••••••••••••••••• 1-3
2.1
2.2
2.3
2.4
2.5
Block A and Block B - General ••••••••••••••••••••••••••••••••• 2-2
Block A•• ~••••••••••••••••.••••••••••••••••••••••••••••••••••• 2 3
Block B••••••••••••••••••••••••••••••••••••••••••••••••••••••• ~-3
Figures 2 & 3 - EXamples of Block B Configurations •••••••••••• 2-5
Block Select Addressing ••••••••••••••••••••••••••••••••••••••• 2-6
PROM/Scratchpad Memory Invert ••••••••••••••••••••••••••••••••• 2-6
RAM Memory Address Select in Block B •••••••••••••••••••••••••• 2-7
Disable 3K of Address Space in Block B •••••••••••••••••••••••• 2-7
Power-on/Reset Jump - Description ••••••••••••••••••••••••••••• 2-8
Use PRESET or POC for Power-on/Reset Jump ••••••••••••••••••••• 2-8
Phantom Generated if Power-on/Reset ••••••••••••••••••••••••••• 2-9
Jump to PROM/RAM III Board if Power-on/Reset •••••••••••••••••• 2-9
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
Block Swap•••••••••••••••••••••••••••••••••••••••••••••••••••• 2 1 0
Disable Power-on/Reset Response ••••••••••••••••••••••••••••••• 2-10
MWR.ITE •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2 10
Wait Sta~e Generation ••••••••••••••••••••••••••••••••••••••••• 2-11
2.18 Programming a PROM - Normal Procedure •••••••.•••••••••••••••••• 2-13
2.19 Writing a PROM Programming Program •••••••••••••••••••••••••••• 2-16
2.20 Re-assembling the PROM Programming program •••••••••••••••••••• 2-17
2.21 PROM Programming Program Listing ••••••••••••••••••••••• 2-18 - 2-24
3.1 Addressinq •••••••••••••••••.••••.••••••••••••••••••••. _••••••••• 3 1
3.2 Data Inp:ut/Output••••'•••••••••••••••••••••••••••••••••••••••••• 3-2
3.3 Control Signals•••••••••••••••....••••....••••••• e .••••••••••••• 3 2
3.4 PR.OM Proqramminq ••••••••••••••••••••••••••••••••••••••••••••••• 3 3
3.4 Power Supplies ••••••••••••••••••••••••••••••••••••••••••••••••• 3 4

Board Layout ••••••••••••••••••••••••••••••••••••••••••••••••••• 4 1
Schematic Errata ••••••••••••••••••••••••••••••••••••••••••••••• 4 2
Schem.tic •••••••••••..•••.•••••••••••••••••••••••.•.•••••••••••• 4 3

Standard Location of
Systems Monitor PROM
RAM: 1K, included with the board
PROM: Sockets for 12 PROMs.
Listing included in manual
Executable version on MOOS System Diskettes
8.4 and later.
RAM: 300 ns.
PROM: User selected (450 ns. typ)
RAM: 2114 static
PROM: 2708 (1K each) or 2704 (1/2K each)
Two blocks (A and B) are separately
addressed
Block A has 8 PROM sockets
Block B has 4 PROM sockets and 1K RAM
Base address of the two 8K blocks
Block B PROM at top or bottom of block
Address of 1K RAM within remaining 4K
Disable unused 3K, for use by other boards
Block k disabled
Block B base address: COOOH
Block B PROMs: COOOH - CFFFH
Block B RAM: DCOOH - DFFFH
Block B disabled 3K: DOOOH - DBFFH

Power-on/Reset JumpOptions
(jumper) Use PRESETor POC
Jump to first instruction of Block A or B.
Disable phantom generation
Disable jump to on-board memory
Standard.power-on/Reset
Jumpers POCis used Jump to beginning of Block B
Phantom and jump to on-board both enabled
Jumper option to generate MWRlTEon board
Standar~ option not enabled
Jumper option to generate one wait state
each time board is addressed
Standard: option not enabled
+8Vdc @ 450 mA(Typ)
+18Vdc @ (depends on quantity of PROM)
-18Vdc @ (depends on quantity of PROM)
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Vector Graphic's PROMRAMIII Board is a versatile, S-100 bus compatible,
high density memoryboard combining the memory technologies of erasable
programmableread only memories (EPROMs)and high speed randomaccess memory
(RAM). Of unique value, one of the PROMsockets on the board can be used to
program a 2708 or 2704 EPROM,enabling any owner to create PROM-based
software for use on this board or in any other 1J icroprocessor device. 1Kof
RAMis provided on the board, but no PROMsare included with purchase. The
software which is used to program PROMsis provided as a listing in this
manual, and is included on disk with all Vector Graphic systems shipped with
this board.
By combining the use of MSIdecoding logic and unique addressing features, a
wide range of applications requirements may be met by this memory board.
The addressing flexibility is as follows. The board offers two
independently addressable 8Kblocks of memory(A and B). Youuse jumpers to
specify the two separate 8K addressing spaces assigned to these blocks.
Block A can be used for up to 8Kof PROM.Block B contains 1K of on-board
RAMplus up to 4Kof PRCM.
For block B, you use jumpers to specify' whether the PROMis at the top or
the bottom of the 8K allocation, and then, within the remaining 4K, where
the 1Kof RAMis addressed. Once this is done, there are also jumper
options for DISABLINGsome or all of the remaining 3Kof addressing space
allocated to block B, so that other boards in the system can use those
addresses.
The addressing spaces are fully utilized if 2708 1KPROMsare used. If 2704
1 2K PROMsare used, then every other 1/2Kof PROMallocation will be used,
with 1/2K gaps between. other features offered by the board are: jump on
power-on or reset to on-board memory,with phantom generated to temporarily
disable other memoryboards, and a jumper option to use PRESETinstead of
poe to cause this jump; jumper option for on-board generation of the S-100
MWRITEsignal;. and a jumper option to generate a one-cycle wait-state each
time the board is addressed.
Full buffering of all inputs and outputs is provided to minimize loading of
the system S-100 bus to at most one TTLload. On-board power regulation and
filtering is provided using IC regulators and heat sinks for power
dissipation. careful attention to good design practice and an awareness of
the need for flexibility has resulted in a reliable board useful in a wide
variety of systems and applications.

This Users Guide begins ·with a description of the amountand kind of PRat
which can be used on this board, followed by a description of the RAM
included with the board, then a detailed description of the various options
you have for addressing the PRats and the RAM. Read it before attempting to
re-jumper the board addressing. Following this section are a description of
each of the jumper options possible on the board, including addressing
options, power-on/reset jump, MWRITEinput, and wait state generation. The
diagrams of jumper pads showeach of the pads as it is pre-jumpered at the
factory. The guide ends with instructions for operating the PROM
programmingsoftware provided with the board, as well as instructions for
writing your ownif desired. The listing of the program is provided.
Amaximumof 12Kbytes (whereK =
in available sockets on the board.
THE BOARDALONE. Jumpers are
addressed.
1024) of 2708 type PROMsmaybe installed
NOPRatSAREINCLUDEDWITHPURCHASEOF
used to determine where the PROMsare
The following discussion. assumes that 2708 type PROMs(having 1Kof 8-bit
bytes each) are used. If 2704 PRQIs(having 1/2Kbytes each) are used, the
issues are the same, the only difference is that wherever a 2704 PROMis
used, there will be 1/2Kbytes of PRat accessible by the ·system, followed
immediately by a 1/2Kgap which will not contain any memoryat all.
The numbers 2708 and 2704 are Intel generic part numbers. Manyother
manufacturers make equivalents, with 2708 or 2704 as part of their
proprietary part number. All 2708 or 2704pin for pin equivalents can be
used on this board.
In addition to the PROMsockets, there is 1Kof static RAMon the board,
which IS included with purchase of the board alone. Jumpers are used to
determine where this 1Kof RAMis addressed.

To begin specifying the addresses for the memory,there are two seParately
addressable blocks of memoryspace available on the board, called blocks A
and B. Jumpers are used to specify what the base address is for each of
these two blocks, within a 64Ktotal memory space. Alternately, one (or
both) blocks can be disabled canpletely. Jumper area F is normally used to
specify the base address of (or disable) block A and jumper area E is
normally used to specify the base address of (or disable) block B. If a
block is not di~abled, then that block will occupy exactly 8K bytes of
memory, beginning at its base address. This is true for both blocks, as
shownin Figure 1.
FIGURE 1
Starting Address B Starting Address A
Note that both blocks together occupy 16Kof memory. However,there are
only 12 sockets for PRats, and only 1Kof RAMon the board, totalling 13K.
What happens if the processor .addresses memoryin the remaining 3Kportion?
This memoryspace is NOTnecessarily empty. A set of jumpers is provided
which in effect specify that the unused 3K, within the 16K, is not on the
PRat RAMIII board at all, and therefore maybe-used on other boards.
It must be emphasized that except for the 3Kspecified as unused by jumper,
the addresses assigned to the board for blocks Aand B cannot be used by any
other board, even if some of the PROMsockets are left empty. However,
rememberthat you maychoose not to use one (or both) of the blocks at all,
by disabling it completely in jumper areas E and F. If you do this, then
the corresponding memoryspace CANbe assigned to another board, and no
space is wasted.

If the jumpers in area G are switched from the way the board is normally
shipped, then the base address of block Awill be controlled by jumper area
E and the base address of block B will controlled by jumper area F, instead
of the other way around. If this is done, then the address which is
accessed for power-on jumpwill also be switched, beccining the first address
in block A instead of the first address in block B. This is the purpose for
using this option. (See Section 2.14) For simplicity of language, the
Users Guide is written assuming that jumper area G is left as manufactured.
Block A refers to the 8 PROMsockets at the top of the board (labeled 0
through 7). Insert PROMswhich. you want in block A into these sockets.
Socket 0 corresponds to the 1Kblock beginning at the base address of block
A. SOcket 1 corresponds to the next 1Kand so on, as shownin the following
table:
HexadecimalAddress
Relative to Base Address ("A")
of Block A
A + 1eOOH
A + 1800H
A + 1400H
A + 1000H
A + eOOH
A + 800H
A + 400H
A
Jumper area F is normally used to determine the base address of block A, or
to disable block A. Whenthe board is sold, jumper area F is pre-wired to
disable block A. No particular base address is thus specified until you
install the jumpers.
Block B includes the lower four PROMsockets on the board, labeled 8 through
11. The other 4Kin block B is filled with the 1Kof RAMon the board, plus
the 3Kof address space which can be, at you discretion, returned for use by

other boards. The wayyou specify the address spaces within block B is as
follows: First, you specify the base address of Block B using jumper area E
(or you specify in area E that the block is disabled). If it is not
disabled, then you use jumper area J to specify whether the 4Kof PROM
occupies the top or the bottom 4K of the block. These are the only two
choices. The board is pre-jumpered so that the PROMoccupies the lower 4K.
Then, you specffy using jumper area I which 1Kwithin the other 4K is used
for the on-board RAM. Lastly, you specify using jumper area R whether one
of more of the last three 1Kblocks is to be returned for use by other
boards. (Normally you specify that all three of them are returned.)
Twotypical configurations of Block B are shownin figures 2 and 3. Figure
2 is the standard - the one for which the board is pre-wired. Since in the
pre-wired version, block Bbegins at COOOR, Figure 2 shows that the standard
address for scratch-pad RAMis DCOOH, and the standard address for the
System's Monitor PRCM is COOOR. Figure 3 shows the result of putting the
PROMin the upper 4K and specifying that the RAMoccupy the second 1K
portion.

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Jumper names: A13, A13, A14, A14, A15, A15 ~ address lines
BA 1, BA2, BAJ • block B address pads
BB1, BB2, BB3 • block A address pads
NOT. The second letter in the block B address pads is A , while the
second letter in the block A address pads is B . This occurs because
historically, the pads were named before it was decided to manufacture the
board with the block swap jumpers in area G reversed.
Functiom Address lines A13, A14, A15 form the most significant bits of the
address from the CPU. These three bits can select any of 8 possible 8K
blocks of memory in a 64K memory space. see table 1.
Options: Table 2 tells you what jumpers to connect to specify any
Particular 8K block starting address.
ro
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Functiom The pre-wired connection specifies that the low order 4k bytes of
block B consists of PRCM. This jumper area is used to reverse this, putting
the PRCM at the high end of block B.
Options: If the PROM is to occupy the high order addresses of this block
cut the jumper from 6 to 7 and tie 6 to 8.

RAe
0
RA8
0
RA4
0
RAO
18
Function: These jumpers allow the user to selectively determine where the
RAMaddresses are to be located. With the board jumpered as manufactured,
the 1Kof RAMoccupies the top-most 1Kof addresses of the 4K scratchpad
memoryblock.
Options: If you wish to alter the factory supplied connections, the
following procedure is recanmended: Cat the jumper from 18 to RAC. Then,
determine the desired address for the 1KRAMfrom Table 3 and connect a
jumper as specified. The third part of Table 3 is not relevent to this
jumper area.
::i::~
o 17
Function: These jumpers allow the user to selectively determine which 3 of
4 1Kblocks of memoryare returned for use by other boards. These jumpers
are selected in conjunction with the RAMmemoryaddress jumper in area I, so
that together, all 4Kof the non-PROM(scratchpad) address space in block B
are accounted for. The factory supplied connections canplement the factory
supplied RAMaddress jumper, so that the bottom 3Kof the scratchpad memory
is allocated for use by other boards.
Options: If it is desired to alter the factory supplied connections, the
following procedure is recanmended: Verify the RAMmemoryaddress selected
previously. Then, refer to Table 3 to find the RAMaddress selected, and
connect jumpers as specified in the third part of the table.

A power on/reset jump feature is also provided on this board. When the iO'C
or PRESET (your choice of which, by jumper selection) line is low, the
instruction stored in the first address of block A or B (determined by the
jumper in area G, as explained below) will be executed by the CPU, and a
phantom signal will be issued by the board on bus line 67 which disables
other system memory boards.
After this initial instruction execution, the other memory boards will be
re-enabled. However, if the instruction is a jump to the next instruction
in the same block, then control will have been effectively transfered to
that block on the PROM/RAM III board. Therefore, the second instruction
should be the beginning of a system initialization routine followed by a
systems executive. This is always the case in standard Vector Graphic
computers.
Two additional jumper areas are provided, one to disconnect the phantom
signal if it is not desired, and the other to disconnect the jump to the
on-board PROM if this is not desired. These options give you maximum
control over use of the board.
JTIlo
Function: In the factory version of the board, the roc signal is connected
to the power-on/reset jump circuitry on the board. This is appropriate for
standard Vector Graphic canputers, because in these systems, both the RESET
switch on the front panel and the· initial poW'er-on condition cause an active
low pulse on the POC line, via circuitry on the Z80 board. If the CPU board
used in your system does not have this feature, the PRESET signal can be
connected to the power-on/reset circuitry by changing the jumper area D.
Options: To connect PRESET to the power-on/reset dircuitry, cut the trace
between 27 and 28 and tie 28 to 29.

rn
Function: When1 and 2 are tied together, the phantom signal is generated
whenever a POCor PRESETsignal is received. Phantomdisables other system
memoryboards. The zao (and 8080) processor chip immediately executes the
instruction at OOOOH when the POC or PRESETsignal appears on the bus,
assuming the CPOboard is so designed. With the other memoryboards in the
system disabled, the PROM/RAMIII Board is free to supply the instruction
for address OOOoH.
Options: To disable the generation of the phantom signal, cut the jumper
from 1 to 2.
sO
A
Function: Whenthe POCor PRESETsignal is received, a jumper in area A
causes the board to respond to the address OOOoH from the CPU. At your
option, you maydisable this feature, so that the PRat/RAMIII board is NOT
the board which responds to the address oOooH.
Options: To cause the board NOTto respond to address OooOH when POCor
PRESETis received, cut the jumper from 3 to 4 and tie 4 to 5.