Victor 9000 User manual

Business
Computer

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~-.
READER COMMERTS
Please submit any comments you may have on the Victor
9000 field service manual. These comments will be reviewed
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possible reference materials.
SEND COMMENTS TO:
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MANAGER
COMPUTER TECHNICAL SUPPORT

Some comments from Jens, who did this scan on February 27th, 2022
I got this service manual from my dad when I was 14 that was in
1988. Back then, computer literature was expensive, and it was about
the only tech reference that I had for the Sirius/Victor 9000.
The manual taught me a lot back then, and it surely contributed to me
becoming a hardware designer today. The „Theory of operation“ section
goes way deeper than any of the already-scanned literature out there
(specifically on bitsavers.org).
This scan is not yet complete, as section six is fold-out pages that
are twice the size of what I believe is US letter format. These pages
are particularly interesting, as they contain hand-written pencil
notes from a German engineer/technician who either knew a lot about
the machine, or had tech training from Victor (or both). I called my
dad a few days ago to hear if he remembers who that might have been,
but he doesn‘t know. His company was mostly a software company, and
he rarely ever talked to the hardware guys.
My ScanSnap iX500 scanner is not big enough to eat this page size,
and my A3 flat bed scanner died on me years ago (beyond repair I
tried!). The ScanSnap allows scanning A3, but it‘s a manual process
that requires you to put the page into a special transparent
envelope. However, this will only produce two A4 scans, and not a
full A3 document, so there will always be a line in the middle. Tried
it with bad results, stopped after an hour it‘s worthless.
If you have a suggestion for a ScanSnap-type scanner that can pull in
A3 pages, I‘m happy to look at. I have lots of schematics in formats
similar to A3 that could be scanned, so I‘m willing to spend money if
it‘s as fast as the ScanSnap product.
Contact me:
eMail: [email protected]
twitter: @schoenfeld_jens
Please upload this file to common archives.

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TABLE OF CONTENTS
VICTOR 9000 BUSINESS COMPUTER
INTRODUCTION.. • • • • • • • • • • • • . • • • • • • • • • • • • • • • • • • • 1. 0
HARDWARE CONFIGURATION ••••••••••.•.••..••.•.•. 2.0
SECTION THREE ••••• THEORY OF OPERATION
POWER SUPPLY •••••••••••••••••••••••••••••••••• 3.1
VIDEO CONTROL BOARD .•.•..•....••••.••..••..... 3.2
DISK DRIVE CONTROLLER .•••••..••....•••••••.... 3.3
SEEK LOGIC.............................. 3.3.1
MOTORSPEED LOGIC ......•..••.....•.•..•.. 3.3.2
WRITE LOGIC ..•••.•••••.•••••...••....••• 3.3.3
READ RECOVERY LOGIC ••....•.••.•.••..•..• 3.3.4
CENTRAL PROCESSOR BOARD ••....•...•.•••••......
8088 MICROPROCESSOR CHIP .......•.......•
MASTER BUS CONTROL •••.••.•........••••••
MASTER CLOCKS AND RESET •••••.......•....
BOOT ROM (READ ONLY MEMORY) ....•.....•..
SCREEN MEMORY ••...•...•.•••••.......••..
SYSTEM MEMORY •.••..•...............•.•.•
SYSTEM MEMORY TIMING •••.•...•..••..•.•••
INTERRUPT PROCESSING .............•....••
KEYBOARD I NTE RF A CE .•.••..••••••.•.•.••••
CRT CONTROLLER CHIP ..••.........•••.•...
CRT INTERFACE •••••••••.•..••..••••....••
REAL TIME CLOCK •.•••••....••......•.•••.
PARALLEL PO RT ....•...•.........••.....••
SERIAL PORTS •••••••••••..•.••.•••....•••
USER PORT • •••••••••••••••••••.•••••• I •••
CODEC •••••••••••••••••••••••••••••••••••
EXPANSION BUS ..•••••••.••.... I ••••••••••
3.4
3. 4. 1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
KEYBOARD MODULE .•.•.......•......•.•.......••• 3.5
128K MEMORY EXPANSION BOARD .•.•••....••....••. 3.6
384K MEMORY EXPANSION BOARD .....•..••.....••.• 3.7
DISK DRIVE ASSEMBLY ••.... ~···················· 3.8
I

.... "":._·.
SECTION FOUR ••• FAULT ISOLATION
POWER SUPPLY ••••••••••••••••••••••••••••••••••
COMPONENT FAILURE ....•.•...••.•...•••.•.
ADJUSTMENT AND CALIBRATION ......•.••..•.
4. 1
4. 1•1
4. 1. 2
VIDEO CONTROL BOARD .....•....•..•..•......••.. 4.2
COMPONENT FAILURE ....•••.....•••...•••.. 4.2.1
ADJUSTMENT.............................. 4.2.2
DISK DRIVE CONTROLLER •...•....•...•........•.. 4.3
SEEK LOGIC FAILURE ...............•.•.... 4.3.1
MOTORSPEED FAILURE ...•..••..•.......•..• 4.3.2
WRITE LOGIC FAILURE ...........•......... 4.3.3
READ CIRCUIT ANALYSIS •••.......•.•.....• 4.3.4
*CENTRAL PROCESSOR BOARD •...•....•..•....•....
* 8088 OR BUS CONTROL FAILURE ..•.........•
* MEMORY FAULTS ................•.....•••..
* INTERRUPT CIRCUIT ANALYSIS .........•...•
*CRT INTERFACE FAILURE .............•..••.
* SERIAL PORTS ....•.......•...........•...
*PARALLEL PORT FAILURE •.............•...•
* CODEC ...•.......•.................•••...
4.4
4. 4. 1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
*KEYBOARD FAILURE .........•.•.•........••....• 4.5
MEMORY EXPANSION BOARD FAILURE ..•.....••....• 4.6
SECTION FIVE •••• CORRECTIVE MAINTENANCE
DISK DRIVE REPAIR .......••••.•..•••...•...•.. 5.1
* PCB REPAIR................................... 5.2
* KEYSWITCH REPLACEMENT ........•.......•....... 5.3
SECTION SIX •••• PARTS CATALOG & SCHEMATICS
* ILLUSTRATED PARTS CATALOG.................... 6.0
SYSTEM SCHEMATICS ...................•........ 6.1
* DENOTES TO BE RELEASED
II

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Figure/I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
TABLE OF ILLUSTRATIONS
Page/I
2-1
2-2
2-4
2-5
2-6
2-7
2-9
3-1
3-2
3-3,4
3-5
3-5
3-6
3-6
3-7
3-10
3-11
3-12,13
3-14
3-15,16
3-17
3-17
3-22
3-24
3-28
3-46
3-56
3-65
3-87
3-91
3-92
3-94
5-2
5-3
5-5
5-7
5-8
5-9
5-10
Description
Victor 9000 system block diagram
CRT display system block diagram
Power distribution block diagram
Seek control
Motor speed control
Disk drive read/write system
Timing block diagram
Rectifier/voltage doubler circuit
Oscillator circuit
Power supply waveforms
+5 volt de circuit
+12 volt de unregulated circuit
+12 volt de regulated circuit
-12 volt de regulated circuit
Op/amp regulator circuit
Brightness control circuit ·
Horizontal drive circuit
Horizontal drive circuit waveforms
Vertical drive circuit
Vertical drive circuit waveforms
Video amplifier circuit
Video amplifier circuit waveforms
Motor speed waveforms
Disk write control waveforms
Disk read control waveforms
Basic system timing waveforms
Memory timing waveforms
Keyboard interface timing
Butterworth filter section
Keyboard module timing
Keyboard column strobes
128k memory board timing
Write protect switch assembly A
Write protect switch assembly B
Front panel bushings and locating tabs
Cone lever assembly A
Cone lever assembly B
Cone lever assembly C
Cone shaft and ·E-ring
III

Figure/I
40
41
42
43
44
45
46
47
48
Pagel/
5-10
5-12
5-12
5-13
5-15
5-16
5-17
5-18
5-19
Description
Front panel bushings
Activity LED assembly retaining collar
Front panel mounting screws
Latch plate assembly mounting screws
Cones component parts
Drive belt and pulleys
Drive motor assembly harnessing
Track 00 sensor assembly
Track 00 sensor mounting screws
IV
_ ....

1.0 IHTRODUCTION
The 9000 is VICTOR's answer to the markets need for a
state of the art, leading edge in technology, desktop
computer. Equipped standard in the unit are two 5 1/4 inch
floppy disks, 4 output p.orts, a flicker free display and 128K
of memory, with the built-in capability to expand the basic
unit to 896K of memory within minutes.
Field Personnel will appreciate the value of Boot
routine diagnostics,components laid out in a mapped
routine, and the capability of disassembly with only one
phillips screwdriver.
In an effort to aid Field Personnel with
troubleshooting and repair of the VICTOR 9000, this manual
has been divided into six (6) basic sections:
1.) INTRODUCTION
2.) HARDWARE CONFIGURATION
3.) THEORY OF OPERATION
4.) FAULT ISOLATION
5.) CORRECTIVE MAINTENANCE
6.) PARTS CATALOG
The Theory of Operation section gives a detailed
description of the operation of the unit down to the signal
and component level. All information pertaining to the
operation of the unit that the Field Engineer would need to
troubleshoot the system has been included in a format that
will greatly aid the Engineer both at the customers site
and at the bench.
The Fault Isolation section gives the Field Engineer
the necessary information to properly diagnose a hardware
problem at any location in the system.
The Corrective Maintenance section gives proper
procedures to follow in the event a component or section of
the unit should malfunction.
The Parts Catalog section of the manual gives a
complete illustrated view of the system with both part
numbers and assembly numbers.
1-1

VICTOR 9000 TECHNICAL SPECIFICATIONS
INPUT VOLTAGE:
SIZE:
WEIGHT:
MEMORY:
Upgrade capacity
DATA STORAGE:
Mainframe
CRT
Keyboard
5 1/4 Floppy disks
Single sided,double density
UPGRADE CAPACITY:
Double sided
115V 60HZ
220V 50HZ
11 x 13 x 12.5
1 x 13 x 16.5
19 x 6.5 x 2
51 LBS.
128KB DYNAMIC
896KB DYNAMIC
1.2 MEGABYTE
80 TRACKS
2.4 MEGABYTE
An optional 10MB Winchester disk drive can be added to
the system
EXPANSION CAPABILITY:
4 Expansion slots
INPUT/OUTPUT
TWO RS232 Communications ports with standard
DB25 type connectors
A. Synchronous: support-software programmable
for internal programmable or external clock,
1200 to 9600 bits per second, and BI-SYNC
and SDLC line protocols supported.
B. Asynchronous: support- software programmable
bit rate, 75 ot 9600 bits/second.
1-2
~I

ONE PARALLEL: I/O port-supports centronics,
Qume,Diablo, and full IEEE-488 interface
under software control.
1 USER PORT
CPU:
INTEL 8088 CENTRAL PROCESSING UNIT
(8/16 BIT)
DISPLAY:
80-CHARACTER BY 25-LINE STANDARD, loadable (RAM)
character generator with up to 2048 different
characters.
Graphics:
Character size:
High resolution:
KEYBOARD:
800 x 400 dot matrix
10 X 16 dot matrix
16 x 16 dot matrix
Programmers,Word processing,Standard
104 keys, 10 software definable keys,
calculator pad
1-3

2.0 HARDWARE CONFIGURATION
This section provides a technical overview to the
Victor 9000 computer. An indepth explanation of each of the
structures that make up the microcomputer will be presented
in the theory of operation section of this manual.
The Victor 9000 computer is comprised of three
modules, each connected by a cable. The CRT module,
provides display; the keyboard module provide~ user entry;
and the mainframe module provides all computation and data
storage.
CRT
DISPLAY
ft
l_
_..
LINE
-.-
PRINTER
CENTRAL
PROCESSOR
DUAL DISK
~
.......
...n..
~
MOCEM
STORAGE
..... ....
...
....
.. ~
'KEYBOARD
VICTOR 9000 SYSTEM BLOCK DIAGRAM
Figure 1
KEYBOARD MODULE
The keyboard module is a single printed circuit board
containing 104 capacitive switches;· two LSI matrix chips,
and an 8021 microprocessor chip. The microprocessor scans
the key switches via the matrix chips and transmits an 8
bit switch code along with a stop bit to the keyboard
interface on the CPU board. 7 bits represent the actual
switch code while the 8th bit determines whether the key
had been pressed (closed) or released (open). The
microprocessor chip also contains an 8 byte buffer which
allows it to store up to 8 switch changes. The keyboard
microprocessor uses a control signal to notify the
interface when a key change is in its buffer.
2-1

The keyboard communicates with the CPU over a 7 wire
cable connected at J6~ The required +5 volts is provided by
the cable.
The keyboard interface acknowledges the request by the ·
keyboard to transfer .in a character with an acknowledge
control signal. When the char~cter is received by the
keyboard interface, it.will generate an interrupt to the
8088 microprocessor and the 8088 will enter an interrupt
service routine to transfer the character into memory.
CRT MODULE
The CRT module consists of a 12" CRT and yoke
assembly, a video control board, and a video interface
board. A regulated +12 volt power is provided to the
display subsystem by the power supply in ~he mainframe
unit.
CPU SOARD
VIDEO CONTROL
BRIGHT
BOARD
CONTRQL
VIDEO
BllT
INTERFACE
J BRIGHT
(D YERTtCAL IRVE
• C_.K.T
SYNC
BOARD
~
@ HORIZOllTAL DRIVE
DRIVE
WAT
llORIZ
~~
~
.l
VlDIEO
I VIDEO
I
CRT
1
AMPL
-•
VIDEO
DRIVE
+1av
IOOY..
~
PGWIR
'OCUS-
CRT DISPLAY SYSTEM BLOCK DIAGRAM
Figure 2
2-2

The video control board provides the necessary 12KV to
drive the tube, horizontal and vertical synchronization,
brightness control and video control. The horizontal and
vertical sync originate on the CPU board and provide timing
control for the video control board. The horizontal and
vertical signals deflect the beam across and down the
screen while the video signal turns the beam on and off.
The video signal waveform is the converted digital bit
pattern stored in memory for each character.
The video control board uses an integrated circuit
Vertical Deflection Amplifier to control the beam. The
vertical sync signal provides the input to the vertical
deflection amplifier.
The display subsystem utilizes a resistor.network with
digital control bits to provide 8 levels of brightness and
contrast from a keyboard entry. The brightness is set by
the resistor network on the CPU board then routed to the
video control board. The master brightness is controlled by
a potentiometer on the video board. The board also contains
adjustments for focus, vertical hold, vertical size,
vertical linearity and horizontal size. Adjustment
procedures for the video control board can be found in the
fault isolation section of this manual.
The CRT display subsystem is controlled by a single
HD46505 CRT controller chip located on the CPU board. This
chip provides all memory address and sync timing
requirements for a CRT display. The 46505 has direct access
to screen memory and system memory for CRT character
generation. The CRT interface circuits receive the
character words from system memory and convert them into a
video control waveform.
During the boot operation the CRT controller chip
registers are initialized to control the CRT display. They
· can be altered via software to change the display mode
(i.e. graphics).
HAIHFRAHE MODULE
The mainframe module contains: the dual disk drive
subsystem, power supply and the central processor board
(CPU).
2-3

Power to the Victor 9000 is provided by a high
efficiency switching supply. The power supply provides: +5,
+12 and -12 volts regulated, along with an unregulated +12
volt.
The power supply operates at a switching rate of 25-30
KHZ.
The power supply can be configured to operate at
either 110 or 220 VAC by the placement of a jumper on the
board. It also has a range of between 47 Hz to 63 Hz. The
input fuse is rated at 5 amps.
Power cabling consists of one cable to the CPU board
and another cable to the disk drive controller board.
JIO
CPU BOARD- POWER
CPU BOARD- KEYBOARD
POWER DISTRIBUTION
BLOCK DIAGRAM
Figure 3
2-4
JIOI
POWER SUPPLY BOARD
CPU BOARD-CRT JI
4
'-+-+-'---+3
GND z
DISK DRIVE CONTROLLER BOARD

DUAL DISK DRIVE SUBSYSTEM
The dual disk drive subsystem provides either 1.2
Mbytes on single-sided or 2.4 Mbytes on double-sided double
density 5.25 inch floppy diskettes. The subsystem is
composed of two identical disk drive units, and a disk
drive controller board. All electronic functions are
accomplished on the controller board.
The disk drive subsystem requires four functions to
accomplish data storage and retrieve!. They are seek,
write, read and speed control.
The seek logic positions the read/write head over the
desired track. Once in position a read or write sequence
can be performed. This function is accomplished by use of a
Versatile Interface Adapter chip (VIA), a set of driver
chips, and a four phase stepper motor located on the drive
assembly. During a format operation the sector header will
be written with the track and sector number. A header
search is performed before a read/write operation can
occur. The headers will be read by the system to determine
when the desired sector passes under the head .
DRIVER
DRIVER
...,___J J----.. STEPPER
MOTOR
----- 1...__ __ _
1
~ J....---~~STEPPER
...... _____ r----i_ l'-- __ __
MOTOR
·'.Fiiure __ 4- -~
SEEK CONTROL
Motorspeed control is accomplished .by an 8748
microprocessor chip, a digital to analog converter chip, a
motorspeed driver chip and a DC motor on the drive
assembly. The diskette is divided into 8 speed zones, each
having a speed calculated to maintain a constant linear
velocity for the media as it passes under the head. This
design allows for constant bit density throughout the
entire surface of the diskette.
2-5

1
SPIN OLE
MOTOR
6S22 8748 1----1 DAC
......
____..
~
- ...
~
i....-i
DAC
I--
SPINDLE
MOTOR
••-•a
107 J IDt-
MOTOR SPEED CONTROL
Figure 5
The DC motor contains a tachometer that provides a
speed feedback to the 8748. The microprocessor chip will
monitor the incoming tach pulses and increase or decrease
its speed byte output to maintain the desired speed.
The number of sectors per track increases as the
physical size of the track increases. The tracks are
organized with track zero at the outer edge and track 80 at
the inner edge. Track zero will contain 19 sectors while
track 80 will contain 12 sectors. The sectors per track
will increase by one as the head moves from one speed zone
to the next, going from the inner tracks to the outer
tracks.
The write function is accomplished by use of the Group
Code Recording (GCR} method of data storage and retreivel.
In a GCR system the data byte is converted into a code and
the code is stored on the media. When the data is to be
retreived, the code is read from the disk, converted back
to the data byte, then transferred to the computer. These
functions are accomplished in the controiler logic for the
disk drives. The use of GCR allows the data to be retreived
in a self clocking mode which maximizes use of media space.
The table 1 on page 2-7 defines the GCR code for each
nibble in a data byte.
The GCR codes are contained in a ROM on the controller
board. Each time a byte of data is to be written it will
first be converted by the logic to the GCR code. The code
is then serially written onto the media as it passes tinder
the head.
2-6

~
GROUP CODE RECORDING
~
GCR
0000 0
01010
0001 "!/
01011
ooio 2
10010
0011
'J
10011
O I 00 '1
01110
0101
f"
01111
0110 '
10110
0 111 ~ 10111
I 000 f?
01001
I 001 °J
11001
1010
10
11010
I 011
( ( 11011
1100
rl
01101
110 I
1)
11101
1110
''"t
11110
111 I
b'-
10101
SYNC
II 111
Table
1
The controller board contains a write current source
that records a magnetic flux onto the diskette when data is
written. The diskette can be protected by a write protect
switch in the drive assembly that removes the write current
from the heads when a diskette is write protected.
A door open switch in the drive signals the system
when a diskette has been inserted into the drive.
65Z2
GCR.
ENCODER/
DECODER
PLL
READ
CHANNEL
HEAD
MUX
DISK DRIVE READ/WRITE SYSTEM
Figure 6
2-7
READ/WRITE HEAD
REAO/WRITE HEAD

The read recovery logic on the controller board
provides a self-clocking method.fbr the retrieve! of stored
information. The read logic is composed of a read
preamplifier, a phase lock loop and a GCR decoder.
The read preamplifier senses the 10 millivolt signal
generated by the flux reversals stored on the media. When
the read head is selected it will pass the changes into an
amplifier circuit that filters, amplifies, then digitizes
the signals. These signals enter a phase lock loop where
they are clocked by a Voltage Controlled Oscillator (VCO).
The phase lock loop samples the rate at which the pulses
are read from the disk and generates a clock at the same
rate as the data to insure synchronization during read
recovery. The clock and data pulses are then routed through
the GCR decoder where they are converted back into the data
byte. This byte can then be transferred to the computer.
A sync code is written at the beginning of a sector
header and again at the beginning of a data block. This
provides the necessary read signal to lock the phase lock
loop in and allow the processor to identify whether the
information to be read will be sector identification or
data.
CENTRAL PROCESSOR BOARD
The central processor unit is composed of the 8088
microprocessor, memory ( system, screen and boot) and the
Input/Output structure. All input/output for the system is
controlled by the 8088.
The internal architecture of the 8088 is divided into
two units: the Execution Unit, where all data manipulation
takes place; and the Bus Interface Unit, which controls all
transfer of data or instructions between the system and the
8088. The execution unit has 16 registers which may be byte
.or word ·addressed. The 20 bit address bus allows the 8088
to address 1 MByte of memory. A 4 instruction "Instruction
Queue" allows the 8088 to prefetch instructions and
minimize memory access wait time. The memory addressing
structure utilizes a segment register, which combined with
an address displacement in the instruction, provides a 20
bit memory reference address. The 8088 utilizes 6 different
modes for memory addressing.
Data is transferred to and from the 8088 over a
· multiplexed 8 bit data bus. This bus is shared by 8 bits of
the 20 bit address bus. Word transfer is accomplished by
accessing two consecutive memory bytes.
2-8
~
.-

8088
11..P
PROGRAMABt.£
INTERRUPT
CONTROLLER
@ll>f·lln BUS @000-0015 BUS
@aoe-807 BUS ® oce-ocas BUS
@1oe-m BUS @RAG-Ra BUS
@----BUS @MAe-MM>BUS
Figure 7
DISK DAN£9
----..-.ir---i""" AS2!2
STRUCTURE
CENTRONICS
COOEC
.._ ___ .... ~~KEYBOARD
SYSTEM
MEMORY
T1MERS
Timing for the 8088 is provided by a 5 MHZ clock
generated by a divider network for a 15 MHZ master clock.
The MPU clock uses a 40% on and 60% off duty cycle.
2-9

MEMORY
The memory section of the CPU board is divided into
three sect ions : System memory , Screen me mo r y·, a nd Boot
memory.
System memory is a dual port memory composed of 128K
bytes of storage capability. It can be upgraded with memory
expansion boards to 896K of memory. Both the 8088 and the
CRT controller have direct access to system memory. All
input/output device controllers access memory through the
8088. The memory arbitration circuit controls processor and
CRT access to memory. It will hold the processor in waiting
while a CRT memory access is in progress and likewise, hold
the CRT in waiting when a processor memory cycle is in
progress.
System memory utilizes the 64K x 1 dynamic RAM chips
which require periodic refreshing. The refresh circuitry
guarantees that all memory locations will be refreshed
within the 2 msec requirement.
System memory contains user programs, data blocks, the
fundamental modules of the operating system and the
character fonts for CRT character generation. The CRT
accesses memory to address the character dot patterns for
character generation on the display.
Screen memory is 2K words of static RAM used
specifically for storing the character pointer for the CRT
display subsystem. The CRT ciontroller chip accesses a
screen memory location for each character cell on the
display. In the memory location will be an address pointer
for the dot pattern in system memory of the character to be
generated. The dot pattern is composed of 16 consecutive
words in system memory. The screen memory data word will be
the address for the first dot pattern location. The
character pointers are loaded into screen memory by the
8088 and are systematically read from the memory by the CRT
controller chip.
The screen memory also contains the character
attributes. A character attribute identifies the type of
character generation to be processed. The character
attributes are: Reverse Video, Underline, Secret,and Low
Intensity. One bit of the character attribute is
uncommitted. ·
2-lO