Circle
241
on
inquiry card.
DA.TA
PLOTTING
SOFTWARE
FOR
MICROS
'
'''
..
l
yt
I(lI
Iff4
~
P\Jtlr
u
1'" Mil ,
1
""
015>-1
It
"IIUII
,U
I~
m.~
rtI11
'.
I
~
tO~
,
!~9
ro
v,~
I~
IR\
Ol
ll.
$ IC
,l
.I'
!.
21
Programs
Fully
Documented,
Copyable
BASIC
listings
Apple
II
and
IBMpc
PIE CHARTS • BAR CHARTS
STOCK MARKET CHARTS
3D SURFACES • HISTOGRAMS
LOG PLOTS • CURVE
FiniNG
REGRESSION ANALYSIS
DATA MANAGEMENT
STATISTICAL ANALYSIS
TEXT ON GRAPHICS
All
programs listed
in
Applesoft BASIC
in
a
248
pg
book with theory, equation
s,
f
ull
ex-
planation
of
how they work. Mod
ul
ar
and
menu driven. Use
as
is
, modify
and
combine
for your own applications, or use
as
building
blocks to develop your own programs. Op-
tional 5y." disks
of
listings availble for Apple
II
+
00S3
.3
48K
and IBMpc
00S1
.1
48K
.
Th
is is your best buy
in
data plotting software!
Book
:
$28
.
50
Disk
:
$19.95
ALSO AVAILABLE
Graphic
Software
for
Mlcros
:aself-teaching guide
to writing
20
and 3D graphics software-61
programs-H
_.
the
best
book
available
on
micro
graphics
..
"-Creative Computing 2/
82
.
Book
: $21 .
95
Disk:
$19
.
95
Engineering
Software
for
Micros
:
25
programs
for CAD, Fourier analysis, optimization, etc.
Book
:
$28
.
50
Disk
:
$19
.
95
Structural
Analaysls
Software
for
Micros
:
14
programs-20,
30
trusses, frames & more.
Book:
$39
.
95
Disk
:
$24
.
95
KERN PUBLICATIONS
Send check, money order,
VISA/MASTERCARD
no with
exp date to 190
Du
ck
Hill
Rd
,
PO
Bo
x
1029
,
Du
xbury,
MA 0
2332
. Add
$2
per book post
ag
e
In
US,
$3
UP
S,
$4
Canada, $12 air Europe and Central America,
$1
B
elsewhere. Specify Apple or IBM with disk orders.
For
faster delivery
cali
(617)934-0445
230 November 1982 ©
BYTE
P
ub
lica
ti
ons Inc
Pin Signal 1
/0
Description
50
A19 1/0
Bu
ffered-address bits 8 to
19
.
Th
ese
1 A18 1
/0
l
in
es
are driv
en
from the 8088 during
49
A1
7 1
/0
normal operation a
nd
are v
al
id from
2 A16 1/0 the falling edge of address-latch
48 A15 1
/0
enable
(A
LE
) to
th
e
ri
sing edge of t
he
3 A14 1
/0
next
ALE
. If an external device takes
47
A13 1
/0
control of the system v
ia
HOLD
an
d
4 A12 1
/0
HOLD AC
KN
OWLEDGE, the
se
lines
46 A
11
I
/O
are tri-stat
ed.
5 A10 1
/0
45
A9
1/
0
6
A8
I
/O
29
BD
7 I
/O
Time multiplexed buffered addressl
22
BD
6 I/O data bus. During normal operation,
28 B
D5
1
/0
the lower 8 bits of addre
ss
(
AD
O-
23 B
D4
I
/O
AD7) are
va
lid
on
the falling edge of
27
BD
3
I/
O A
LE
.
24
BD
2
I/
O
26
BD
1
I/
O
25 B
OO
I/O
9 ALE 0 Buffered addre
ss-
latch
en
a
bl
e.
Pr
ocessor s
ig
na
l that indicates
BDO
-
BD
7 contain
va
lid addresses. Typically used to l
atc
h low-
order 8 bits of address.
11 RD 0 Buffered read strobe.
Pr
ocessor
si
gnal indica
ti
ng
'a read cycle.
14 WR 0 Buffered write strobe. Processor signal
in
dicating a w
ri
te
cycle.
8 D
EN
0 Buffered data enab
le
.
Pr
ov
id
ed by the processor for use
as
an
enable for transceive rs.
33
DL
ATCH 0 Data latch. The falling edge of this signal m
ay
be used
to
strobe data ge
ne
ra
ted from a processor read access.
30 EX
TI
O External I/O. Contr
ol
line that prevents internal data-bus bu
f-
fers from conflicting with external buffers when mapping ex-
ternal I
/O
in
to address s
pa
ce E
OO
OO
to EFFFF hexadec
im
al.
CS
EN
should be u
se
d as a control signal to di
sa
bl
e inte
rn
al
buffers via EXTIO and enable external buffers if
us
in
g address
space
EOOOO
to EFFFF. Addresses used
by
t
he
system cannot
be
disab
le
d by EX
TI
O.
19
CS
EN
0 Chip
se
lect ena
bl
e.
This line is
sy
nchronized to
PH
AS
E
2.
It is
true from a
fa
lling edge of
PHA
SE2 to
th
e next
fa
ll
ing
edge of
PH
AS
E
2,
when a
dd
ress s
pa
ce E
OOOO
to EFFFF
he
xadecimal
is accessed.
40 CLK15B 0 1
5-
MH
z clock. S
ign
al from which all system timing
is
derived.
Its pe
ri
od is 66.6 ns with a 5
0%
± 1
0%
duty cycle.
38 CL
K5
0
5-M
Hz clock. Signal is
in
ph
ase with the 8088 clock input. I
ts
period
is
200
ns
with a
33
% duty
cyc
le.
20
PH
AS
E2 0 1-MHz clock. Signal
is
asynchronous
wi
th
CL
K5.
Its period
is
11'
s with a 40/60% duty cycle. Useful to interface 6800
-t
ype
I/
O circuits.
21
XA
CK
External acknowledge. This line
is
no
rma
ll
y hi
gh
an
d may
be
pulled low by exte
rn
al devices r
es
ult
in
g in p
ul
li
ng
the 8088
READ
Y input low, generating wait s
ta
tes.
This line is resyn-
chro
ni
ze
d by the system logi
c.
17 HO
LD
Input to the 8088.This is an
ex
te
rn
al
requ
es
t for control of t
he
s
ys
tem buses.
18
HLDA 0 Buffered ho
ld
acknowledge.
Sys
tem r
es
pon
se
to
HO
LD
r
e-
q
ue
s
t.
Wh
en true (high) the fo
ll
owing signals are tri-stated:
A8-A19,
BD
O-
BD7, A
LE
,
10
1M,
RD
,
WR
,
DT
IR,
DEN
, SSO, and
I
NT
A
DLATCH is contro
ll
ed by external
log
i
c.
41
RE
ADY 0 Status line. This line reflects
th
e
sy
nchroni
ze
d
READ
Y
in
put to
th
e 8088.
10 10iM 0 Buffered 8088 sta
tu
s l
in
e.
Di
stinguishes between a memory or
I
/O
bus cycle.
7
SSO
0 Buffered 8088 status line.
Conti
nued on page 234
Tabl
e 1: The s
ig
nal names and descriptions for the Victor 9000 expansion
bus
. The
expansion bus
is
basi
ca
ll
y a buffered extension of the
sys
tem's 8088 processor plus
add
itional timing
and
co
ntr
ol signals re
quir
ed to interface the
sy
stem. The expansion
bus consists
of
a
mult
iplexed buffered data
bu
s (BDO-BD7
),
a buffered
addr
ess bus
(A8-A
1
9)
,
and
va
ri
ous timing, control, interru
pt
,
and
p
owe
r lines.