Wave Mate Z80 Super Bullet User manual

WAVE MATE Z8D
SUPER BULLET MANUAL
This manual contains user information on the WAVE r~TE Z8D SUPER
BULLET Microcomputer. Its contents are proprietary and may not
be reproduced, in whole or in part, without written authorization
of WAVE MATE, Inc.
2-16-84

I INTRODUCTION
II DESIGN PHILOSOPHY
III HARDWARE DESCRIPTION
A. Physical Considerations
B. Electrical Requirements
C. CPU, DMA, and Interrupt System
1. Central Processing Unit (CPU)
2. Direct Memory Access (DMA) Facility
3. Priority Interrupt Structure
4. I/O Port Assignments
D. Memory System
1. Random Access Memory (RAM)
2. Read Only Memory (ROM)
3. Erasable Programmable Read Only Memory (EPROM)
E. I/O System
1. Hardware Status Register
2. Floppy Disk Controller/Formatter (FDC)
3. Dual Asynchronous Receiver/Transmitter (DART)
4. Serial Input Output (SIO)
5. Counter Timer Circuits (CTC)
6. Parallel Input/Output Controller (PIO)
7. Centronics Printer Port
8. SCSI Bus Interface
IV I/O CONNECTORS
V SYSTEM SET UP
A. Switches and Jumpers
B. Serial Cable Information
C. Connecting Floppy Disk Drives
2-16-84 1

I INTRODUCTION
The Wave Mate SUPER BULLET is a fast, compact and very powerful
single board computer (SBC). The SUPER BULLET provides an 8
megahertz Z80H CPU, 256K bytes ,of random access memory (RAM), up
to 16K bytes of erasable programmable memory (EPROM), 4 RS-232-C
serial ports, a Centronics printer interface, a diskette
interface (supporting four 8", four 5", and two 3" drives) and
SCSI bus interface for Winchester disk controllers. This 8
megahertz Z80H, along with powerful direct memory access
controllers (DMA) for data transfer and a greatly enhanced
C-BIOS, executes CP/M PLUS at a previously unheard of speed.
Video display communication is provided through one of the
RS-232-C ports, to which many different serial terminals may be
attached. Future I/O expansion is provided through a special bus
link. Because the BULLET contains four serial ports and 256K
bytes of memory, an efficient and economical multi-user system
may be realized.
II DESIGN PHILOSOPHY
The Wave Mate SUPER BULLET has been designed to be the heart of
an extremely low cost, high performance microcomputer system. It
is ideally suited for high performance single user CP/M and
multi-user MP/M small business applications. It is also capable
of providing intelligent terminal, distributed processing, and
high speed local networking capabilities. Special BULLET
hardware features and a greatly enhanced C-BIOS have been
implemented in order to overcome limitations of the CP/M
operating system encountered in most existing hardware
configurations.
Since most small microcomputer systems are I/O bound (rather than
compute bound), the BULLET design has addressed this fact by
incorporating into its architecture a flexible DMA facility,
fully interrupt driven I/O, and a high speed floppy disk
controller. The 8MHZ Z-80H CPU was chosen with a full complement
of Zilog compatible peripheral chips. This insures a cost
effective, simple design; yet unlike most other implementations,
the design results in full use of the microprocessor's
capabilities.
The SUPER BULLET has been designed with the OEM/systems
integrator in mind. Its compact size, low power requirement, and
single supply voltage make it easy to incorporate into both
existing and new equipment.
2-16-84 2

III HARDWARE DESCRIPTION
A. Physical Considerations
The SUPER BULLET is packaged on a single printed circuit board
measuring 7.875 inches (20 cm) by 10.7 inches (27.2 cm).
Mounting holes .156 inches (4 rom) in diameter are provided .250
inches (6.4 rom) from the corners. The maximum height of the
board, considering pin lead protrusion through the board on the
underside as well as component height, is .625 inches (15.8 rom).
Additional height must be provided for the header connectors for
the I/O and power. However, all connectors have been placed on
the component side of the board. Component and connector
identifiers have been silk screened on the board.
B. Electrical Requirements
The SUPER BULLET requires only one regulated 5 volt power supply,
which under normal room temperatures need supply only 2 amps.
Actual current consumption depends upon use of the optional EPROM
and whether the SCSI bus is being used. The plus and minus
voltages, required for the RS-232 operation, are generated on the
board itself.
For power an AMP connector, part # 350211-1, has been mounted on
the board. The mating connector, supplied by the user, must be
an AMP part # 1-480424-0 with AMP contacts #60617-4 or
equivalent. OEMs that require a low profile power connector
should contact Wave Mate regarding an optional connector. If a
switching power supply is used, the board and ALL disk drives
MUST be shielded from noise.
C. CPU, DMA, and Interrupt System
1. Central Processing Unit (CPU):
The Zilog Z80H CPU device is clocked up to the maximum eight
megahertz rate with no memory wait states. Peripheral I/O
devices are clocked at a four megahertz rate. Timing differences
between slow peripherals and EPROM are resolved by a proprietary
circuit •
.
2. Direct Memory Access (DMA) Facility:
There are two Zilog DMA controllers on the SUPER BULLET, DMAO and
DMAI. These devices provide for data transfer from/to any memory
location or I/O device at rates of up to one megabyte per second.
External logic is provided which allows transfers from/to any RAM
memory bank at the same data rate. It should be noted that only
the RAM memory is accessible to the DMA devices, EPROM and ROM
memory are not in the DMA map.
External device multiplexing allows several I/O devices to use a
2-16-84 3

DMA channel and controls transfers between the memory banks.
Device selection and memory control is selected through an
external write only register. I/O port addresses for the DMA
controllers and the external control registers are as follows:
lA HEX
14 HEX
18 HEX
15 HEX
DMA channel 0 status/control
DMA channel 0 external control
DMA channel 1 status/control
DMA channel 1 external control
DMA I/O device selection and memory
the external control register and are
table:
control are programmed into
defined in the following
BITS
2,1,0
DEVICE
000
FDC floppy
disk controller.
001
LOGIC O.
010 DART serial channel B.
011
SCSI bi-directional
bus.
100
External device 1.
101 External device 2.
110
SIO serial channel
A.
III
SIO serial channel
B.
RAM memory control of DMA operations is selected according to the
following fields:
RAM
BITS 5,4
BITS 7,6
memory bank
00
BANK
01 BANK
10 BANK
11
BANK
Select source bank.
Select destination bank.
selection
bit fields are defined
0
1
2
3
as follows:
The remaining bit, bit 3, in this register is unused. Note that
when a transfer is between an I/O port and memory, the memory
control bit fields for both the source and destination must be
programmed the same and must contain the desired memory bank
number for the I/O. A device selection at a known logic state is
provided to facilitate memory to memory moves where it is desired
to move only one byte by using the DMA byte mode and the force
ready command. To use this facility, the DMA must be programmed
for a logic 1 to be ready, and the logic a "device" selected.
Then when the force ready command is issued only one byte will
transfer if byte mode has been programmed. If the DMA senses
external ready when it is enabled, the full byte count plus one
will be immediately transferred when the DMA is enabled.
When both DMA devices request the bus at the same time, . the bus
request priority is hardwired to give DMAO the highest priority.
2-16-84 4

The bus request priority out line of DMAI is present on the
external bus connector as *BAO and additional DMA devices may be
added. If additional DMA devices are added, they will be of
lower priority and will not have access to the special hardware
on the board which allows efficient memory to memory data moves
and I/O.
3. Priority Interrupt Structure:
All peripheral devices are connected to the standard Zilog
interrupt priority daisy chain. The priority interrupt daisy
chain is provided with look ahead logic which terminates on the
external bus connector. Thus any devices added to the external
bus may use the priority interrupt daisy chain. The priorities
are shown in the table below from the highest priority to the
lowest:
1. DMAO
2. DMAI
3. SIO
4. DART with FDC on the A level.
5. PIO with Centronics and SCSI.
6. Clock Timer Circuit 0
7. External Devices
When using the interrupt daisy chain the ZSO must be programmed
in interrupt mode 2 (1M2). In order to accomodate the slower
peripherals, the external timing logic must synchronize to the
peripheral clock during the execution of the ZSO RETI
instruction. This is required to allow the interrupt daisy chain
to stabilize so that the RETI instruction is decoded by the
peripheral under service. This synchronization MUST be
accomplished by the following three ZSO instructions:
OUT (lFH) ,A
EI
RETI
; Enable synchronization.
; Reenable interrupts.
; Execute return from interrupt.
Failure to execute this code sequence for peripherals which
require the RET! instruction will result in a system failure.
Once synchronization is started, it is only active for the
following two instructions. Interrupts MUST be disabled at the
start of this sequence to ensure that it executes uninterrupted.
2-16-S4 5

4. I/O Port Assignments:
The following chart summarizes the I/O port assignments.
2-16-84
PORT
o
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
lA
IB
IB
lC
lD
IE
IF
DEVICE
DART Channel A Data
DART Channel A Status/Control
DART Channel B Data
DART Channel B Status/Control
PIO Port A Data
PIO Port B Data
PIO Port A Control
PIO Port B Control
CTCO Channel 0
CTCO Channel 1
CTCO Channel 2
CTCO Channel 3
SID Channel A Data
SID Channel A Status/Control
SID Channel B Data
SID Channel B Status/Control
FDC Command/Status Port
FDC Track Register
FDC Sector Register
FDC Data Register
External DMAO Control Register (Write only)
External DMAI Control Register (Write only)
External FDC Register (Hardware Control)
Memory Map Select Register (Write only)
DMAI Status/Control
SCSI Bi-directional Data Bus.
DMAO Status/Control
FDC9229 Control (Write only)
Hardware Status Register (Read only)
CTCI Channel 0
CTCI Channel 1
CTCI Channel 2
Return From Interrupt Control (Write only)
6

D. Memory System
1. Random Access Memory (RAM):
There is 256K bytes of random access memory on the SUPER BULLET.
The memory is physically organized as four 64K banks. External
support logic allows the DMA devices to directly access any
location within this 256K memory system. Although the DMA device
can move data from/to any address within the 256K bytes of RAM on
the SUPER BULLET, the Z80 can only address 64K bytes at anyone
time. To provide greater versatility, memory mapping of the CPU
address space is provided through an I/O port. There is a common
memory area which is always in the CPU's context. The common
memory may be mapped into either RAM or the EPROM. The CPU's
common memory may be selected to be either the address space from
0000 HEX to 3FFF HEX, or from COOO HEX to FFFF HEX. This is
equivalent to 16K bytes of address space. The remaining 48K of
CPU address space may be mapped from anyone of five logical
banks of 48K which comprise the remainder of the 256K of RAM on
the system. Note that the state of the CPU memory map does not
affect the DMA operations; that is, the memory banks are constant
for the DMA device as it can access the full 256K of RAM memory.
For example, assume two CPU memory maps each contain a program,
and the currently executing program request~d the operating
system to 'read a disk sector. The operating system could
initiate a DMA read sector operation to transfer the data from
the disk to that user space. The operating system could then
switch CPU address banks and start the second program executing
while the DMA operation was being performed without affecting the
transfer of data to the first program.
Selection of the CPU memory map is accomplished by outputting a
map code to the Segment Register at I/O port 17 HEX. The
function of the map code bits is shown in the following table:
SEGMENT REGISTER CONTROL FUNCTIONS:
Bits Function
4 Select address of common memory area:
a = COOO-FFFF
1 = 0000-3FFF
3 Select EPROM to be common:
a = RAM is common
1 = EPROM is common
2,1,0 Select active bank (non-common memory):
000 = Bank a is selected
001 = Bank 1 is selected
010 = Bank 2 is selected
all = Bank 3 is selected
100 = Bank 4 is selected
2-16-84 7

The
address mapping function of
the Memory Map Register contents
is shown in the following table:
Logical CPU Address
0000-3FFF 4000-7FFF 8000-BFFF
COOO-FFFF
Segment Register
bank/seg
bank/seg
bank/seg
bank/seg
00000
BO ,SO BO ,Sl
BO,S2 BO,S3
00001
Bl,SO
Bl,Sl
Bl,S2
BO ,S3
00010 B2,SO
B2,Sl
B2,S2
BO,S3
00011 B3,SO
B3,Sl B3,S2
BO,S3
00100
Bl,S3 B2,S3 B3,S3
BO ,S3
01000
BO,SO BO ,Sl BO ,S2 EPROM
01001
Bl,SO Bl,Sl Bl,S2
EPROM
01010 B2,SO
B2,Sl B2,S2 EPROM
01011 B3,SO
B3,Sl B3,S2 EPROf.l
01100
Bl,S3 B2,S3 B3,S3 EPROM
10000
BO ,SO
BO ,Sl BO,S2 BO,S3
10001
BO ,SO Bl,Sl Bl,S2
Bl,S3
10010
BO ,SO
B2,Sl B2,S2
B2,S3
10011 BO ,SO B3,Sl B3,S2
B3,S3
10100 BO ,SO Bl,SO B2,SO B3,SO
11000
EPROM
BO ,Sl
BO ,S2
BO,S3
11001 EPROM Bl,Sl
Bl,S2
Bl,S3
11010
EPROM
B2,Sl B2,S2
B2,S3
11011
EPROM
B3,Sl B3,S2
B3,S3
11100
EPROM
Bl,SO B2,SO B3,SO
Do not use any undesignated segment register
values.
Key
to physical
IIbank/seg
ll
mapping:
BO Physical
Bank 0
SO Segment 0, 0000-3FFF
Bl
Physical
Bank 1 Sl Segment 1, 4000-7FFF
B2 Physical Bank 2
S2
Segment 2, 8000-BFFF
B3
Physical
Bank 3
S3
Segment
3, COOO-FFFF
2-16-84
8

2. Read Only Memory (ROM):
Initial program loading (the boot process) may be done from a
flexible diskette by a 32 byte program in ROM. This function is
selected by switch four on SWI. Upon power up or reset, if this
switch is OFF, the ROM is mapped into a starting address of zero
which is the Z80 starting address after power up reset. In
addition, reset enables switch selection of the floppy disk boot
parameters. The boot device and mode are determined by the
settings of the 8 position DIP switch on the SUPER BULLET. The
physical disk unit number is always unit zero regardless of
whether it is a 3, 5 or 8 inch drive. The ROM location is read
only, a write to its address space will be placed into RAM. The
function of the ROM is to read the first sector from track zero
into RAM memory starting at address zero. When this is achieved
with no disk I/O error, the ROM starts executing the code at
location 32 HEX. At any time after a reset, an input or output
to the port address 1A HEX (the DMAO port) will disable the ROM
and it will no longer be accessible until another reset occurs.
3. Erasable Programmable Read Only Memory (EPROM):
A location for an optional EPROM is located at U131. This socket
fs configured as an Intel Univer sal Memory Si te. It accepts
either a 24 pin 2732A, or 28 pin 2764, or 28 pin 27128 EPROM.
Selection of the type is controlled by jumper option. Refer to
the section on switches and jumpers for configuration data. If
an EPROM is installed, it may be selected as the reset program by
setting SWI switch four ON. If this option is selected, the
program starting at location zero in the EPROM will execute upon
reset. At any time after a reset, an input or output to the port
address lA HEX (the DMAO port) will disable the reset mapping of
the EPROM. The EPROM may also be mapped into the CPU memory at
any time by appropriate selection of the value placed in the
Memory Segment Register. See the memory mapping information
under RAM above. The address decoding provides for a 16K EPROM.
If an 8K or 4K EPROM is installed the EPROM will appear in
multiple images in the CPU memory map. When the CPU is accessing
the EPROM the CPU clock is slowed to 4 megahertz. The
recommended access time for the EPROM is 250 nano seconds. The
SUPER BULLET is shipped without EPROM unless special OEM
arrangements have been made.
E. I/O System:
The I/O system is fully decoded on the SUPER BULLET thus all
unassigned port addresses from 20 HEX to FF HEX may be used by
external hardware. The I/O space from 20 HEX to 2F HEX is set
aside for OEM manufactured devices and the space from 30 HEX to
3F HEX is reserved for Wave Mate developed peripherals. The
space from 40 HEX to FF HEX is undesignated.
2-16 -84 9

1. Hardware Status Register:
A read only hardware status register at port lB HEX is provided
to check the state of the following functions:
BIT STATUS FUNCTION.
o Centronics Busy Bit.
1 DIP switch 2.
2 DIP switch 3.
3 *Floppy disk two sided.
4 Floppy disk head load status.
5 *Floppy disk exchange (8 inch only).
6 FDC interrupt request line.
7 FDC data request line.
2. Floppy Disk Controller/Formatter (FDC):
This device is a Synertek SY1793-002. It is upward compatible
with the western Digital FD1793 controller. The following I/O
port addresses are assigned to this device:
10 HEX
11 HEX
12 HEX
13 HEX
Command/Status register.
Track register.
Sector register.
Data register.
Since this is not a Zilog device and not capable of generating or
responding to the Zilog priority daisy chain interrupt, it is
connected to the DART *RIA (Ring Indicator A) input to provide an
interrupt vector. External logic provides for control of four
8-inch floppy disk drives, four 5-inch floppy disk drives, and
two 3-1/2-inch floppy disk drives. The external logic also
provides for software control of the spindle motors (5 inch and 3
inch drives only) , side select, and enabling of write
precompensation. These functions are controlled by write only
registers.
The following table gives the external control port addresses and
bit definitions: .
FDC DISK CONTROL REGISTER, PORT 16 HEX:
BIT 0-3
BIT 4
BIT 5
BIT 6
BIT 7
Bits 0, 1, 2, 3 form a unit select number,
as follows:
0, 1, 2, & 3 are the 5 inch drives, 4, 5, 6 & 7
are the 8 inch drives, and 8 & 9 are the 3 inch.
Select side 2.
Disable 3 & 5 inch spindle motors.
Select 1 or 2 MHZ controller operation.
Select single or double density operation.
FDC CONTROL PORT lB HEX:
2-16-84 10

BIT
0 Set
FDC9229
PO mode.
BIT
1
Set
FDC9229
PI
mode.
BIT
2 Set
FDC9229 P2 mode.
BIT
3 Set SYl793 test pin (fast seek).
BIT
4 Select software control of port 16HEX.
BIT
5
Unused.
BIT
6 Unused.
BIT
7
Set door lock.
The FDC device is capable of formatting and reading a wide
variety of soft sectored diskettes. With 8 inch drives, it is
compatible with the IBM 3740 format and FM recording and the IBM
System-34 format and MFM recording. With 5 inch drives, it is
compatible with both single density and double density soft
sector formats. Data separation for all modes is provided by a
digital data separator circuit.
,3. Dual Asynchronous Receiver/Transmitter (DART):
This device provides two independent asynchronous serial data
channels. Each channel has an independent baud rate which is
derived from two channels of the counter timer circuit 0
(described later). The baud rates are determined by the CTCO and
DART programming and can range from 110 baud to 76.8 kilobaud.
In addition, the transmit/receive word parameters are fully
programmable within the DART. Channel A and B of the DART
provide a full implementation of the RS-232-C interface type E,
with the exception that there is no circuit CE (ring indicator).
Channel A of· the DART is normally used for the system console.
The channel A ring indicator input is used by the floppy disk
controller to request an interrupt vector on the Zilogdaisy
chain interrupt system. The DART is the fourth device on the
interrupt priority daisy chain, following the SIO device.
The DART registers
are at the following
port addresses:
0
HEX Channel
A
data.
1 HEX Channel
A
status/control.
2
HEX Channel
B
data.
3
HEX Channel B
status/control.
4.
Serial Input/Output
(SID)
This device provides two independent synchronous or asynchronous
serial data channels. Each channel has an independent baud rate
which is derived from the counter timer circuit 1 (described
later). In addition, the transmit and receive baud rates for
channel A may be set independently. This allows the user to
transmit and receive at different bauds. These baud rates are
determined by the CTCI and SIO programming. For asynchronous
operation these bauds can range from 110 baud to 76.8 kilobaud.
For synchronous operation, bauds as high as 880K may be
programmed. In addition, the transmit/receive word parameters
are fully programmable within the SID. Channel A and B of the.
2-16-84 11

SIO provide a full implementation of the RS-232-C interface type
E with the exception that there is no circuit CE (ring
indicator) II! The SIO is the third device on the' interrupt
priority daisy chain, following the DMAI device.
The SIO registers are at the following port addresses:
C HEX
D HEX
E HEX.
F HEX
Channel A data.
Channel A status/control.
Channel B data.
Channel B status/control.
5. Counter Timer Circuit (CTC):
Counter Timer Circuit a (CTCO):
This device provides four independently programmable
counter/timer channels. Channel a is used to provide the baud
clock for the DART channel A. Channel 1 is used to provide the
baud clock for the DART channel B. Channels 2 and 3 are u'sed
together to provide a real time clock capability and clock
interrupts. This is achieved by using channel 2 as a timer and
channel 3 as a counter. Channels 0, 1, and 2 have their inputs
connected to a crystal controlled clock which provides a 1.2288
MHZ frequency. The CTCO device is the·sixth device on the
interrupt priority daisy chain.
The CTCO registers are at the following I/O port addresses:
Channel a
Channel 1
Channel 2
Channel 3
8
HEX
9 HEX
A HEX
B HEX
Counter Timer Circuit 1 (CTCl):
This device provides additional programmable counter/timer
channels. Channel a is used to provide the transmit baud clock
for the SIO channel A. Channel 1 is used to provide the receive
baud clock for the SIO channelA. Channel 2 is used to provide
the baud clock for the SIO channel B. Channels 0, 1, and 2 have
their inputs connected to a crystal controlled clock which
provides a 1.2288 MHZ frequency. The CTCI device is not on the
priority interrupt daisy chain.
The CTCI registers are at the following I/O port addresses:
Channel a
Channel 1
Channel 2
lC HEX
lD HEX
IE HEX
Note that channel 3 may not be used. Its port (IF HEX) is used
to enable interrupts on the priority daisy chain.
2-16-84
12

6. Parallel Input/Output Controller (PIa):
This device provides two 8 bit parallel I/O ports. It is used to
implement the Centronics interface .and the SCSI bus control
interface. Port Bprovides the Centronics data and handshake
signals. Port A is used in bit mode to provide status of the
SCSI bus interface. The control signal assignments presented
here are further described under ·the applicable I/O device.
PIa
Port A,
SCSI bus control (bi t mode) :
BIT
o:
ATN
output
BIT
1: RST
output
BIT
2:
SEL
output
BIT
3 :
BUSY input
BIT 4: MSG input
BIT 5 :
C/D
input
BIT 6: REQ input
BIT 7:
I/O
input
Note that program control allows these devices to operate in
either interrupt driven or polled mode. The PIa device is the
fifth device on the interrupt priority daisy chain.
The PIa registers are at the following I/O port addresses:
4 HEX
5 HEX
6 HEX
7 HEX
Port A data.
Port B data.
Port A control.
Port B control.
7. Centronics Printer Port:
The Centronics printer interface has been implemented with the
use of a Zilog PIa device. The PIa port B is programmed in
output mode and provides data output and handshaking to the
interface. The Centronics status is sensed in the hardware
status register. When bit zero is 1 the interface is busy, when
it is zero the interface is not busy. If the interface is not
busy, data may be written to the PIa data port B. An interrupt
may be programmed when the interface accepts the data and
additional data written to port B during the interrupt service
routine.
8. SCSI Bus Interface:
A SCSI bus interface is provided which is capable of controlling
a variety of SCSI compatible devices. It is most commonly used
to communicate with.a Winchester disk controller.
The SCSI bus interface is implemented by a bi-directional data
port at 19 HEX. Status and control of the SCSI is implemented
with the PIa Port A programmed in bit mode, and through hardware
handshaking. A read from port 19 HEX accesses the data on the
2-16-84
13

SCSI data bus. A write to port 19 HEX latches the data which
will be read by the external device when it reads the SCSI data
bus. Note that a read or write to this port causes the hardware
to assert *ACK if enabled by *REQ.
Users wishing to program the SCSI should be familiar with the
operation of the SCSI as described in ANSI X3T9.2/82-2.
2-16-84 14

IV I/O CONNECTORS
1. Jl -50 pin General Purpose External Bus Connector
A 50 pin male header is used to permit the Z-80A CPU bus and the
DMA bus to be used externally from the SUPER BULLET. The pin-out
of this header is shown below.
PIN Signal I/O
1 DO IO
2 Dl IO
3 D2 IO
4 D3 IO
5 D4 IO
6 D5 IO
7 D6 IO
8 D7 IO
9 CLOCK 0
10 GND 0
11 AO IO
12 AI IO
13 A2 IO
14 A3 IO
15 'A4 IO
16 AS IO
17 A6 IO
18 A7 IO
19 A8 IO
20 A9 IO
21 AI0 IO
22 All IO
23 A12 IO
24 A13 IO
25 A14 IO
26 A15 IO
27 GND 0
28 *BAO 0
29 *EXRDYI I
30 *EXRDY2 I
31 N/C
32 *RESET 0
33 *INT I
34 N/C
35 *BSREQ I
36 *BSACK 0
37 *IORQ 0
38 *MREQ 0
39 *RD 0
40 *WR 0
41 *Ml 0
42 *RFSH 0
43 *NMI I
44
*WAIT I
2-16-84
Descripti on
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
4
MHZ Peripheral Clock
Ground
Address Bit 0
Address Bit 1
Address Bit 2
Address Bit 3
Address Bit 4
Address Bit 5
Address Bit 6
Address Bit 7
Address Bit 8
Address Bit 9
Address Bit 10
Address Bit 11
Address Bit 12
Address Bit 13
Address Bit 14
Address Bit 15
Ground
Bus ,Acknowledge Out (DMA)
External Device 1 Ready
External Device 2 Ready
Spare
Reset Out
Interrupt (CPU)
Spare
Bus Request (DMA)
Bus Acknowledge (CPU)
I/O Request (CPU)
Memory Request (CPU)
Read (CPU)
Wri te (CPU)
Machine Cycle One
Memory Refresh (CPU)
Non Maskable Interrupt (CPU)
Wai t (CPU)
15

45
*HALT
0 Halt
(CPU)
46
*DMEM
I
Disable on board memory
47 *IEOUT 0 External Interrupt Priority
48
N/C Spare
49 N/C
Spare
50
VCC
0 + 5
VOLTS
The female mating connector to Jl is 3M part number 3425-6000 or
equivalent. The output lines are capable of driving a maximum of
4 CMOS loads or 1 TTL load. The maximum cable length to be
attached to Jl cannot exceed 12 inches.
2. J2 -50 pin SCSI Interface connector
A 50 pin male header is used to connect to a SCSI bus compatible
peripheral. The pin-out of the header is shown below.
PIN Signal
2 *SDO
4 *SDI
6 *SD2
8 *SD3
10 *SD4
12 *SD5
14 *SD6
16 *SD7
32 *ATN
34 *SPARE
36 *BUSY
38 *ACK
40 *RST
42 *MSG
44 *SEL
46 *C/D
48 *REQ
50 *1/0·
I/O Description
10 Data Bit 0
10 Data Bit 1
10 Data Bit 2
10 Data Bit 3
10 Data Bit 4
10 Data Bit 5
10 Data Bit 6
10 Data Bit 7
o Attention
Spare
I Bus busy
o Acknowledge
o Reset
I Message
o Select
I Command/Data
I Request
I Input/Output
Odd numbered pins 1 through 49 are all connected to ground.
The female mating connector to J2 is 3M part number 3425-6000 or
equivalent. The maximum cable length to be attached to J2 should
not exceed 6 meters.
3. J3 - 10 pin serial port connector
A ten pin male header is used to attach a RS-232-C serial
terminal to the SUPER BULLET using the DART channel A. A ten pin
male header is used to attach a second RS-232-C serial terminal
to the SUPER BULLET.
PIN Signal I/O Description
1 *TXDB 0 Transmit Data
2-16-84
16

2 *RXDB
3
*DTRB
4
*RTSB
5
*CTSB
6
*DCDB
7 RLSDB
8
GND
9 *CRESET
10 GND
The female
equivalent.
def ini ti ons.
I Recei veDa ta
0 Data Terminal Ready
0
Request To Send
I Clear To Send
I
Data Carrier Detect
0
Receive Line Signal
Detect
0
Ground
I Computer
Reset
0 Ground
mating connector to J4 is 3M part number 3473-6000 or
The above signals correspond to the Zilog DART
See system set-up for recommended RS-232-C usage.
4. J4 -10 pin serial port connector
A ten pin male header is used to attach· a RS-232-C serial
terminal to the SUPER BULLET using the DART channel A. When
using the WAVE ~mTE provided C-BIOS and CP/M, this port is used
as the system console. The pin-out of the header is shown ,below.
PIN Signal
I/O
Description
1
*TXDA 0
Transmit Data
2 *RXDA
I
Receive Data
3
*DTRA
0
Data Terminal Ready
4
*RTSA
0
Request to Send
5 *CTSA
I Clear To Send
6
*DCDA
I
Data Carrier Detect
7
RLSDA
0
Receive Line Signal
Detect
8 GND
0
Ground
9
*CRESET I Computer Reset
10
GND
0
Ground
The female mating connector to J3 is 3M part number 3473-6000 or
equivalent. The above signals correspond to the Zilog DART
definitions. See system set-up for recommended RS-232-C usage.
5. J5 -34 pin Centronics Printer. port connector
A 34 pin male header is used to attach a Centronics type printer
to the SUPER BULLET. The pin-out of this header is shown below.
PIN
Signal
I/O
Description
1
*CSTRB
0
Strobe
3
CDTAI
0
Data Bit
1
5
CDTA2
0
Data Bit
2
7
CDTA3
0
Data Bit
3
9 CDTA4
0
Data Bit
4
11
CDTA5
0
Data Bit
5
13
CDTA6
0
Data Bit
6
15 CDTA7
0
Data Bit
7
17
CDTA8
0
Data Bit
8
2-16-84
17

19
21
*CACK
CBUSY
I
.1
Acknowledge
Busy
Even
pins 2 through 24 and 27, 30, and 31 are all connected to
ground.
The female mating connector to J5 is 3M part number 3414-6000 or
equivalent. The maximum cable length to be attached to J5 should
not exceed 8 feet.
6. J6 - 50 pin 8" floppy disk drive connector
A 50 pin male header is used to attach from one to four 8"
Shugart 800 compatible disk drives to the SUPER BULLET. The
pin-out of this header is shown below.
PIN
Signal
I/O
Description
2
*XTG43
0
Track greater than 43
10 *FD2S I
Disk is two sided
12
*XDCG I
Disk has been changed
(door opened & closed)
14 *XSIDE 0
Side Select
16
*DLOCK
0 Door Lock
18 *XHLD
0 Head
Load
20 *INDEX
I
Index Pulse
22
*READY
I Ready
26 *SELI 0
Select Drive
#1
28 *SEL2 0
Select Drive #2
30 *SEL3 0
Select Drive #3
32 *SEL4 0
Select Drive
#4
34
*XDIR
0
Direction
36 *XSTEP
0
Step
38
*XWDAT
0
Write Data
40 *XWGAT
0
Write
Gate
42
*TROO
I
Track Zero Sensor
44
*WPROT
I
Write Protect Sensor
46
*RDATA
I
Read Data
All odd numbered pins are connected to ground.
The female mating connector to J6 is 3M part number 3425-6000 or
equivalent. The maximum cable length to be attached to J6 should
not exceed 8 feet.
7. J7 - 34 pin 5-1/4 inch mini floppy disk drive connector
A 34 pin male header is used to attach from one to four 5 1/4
inch Shugart 400 compatible disk drives to the SUPER BULLET. The
pin-out of this header is shown below.
PIN
2
4
2-16-84
Signal
*DLOC
*MHLD
I/O Description
o Door Lock
o Head Load (jumper option)
18

6 *MSEL4
0 Select Drive #4
8
*INDEX
I Index Pulse
10
*MSELI
0 Select Drive
#1
12 *MSEL2
0 Select Drive #2
14
*MSEL3
0
Select Drive #3
16
*MMTR
0 Motor
On
18
*MDIR
0
Direction
20
*MSTEP
0 Step
22
*MWDAT
0
Write Data
24 *
MWG AT
0 Wri
te Gate
26
*TROO
I
Track Zero Sensor
28
*WPROT
I
Write Protect Sensor
30
*RDATA
I Read Data
32
*MSIDE
0 Side Select
34
*RDY
I Ready (
jumper
option)
All odd numbered pins are connected to ground.
The female mating connector to J7 is 3M part number 3414-6000 or
equivalent. The maximum length of cable to be attached to J7
should not exceed 8 feet.
8. J8 -10 pin serial port connector
A ten pin male header is used to attach a RS-232-C serial device
to the SUPER BULLET using the SIO channel A.
PIN
Signal
I/O . Description
1 *TXDA
0
Transmit Data
2
*RXDA
I
Receive Data
3
*DTRA
0
Data Terminal Ready
4
*RTSA
0
Request To Send
5 *CTSA
I Clear To Send
6
*DCDA
I
Data Carrier Detect
7
RLSDA
0
Receive Line Signal
Detect
8 GND
0
Ground
9 N/C
10 N/C
The
female mating connector to J8 is 3M part number 3473-6000 or
equivalent. The above signals correspond to the Zilog DART
definitions. See system set-up for recommended RS-232-C usage.
9. J9 -10 pin serial port connector
A ten pin male header is used to attach a RS-232-C serial device
to the SUPER BULLET using the SIO channel B.
PIN
Signal
1 *TXDB
2 *RXDB
3 *DTRB
2-16-84
I/O Description
o Transmit Data
I Receive Data
o Data Terminal Ready
19