Winbond W83627DHG User manual

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W83627DHG
WINBOND LPC I/O
Note: This document is for UBC, UBE and UBF version
except specified descriptions
Date : April 10, 2007 Version : 1.4
查询W83627DHG供应商 捷多邦，专业PCB打样工厂，24小时加急出货

W83627DHG
Publication Release Date: Aug, 22, 2007
-I- Version 1.4
Data Sheet Revision History
PAGES DATES VERSION WEB
VERSION MAIN CONTENTS
1 N.A. 12/15/2005 0.1 N.A. 1. First published version.
2 N.A. 02/22/2006 0.2 N.A. 1. Add descriptions of the registers, functions,, AC/DC
timing, and top marking
3 N.A. 03/15/2006 0.3 N.A.
1. Revise Table 8.1 and the timing chart of section 10.3.1
2. Add registers for AMDSI at LDB, CRF5h,CRF6h and
F7h(Bank1)
3. Swap LDB, CRF2h bit 0 and bit 1.
4. Modify the default values for LDA, CRFEh
5. Modify the descriptions of LD9, CR30h bit 0 and
CRF7h bit 4.
6. Remove LDA, CRE9h bit4 ~ 3
7. Swap LDC, CRE0h bit3~0 and CRE5h bit7~4
4 N.A. 05/05/2006 0.4 N.A.
1. Add FDC, UART, Parallel Port and KBC interface
descriptions
2. Remove all the descriptions about AMDSI
3. Modify the diagrams and descriptions for Current Mode
4. Add two control bits for the selections of SYSFANOUT
and CPUFANOUT0 output type at CR[24h]
5. Remove the description of the internal pulled-up
resistor of Parallel Port
6. Modify the definitions of edge/level and enable/disable
debounce circuit of GP30, GP31 and GP35
7. Modify the descriptions of LD7, CRF7h and LD9,
CRE6h ~ CRE9h
8. Correct typos and grammatical mistakes
5 N.A 05/15/2006 0.41 N.A 1. Remove the remaining descriptions about AMDSI in
datasheet ver.0.4
6 N.A. 05/19/2006 0.42 N.A
1. Add a note for Index# of FDC Interface and pin
83(GP42) of Serial Port & Infrared Port Interface in Pin
Description
2. Reserve the bit 7 of LD0, CRF0h
3. Modify the descriptions of TRAK0#, WP#, RDATA#
and DSKCHG# of FDC Interface
4. Modify the descriptions for strapping pins: HEFRAS,
PENROM, PENKBC and EN_GTL
5. Modify the DC spec.
7 N.A. 06/23/2006 0.5 N.A.
1. Remove the note and renew the descriptions for
Index# of FDC Interface.
2. Correct the descriptions of HM Device Bank 0, CR[12h]
bit0.
3. Add two control bits for AUXFANOUT and
CPUFAOUT1 output type selection.
4. Add a new bit at LDC, CR[E8h] bit 1 for more PECI

W83627DHG
Publication Release Date: Aug, 22, 2007
-II- Version 1.4
PAGES DATES VERSION WEB
VERSION MAIN CONTENTS
clock selection.
5. Modify the default values of HM Device Bank 0,
CR[43h] bit 5,0 and CR[46h] bit 2~1.
8 N.A. 09/29/2006 0.6 N.A.
1. Add new chapters for Serial Peripheral Interface,
Configuration Register Access Protocol, Power
Management, Serialized IRQ, Watchdog Timer VID
Inputs and Outputs, and PCI Reset Buffers.
2. Update the feature lists of the W83627DHG in Chapter
2 Features.
3. Add descriptions of PECI and SST and a table of
SMBus in Chapter 5 Pin Description.
4. Add new sections of Caseopen and Beep Alarm
Function in Chapter 7 Hardware Monitor.
5. Add Clock Input Timing, PECI & SST Timing, and SPI
Timing in Chapter 21 Specifications.
6. Remove sections 9.4 and 9.5 (EXTFDD and
EXT2FDD).
7. Modify the descriptions of Hardware Monitor Device,
Bank 0, Index 59h, bits(6..4).
8. Add a beep control bit for VIN4 at Hardware Monitor
Device, Bank 0, Index 57h, bit6.
9. Remove status bit of PME# status of MIDI IRQ event at
Logical Device A, CRF4, bit 1.
10. Remove control bit of enable/disable PME# of MIDI at
Logical Device A, CRF7, bit 1.
11. Modify the descriptions of Tape Drive Register in
Chapter 10 Floppy Disk Controller.
12. Correct the description of Digital Input Register, bit
(6-4) in Chapter 10 Floppy Disk Controller.
13. Remove the description of “MR pin” in Digital Output
Register in Chapter 10 Floppy Disk Controller.
14. Adapt “Serial Flash Interface” to “Serial Peripheral
Interface”.
15. Modify “Absolute Maximum Ratings” in Chapter 21
Specifications.
16. Remove “VDD is 5V± 10% tolerance” from the
description of DC Characteristics in Chapter 21
Specifications.
17. Update “S5cold state” to “S5 state.
18. Remove the section of “AT Interface” in Chapter
10 Floppy Disk Controller.
9 N.A. 10/05/2006 1.0 N.A. 1. Update AC Timing parameters and waveforms.
10 N.A. 12/12/2006 1.1 N.A.
1. Update Table 9.1 and Table 9.2 in Chapter 9 Serial
Peripheral Interface
2. Update CR2Ah in Chapter 20 Configuration Register
3. Modify CR24h bit 0 to reserved

W83627DHG
Publication Release Date: Aug, 22, 2007
-III- Version 1.4
PAGES DATES VERSION WEB
VERSION MAIN CONTENTS
4. Use “Tbase” instead of “TControl”
5. Add the pins, registers description and AC timing for
new ACPI function – VSBGATE#, ATXPGD,
FTPRST, PWROK2 and SUSC#
11 N.A. 01/25/2007 1.2 N.A.
1. Modify the description for VSBGATE#, ATXPGD,
FTPRST.
2. Revise the definition for Logical Device A, CR[E5h]
bit 0.
3. Add new section of PWROK Generation in Chapter
14 Power Management Event.
4. Add new timing of VSBGATE# in Chapter 21
Specifications.
5. Modify the description of CR[2Ah], bits [7:4].
6. Modify the “t1” timing of RSMRST#.
7. Modify the descriptions of 7.7.2 OVT# Interrupt
Mode.
8. Modify the “t3” and “t4” timing in Table 14.4 and
section 21.3.3
12 N.A. 03/28/2007 1.3 N.A.
1. Add a new DC spec. of RSMRST# PWROK for UBF
version (In section 14.3 and 14.4)
2. Add LPC Timing in section 21.4
3. Remove redundant Power on/off and LRESET#
Timing
13 N.A. 04/10/2007 1.4 N.A. 1. Modify LPC Timing in section 21.4
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83627DHG
Publication Release Date: Aug, 22, 2007
-IV- Version 1.4
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................... 1
2. FEATURES....................................................................................................................................... 2
3. BLOCK DIAGRAM ............................................................................................................................ 5
4. PIN LAYOUT..................................................................................................................................... 6
5. PIN DESCRIPTION .......................................................................................................................... 8
5.1 LPC Interface .......................................................................................................................... 9
5.2 FDC Interface.......................................................................................................................... 9
5.3 Multi-Mode Parallel Port........................................................................................................10
5.4 Serial Port & Infrared Port Interface...................................................................................... 12
5.5 KBC Interface........................................................................................................................ 14
5.6 Serial Peripheral Interface.....................................................................................................14
5.7 Hardware Monitor Interface................................................................................................... 15
5.8 PECI Interface....................................................................................................................... 17
5.9 SST Interface ........................................................................................................................ 17
5.10 Advanced Configuration and Power Interface ...................................................................... 17
5.11 General Purpose I/O Port...................................................................................................... 18
5.11.1 SMBus Interface ....................................................................................................................18
5.11.2 GPIO Power Source...............................................................................................................18
5.11.3 GPIO-2 Interface....................................................................................................................19
5.11.4 GPIO-3 Interface....................................................................................................................20
5.11.5 GPIO-4 Interface....................................................................................................................20
5.11.6 GPIO-5 Interface....................................................................................................................21
5.11.7 GPIO-6 Interface....................................................................................................................21
5.11.8 GPIO-4 with WDTO# / SUSLED Multi-function ......................................................................22
5.12 Particular ACPI Function pins – both for UBE and UBF Version Only ................................. 22
5.13 POWER PINS ....................................................................................................................... 23
6. CONFIGURATION REGISTER ACCESS PROTOCOL ................................................................. 24
6.1 Configuration Sequence ........................................................................................................... 25
6.1.1 Enter the Extended Function Mode........................................................................................25
6.1.2 Configure the Configuration Registers ...................................................................................25
6.1.3 Exit the Extended Function Mode ..........................................................................................26
6.1.4 Software Programming Example ...........................................................................................26
7. HARDWARE MONITOR ................................................................................................................. 28
7.1 General Description .............................................................................................................. 28
7.2 Access Interfaces.................................................................................................................. 28
7.2.1 LPC Interface .........................................................................................................................29
7.2.2 I2C interface ...........................................................................................................................30
7.3 Analog Inputs ........................................................................................................................ 31
7.3.1 Voltages Over 2.048 V or Less Than 0 V...............................................................................31
7.3.2 Voltage Detection...................................................................................................................32

W83627DHG
Publication Release Date: Aug, 22, 2007
-V- Version 1.4
7.3.3 Temperature Sensing.............................................................................................................32
7.4 SST Command Summary ..................................................................................................... 34
7.4.1 Command Summary ..............................................................................................................34
7.4.2 Combination Sensor Data Format..........................................................................................35
7.5 PECI ...................................................................................................................................... 36
7.6 Fan Speed Measurement and Control.................................................................................. 39
7.6.1 Fan Speed Measurement.......................................................................................................39
7.6.2 Fan Speed Control.................................................................................................................40
7.6.3 SMART FANTM Control ..........................................................................................................41
7.7 Interrupt Detection................................................................................................................. 50
7.7.1 SMI# Interrupt Mode ..............................................................................................................50
7.7.2 OVT# Interrupt Mode .............................................................................................................53
7.7.3 Caseopen Detection...............................................................................................................54
7.7.4 BEEP Alarm Function ............................................................................................................55
8. HARDWARE MONITOR REGISTER SET ..................................................................................... 56
8.1 Address Port (Port x5h).........................................................................................................56
8.2 Data Port (Port x6h) .............................................................................................................. 56
8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0).......... 57
8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0)....................................... 57
8.5 CPUFANOUT0 PWM Output Frequency Configuration Register - Index 02h (Bank 0) ....... 58
8.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) .................................... 59
8.7 FAN Configuration Register I - Index 04h (Bank 0) .............................................................. 59
8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank
0)……................................................................................................................................…………60
8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h
(Bank 0)........................................................................................................................................... 61
8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0).............. 61
8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) ..................................................... 62
8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0)................................................... 62
8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) ............................................... 63
8.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) ............................................. 63
8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0)...................................................... 64
8.16 CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0) ................................................... 64
8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0)................................................ 65
8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0)..................................................... 65
8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0) ......... 66
8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0)....................................... 66
8.21 FAN Configuration Register II - Index 12h (Bank 0) ............................................................. 67
8.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h
(Bank 0)........................................................................................................................................... 68
8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0).............. 69
8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) ..................................................... 69
8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0)................................................ 70

W83627DHG
Publication Release Date: Aug, 22, 2007
-VI- Version 1.4
8.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) ...................................................... 70
8.27 OVT# Configuration Register - Index 18h (Bank 0) .............................................................. 71
8.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) .................................................................. 71
8.29 Value RAM ⎯Index 20h ~ 3Fh (Bank 0).............................................................................. 71
8.30 Configuration Register - Index 40h (Bank 0)......................................................................... 73
8.31 Interrupt Status Register 1 - Index 41h (Bank 0) .................................................................. 73
8.32 Interrupt Status Register 2 - Index 42h (Bank 0) .................................................................. 74
8.33 SMI# Mask Register 1 - Index 43h (Bank 0) ......................................................................... 75
8.34 SMI# Mask Register 2 - Index 44h (Bank 0) ......................................................................... 75
8.35 Reserved Register - Index 45h (Bank 0)............................................................................... 75
8.36 SMI# Mask Register 3 - Index 46h (Bank 0) ......................................................................... 75
8.37 Fan Divisor Register I - Index 47h (Bank 0).......................................................................... 76
8.38 Serial Bus Address Register - Index 48h (Bank 0) ............................................................... 77
8.39 CPUFANOUT0/AUXFANOUT monitor Temperature source select register - Index 49h (Bank
0)…….............................................................................................................................................. 77
8.40 CPUFANOUT1 Monitor Temperature Source Select Register - Index 4Ah (Bank 0)........... 78
8.41 Fan Divisor Register II - Index 4Bh (Bank 0) ........................................................................ 79
8.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0) .............................................................. 79
8.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0) ............................................................ 80
8.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) .......................................... 81
8.45 Winbond Vendor ID Register - Index 4Fh (Bank 0) .............................................................. 81
8.46 Reserved Register - Index 50h ~ 55h (Bank 0) .................................................................... 82
8.47 BEEP Control Register 1 - Index 56h (Bank 0)..................................................................... 82
8.48 BEEP Control Register 2 - Index 57h (Bank 0)..................................................................... 83
8.49 Chip ID - Index 58h (Bank 0)................................................................................................. 84
8.50 Diode Selection Register - Index 59h (Bank 0)..................................................................... 84
8.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0) ................................................................... 85
8.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) .......................................................... 85
8.53 Critical Temperature and Current Mode Enable Register - Index 5Eh (Bank 0) .................. 86
8.54 Reserved Register - Index 5Fh (Bank 0) .............................................................................. 87
8.55 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) ....... 87
8.56 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) .................................... 87
8.57 FAN Configuration Register III - Index 62h (Bank 0) ............................................................ 88
8.58 Target Temperature Register/CPUFANIN1 Target Speed Register - Index 63h (Bank 0)... 89
8.59 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0)................................................... 89
8.60 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0) ............................................. 90
8.61 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0) .................................................... 90
8.62 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0)............................... 91
8.63 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0)....................................... 91
8.64 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0)............................... 92
8.65 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0)....................................... 92
8.66 SYSFANOUT Critical Temperature register - Index 6Bh (Bank 0) ....................................... 93

W83627DHG
Publication Release Date: Aug, 22, 2007
-VII- Version 1.4
8.67 CPUFANOUT0 Critical Temperature Register - Index 6Ch (Bank 0) ................................... 93
8.68 AUXFANOUT Critical Temperature Register - Index 6Dh (Bank 0) ..................................... 93
8.69 CPUFANOUT1 Critical Temperature Register - Index 6Eh (Bank 0) ................................... 94
8.70 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)...... 94
8.71 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ...... 95
8.72 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1)........................ 95
8.73 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ......... 96
8.74 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) .......... 96
8.75 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1)97
8.76 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
1)…….................................……………………………………………………………………………….97
8.77 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)...... 98
8.78 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)....... 98
8.79 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) ........................ 98
8.80 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2).......... 99
8.81 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) .......... 99
8.82 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank
2)……............................................................................................................................................ 100
8.83 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank
2)……............................................................................................................................................ 100
8.84 Interrupt Status Register 3 - Index 50h (Bank 4) ................................................................ 101
8.85 SMI# Mask Register 4 - Index 51h (Bank 4) ....................................................................... 102
8.86 Reserved Register - Index 52h (Bank 4)............................................................................. 102
8.87 BEEP Control Register 3 - Index 53h (Bank 4)................................................................... 102
8.88 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) .................................. 103
8.89 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4).................................. 103
8.90 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4).................................. 104
8.91 Reserved Register - Index 57h-58h (Bank 4) ..................................................................... 104
8.92 Real Time Hardware Status Register I - Index 59h (Bank 4).............................................. 104
8.93 Real Time Hardware Status Register II - Index 5Ah (Bank 4) ............................................ 105
8.94 Real Time Hardware Status Register III - Index 5Bh (Bank 4) ........................................... 106
8.95 Reserved Register - Index 5Ch ~ 5Fh (Bank 4).................................................................. 107
8.96 Value RAM 2 ⎯Index 50h-59h (Bank 5)............................................................................ 107
8.97 Reserved Register - Index 50h ~ 57h (Bank 6) .................................................................. 107
9. SERIAL PERIPHERAL INTERFACE............................................................................................ 108
9.1 Using the SPI Interface via the LPC ................................................................................... 108
10. FLOPPY DISK CONTROLLER..................................................................................................... 111
10.1 FDC Functional Description ................................................................................................ 111
10.1.1 FIFO (Data)..........................................................................................................................111
10.1.2 Data Separator.....................................................................................................................112
10.1.3 Write Precompensation........................................................................................................112
10.1.4 Perpendicular Recording Mode............................................................................................112
10.1.5 FDC Core.............................................................................................................................112

W83627DHG
Publication Release Date: Aug, 22, 2007
-VIII- Version 1.4
10.1.6 FDC Commands ..................................................................................................................113
10.2 Register Descriptions .......................................................................................................... 124
10.2.1 Status Register A (SA Register) (Read base address + 0) ..................................................124
10.2.2 Status Register B (SB Register) (Read base address + 1) ..................................................126
10.2.3 Digital Output Register (DO Register) (Write base address + 2)..........................................128
10.2.4 Tape Drive Register (TD Register) (Read base address + 3) ..............................................128
10.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................129
10.2.6 Data Rate Register (DR Register) (Write base address + 4) ...............................................129
10.2.7 FIFO Register (R/W base address + 5)................................................................................131
10.2.8 Digital Input Register (DI Register) (Read base address + 7) ..............................................133
10.2.9 Configuration Control Register (CC Register) (Write base address + 7)..............................134
11. UART PORT ................................................................................................................................. 136
11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................... 136
11.2 Register Description............................................................................................................136
11.2.1 UART Control Register (UCR) (Read/Write) ........................................................................136
11.2.2 UART Status Register (USR) (Read/Write)..........................................................................139
11.2.3 Handshake Control Register (HCR) (Read/Write)................................................................140
11.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................140
11.2.5 UART FIFO Control Register (UFR) (Write only) .................................................................141
11.2.6 Interrupt Status Register (ISR) (Read only) .........................................................................142
11.2.7 Interrupt Control Register (ICR) (Read/Write) ......................................................................143
11.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................143
11.2.9 User-defined Register (UDR) (Read/Write)..........................................................................144
12. PARALLEL PORT......................................................................................................................... 145
12.1 Printer Interface Logic .........................................................................................................145
12.2 Enhanced Parallel Port (EPP)............................................................................................. 146
12.2.1 Data Port (Data Swapper)....................................................................................................147
12.2.2 Printer Status Buffer.............................................................................................................147
12.2.3 Printer Control Latch and Printer Control Swapper ..............................................................147
12.2.4 EPP Address Port ................................................................................................................148
12.2.5 EPP Data Port 0-3 ...............................................................................................................148
12.2.6 EPP Pin Descriptions ...........................................................................................................149
12.2.7 EPP Operation .....................................................................................................................149
12.3 Extended Capabilities Parallel (ECP) Port.......................................................................... 150
12.3.1 ECP Register and Bit Map ...................................................................................................151
12.3.2 Data and ecpAFifo Port........................................................................................................152
12.3.3 Device Status Register (DSR)..............................................................................................152
12.3.4 Device Control Register (DCR) ............................................................................................153
12.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010......................................................................153
12.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011 ..........................................................................153
12.3.7 TFIFO (Test FIFO Mode) Mode = 110 .................................................................................154
12.3.8 CNFGA (Configuration Register A) Mode = 111 ..................................................................154
12.3.9 CNFGB (Configuration Register B) Mode = 111 ..................................................................154

W83627DHG
Publication Release Date: Aug, 22, 2007
-IX- Version 1.4
12.3.10 ECR (Extended Control Register) Mode = all ......................................................................155
12.3.11 ECP Pin Descriptions...........................................................................................................156
12.3.12 ECP Operation.....................................................................................................................157
12.3.13 FIFO Operation ....................................................................................................................158
12.3.14 DMA Transfers.....................................................................................................................158
12.3.15 Programmed I/O (NON-DMA) Mode ....................................................................................158
13. KEYBOARD CONTROLLER ........................................................................................................ 159
13.1 Output Buffer....................................................................................................................... 159
13.2 Input Buffer.......................................................................................................................... 159
13.3 Status Register.................................................................................................................... 160
13.4 Commands.......................................................................................................................... 160
13.5 Hardware GATEA20/Keyboard Reset Control Logic .......................................................... 162
13.5.1 KB Control Register .............................................................................................................162
13.5.2 Port 92 Control Register.......................................................................................................163
14. POWER MANAGEMENT EVENT ................................................................................................ 164
14.1 Power Control Logic............................................................................................................ 164
14.1.1 PSON# Logic .......................................................................................................................165
14.1.2 AC Power Failure Resume...................................................................................................166
14.2 Wake Up the System by Keyboard and Mouse .................................................................. 167
14.2.1 Waken up by Keyboard events ............................................................................................167
14.2.2 Waken up by Mouse events.................................................................................................167
14.3 Resume Reset Logic........................................................................................................... 168
14.4 PWROK Generation............................................................................................................ 169
14.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST# - both for UBE and UBF
Version Only.......................................................................................................................................170
15. SERIALIZED IRQ.......................................................................................................................... 173
15.1 Start Frame ......................................................................................................................... 173
15.2 IRQ/Data Frame..................................................................................................................174
15.3 Stop Frame.......................................................................................................................... 175
16. WATCHDOG TIMER .................................................................................................................... 176
17. GENERAL PURPOSE I/O ............................................................................................................ 177
18. VID INPUTS AND OUTPUTS....................................................................................................... 178
18.1 VID Input Detection .............................................................................................................178
18.2 VID Output Control..............................................................................................................178
19. PCI RESET BUFFERS ................................................................................................................. 179
20. CONFIGURATION REGISTER .................................................................................................... 180
20.1 Chip (Global) Control Register............................................................................................ 180
20.2 Logical Device 0 (FDC) ....................................................................................................... 187
20.3 Logical Device 1 (Parallel Port)........................................................................................... 190
20.4 Logical Device 2 (UART A) ................................................................................................. 191
20.5 Logical Device 3 (UART B) ................................................................................................. 191
20.6 Logical Device 5 (Keyboard Controller) .............................................................................. 193

W83627DHG
Publication Release Date: Aug, 22, 2007
-X- Version 1.4
20.7 Logical Device 6 (Serial Peripheral Interface)..................................................................... 194
20.8 Logical Device 7 (GPIO6) ................................................................................................... 195
20.9 Logical Device 8 (WDTO# & PLED) ................................................................................... 196
20.10 Logical Device 9 (GPIO2, GPIO3, GPIO4, GPIO5) ............................................................ 198
20.11 Logical Device A (ACPI)...................................................................................................... 202
20.12 Logical Device B (Hardware Monitor) ................................................................................. 210
20.13 Logical Device C (PECI, SST) ............................................................................................ 212
21. SPECIFICATIONS ........................................................................................................................ 216
21.1 Absolute Maximum Ratings ................................................................................................ 216
21.2 DC CHARACTERISTICS .................................................................................................... 216
21.3 AC CHARACTERISTICS .................................................................................................... 225
21.3.1 AC Power Failure Resume Timing.......................................................................................225
21.3.2 VSBGATE# Timing – for UBE and UBF Version Only .........................................................230
21.3.3 Clock Input Timing ...............................................................................................................231
21.3.4 PECI and SST Timing ..........................................................................................................232
21.3.5 SPI Timing ...........................................................................................................................233
21.3.6 SMBus Timing......................................................................................................................234
21.3.7 Floppy Disk Drive Timing .....................................................................................................235
21.3.8 UART/Parallel Port...............................................................................................................236
21.3.9 Parallel Port Mode Parameters ............................................................................................238
21.3.10 Parallel Port .........................................................................................................................239
21.3.11 KBC Timing Parameters ......................................................................................................248
21.3.12 GPIO Timing Parameters.....................................................................................................251
21.4 LPC Timing.......................................................................................................................... 253
22. TOP MARKING SPECIFICATION ................................................................................................ 254
23. PACKAGE SPECIFICATION........................................................................................................ 255

W83627DHG
Publication Release Date: Aug, 22, 2007
-1- Version 1.4
1. GENERAL DESCRIPTION
The W83627DHG is a member of Winbond's Super I/O product line. This family features the LPC (Low
Pin Count) interface. This interface is more economical than its ISA counterpart, in that it has
approximately forty pins fewer, yet still provides as great performance. In addition, the improvement
allows even more efficient operation of software, BIOS and device drivers.
In addition to providing an LPC interface for I/O, the W83627DHG monitors several critical parameters
in PC hardware, including power supply voltages, fan speeds, and temperatures. In terms of
temperature monitoring, the W83627DHG adopts the Current Mode (dual current source) approach.
The W83627DHG also supports the Smart Fan control system, including “SMART FANTM I and SMART
FANTM III, which makes the system more stable and user-friendly.
The W83627DHG supports four -- 360K, 720K, 1.2M, 1.44M, or 2.88M -- disk drive types and data
transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. The disk drive adapter supports the
functions of floppy disk drive controller (compatible with the industry standard 82077/ 765), data
separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive
interface control logic, and interrupt and DMA logic. Such a wide range of functions integrated into one
W83627DHG greatly reduces the number of required components to interface with floppy disk drives.
The W83627DHG provides two high-speed serial communication ports (UARTs), one of which provides
IR functions IrDA 1.0 (SIR for 1.152K bps). Each UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete modem-control capability, and a processor interrupt
system. Both UARTs support legacy speeds up to 115.2K bps as well as even higher baud rates of
230K, 460K, or 921K bps to support higher speed modems.
The W83627DHG supports the PC-compatible printer port (SPP), the bi-directional printer port (BPP),
the enhanced parallel port (EPP) and the extended capabilities port (ECP).
The W83627DHG provides a bridge of the Low Pin Count interface to Serial Peripheral Interface (SPI)
that supports up to 8M bits serial flash ROM. The W83627DHG provides flexible I/O control functions
through a set of 40 general purpose I/O (GPIO) ports. These GPIO ports may serve as simple I/O ports
or may be individually configured to provide alternative functions.
The W83627DHG supports the SST (Simple Serial Transport) interface and Intel®PECI (Platform
Environment Control Interface).
The W83627DHG fully complies with the Microsoft©PC98, PC99 and PC2001 System Design Guides
and meets the requirements of ACPI.
The configuration registers inside the W83627DHG support mode selection, function enable and
disable, and power-down selection. Furthermore, the configurable PnP features are compatible with
the plug-and-play feature in Windows 95/98/2000/XPTM, making the allocation of the system resources
more efficient than ever.
One special characteristic of the Super I/O product line is the separation of the power supply in normal
operation from that in standby operation. Please pay attention to the layout of these two power supplies
to avoid short circuits. Otherwise, the feature will not function.

W83627DHG
Publication Release Date: Aug, 22, 2007
-2- Version 1.4
2. FEATURES
General
yMeet LPC Spec. 1.01
ySupport LDRQ# (LPC DMA), SERIRQ (Serialized IRQ)
yIntegrated hardware monitor functions
yCompliant with Microsoft PC98/PC99/PC2001 System Design Guide
ySupport DPM (Device Power Management), ACPI (Advanced Configuration and Power Interface)
yProgrammable configuration settings
ySingle 24- or 48-MHz clock input
ySupport selective pins of 5 V tolerance
FDC
yVariable write pre-compensation with track-selection capability
ySupport vertical recording format
yDMA-enable logic
y16-byte data FIFOs
ySupport floppy disk drives and tape drives
yDetect all overrun and underrun conditions
yBuilt-in address mark detection circuit to simplify the read electronics
yFDD anti-virus functions with software write protect and FDD-write enable signal (write data signal
forced to be inactive)
ySupport 3.5-inch or 5.25-inch floppy disk drives
yCompatible with industry standard 82077
y360K / 720K / 1.2M / 1.44M / 2.88M formats
y250K, 300K, 500K, 1M, 2M bps data transfer rate
ySupport 3-mode FDD and its Windows driver
UART
yTwo high-speed, 16550-compatible UARTs with 16-byte send / receive FIFOs
yFully programmable serial-interface characteristics:
--- 5, 6, 7 or 8-bit characters
--- Even, odd or no parity bit generation/detection
--- 1, 1.5 or 2 stop-bit generation
yInternal diagnostic capabilities:
--- Loop-back controls for communications link fault isolation
--- Break, parity, overrun, framing error simulation
yProgrammable baud rate generator allows division of clock source by any value from 1 to (216-1)
yMaximum baud rate for clock source 14.769 MHz is up to 921K bps. The baud rate at 24 MHz is
1.5 M bps.

W83627DHG
Publication Release Date: Aug, 22, 2007
-3- Version 1.4
Parallel Port
yCompatible with IBM parallel port
ySupport PS/2-compatible bi-directional parallel port
ySupport Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification
ySupport Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification
yEnhanced printer port back-drive current protection
Keyboard Controller
•8042-based keyboard controller
•Asynchronous Access to two data registers and one status register
•Software-compatible with 8042
•Support PS/2 mouse
•Support Port 92
•Support both interrupt and polling modes
•Fast Gate A20 and Hardware Keyboard Reset
•6, 8, 12, or 16 MHz operating frequency
Hardware Monitor Functions
ySmart Fan control system, supporting the functions of SMART FANTM I -- “Thermal CruiseTM” and
“Speed CruiseTM” modes, and SMART FANTM III
yProgrammable threshold temperature to speed fan fully while current temperature exceeds this
threshold in the Thermal CruiseTM mode
yThree thermal inputs from the different combinations of remote thermistors, and the thermal diode
output
ySupport Current Mode (dual current source) temperature sensing method
yNine voltage inputs (CPUVCORE, VIN[0..3] and 3VCC, AVCC , 3VSB, VBAT)
yFive fan-speed monitoring inputs
yFour fan-speed controls
yDual mode for fan control (PWM and DC)
yBuilt-in case open detection circuit
yProgrammable hysteresis and setting points for all monitored items
yOver-temperature indicator output
yIssue SMI#, OVT# to activate system protection
yWinbond Hardware DoctorTM support
yEight VID inputs / outputs
yProvide I2C interface to read / write registers
Serial Peripheral Interface
ySupport up to 8M bits SPI Flash Memory with clock up to 33 MHz
ySupport Mode 0 and Mode 3

W83627DHG
Publication Release Date: Aug, 22, 2007
-4- Version 1.4
Infrared
•Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
•Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps
General Purpose I/O Ports
y40 programmable general purpose I/O ports
yGPIO port 4 supports the optional functions of Watchdog Timer Out and Suspend LED Output
yGP30, GP31 and GP35 can distinguish whether the input pins undergo any transitions by reading
the registers. All of the 3 GPIOs can assert PSOUT# or PME# to wake up the system if each of
them undergoes any transition.
OnNow Functions
yKeyboard Wake-Up by programmable keys
yMouse Wake-Up by programmable buttons
yOnNow Wake-Up from all of the ACPI sleeping states (S1-S5)
Simple Serial Transport™ Interface
ySST temperature and voltage Combination Sensor command support
ySupport SST 0.9 Specification
PECI Interface
ySupport PECI 1.0 Specification
ySupport 4 CPU addresses and 2 domains per CPU address
Package
y128-pin QFP
yPb-free/RoHS

W83627DHG
Publication Release Date: Aug, 22, 2007
-5- Version 1.4
LPC
Interface
LRESET#, PCICLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ
FDC
UARTA
GPIO UARTB
IR
Floppy drive
interface signals
Printer port
interface signals
ACPI
General-purpose
I/O pins
Hardware Monitor
channel and Vref
KBC
Keyboard/Mouse
data and clock
HM
W83627DHG
UARTA interface
signals
UARTB interface
signals
Infrared interface
signals
PRT
SMBus
Interface
SCL
SDA
SST
Interface
SST
PECI
Interface PECI
VID
VID I/O pins
SPI
Serial Peripheral
Interface
3. BLOCK DIAGRAM

W83627DHG
Publication Release Date: Aug, 22, 2007
-6- Version 1.4
4. PIN LAYOUT
GP37
KDAT/GP26
KCLK/GP27
3VSB
KBRST
GA20M
SI/AUXFANIN1
RIA#/GP60
DCDA#/GP61
VSS
SOUTA/GP62(PENKBC)
SINA/GP63
DTRA#/GP64(PENROM)
RTSA#/GP65(HEFRAS)
DSRA#/GP66
CTSA#/GP67
3VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 AVCC RSTOUT0# RSTOUT1# GP30 GP31 GP32/RSTOUT2#/SCL GP33/RSTOUT3#/SDA GP34/RSTOUT4# GP35 PME# GP40/RIB# GP41/DCDB# GP42/SOUTB/IRTX(FAN_SET2) GP43/SINB/IRRX GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# GP50/WDTO#(EN_GTL) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED GP36 PSIN#/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25
CPUTIN
SYSTIN
CPUD-
PECISB
Vtt
PECI
NC
NC
AUXFANIN0
CPUFANIN0
SYSFANIN
SST
CPUFANOUT0
SYSFANOUT
(FAN_SET)PLED
BEEP/SO
GP21/CPUFANIN1
GP20/CPUFANOUT1
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DRVDEN0
GP23/SCK
INDEX#
MOA#
SMI#/OVT#
DSA#
AUXFANOUT
DIR#
STEP#
WD#
WE#
3VCC
TRAK0#
WP#
RDATA#
HEAD#
DSKCHG#
IOCLK
GP22/SCE
VSS
PCICLK
LDRQ#
SERIRQ
LAD3 LAD2 LAD1 LAD0
3VCC
LFRAME#
LRESET#
SLCT
PE
BUSY
ACK#
PD7 PD6 PD5 PD4
W83627DHG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVCC 3VSB 3VSB
3VCC
3VCC
3VCC
VTT
VBAT
GP37
KDAT/GP26
KCLK/GP27
3VSB
KBRST
GA20M
SI/AUXFANIN1
RIA#/GP60
DCDA#/GP61
VSS
SOUTA/GP62(PENKBC)
SINA/GP63
DTRA#/GP64(PENROM)
RTSA#/GP65(HEFRAS)
DSRA#/GP66
CTSA#/GP67
3VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 AVCC RSTOUT0# RSTOUT1# GP30 GP31 GP32/RSTOUT2#/SCL GP33/RSTOUT3#/SDA GP34/RSTOUT4# GP35 PME# GP40/RIB# GP41/DCDB# GP42/SOUTB/IRTX(FAN_SET2) GP43/SINB/IRRX GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# GP50/WDTO#(EN_GTL) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED GP36 PSIN#/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25
CPUTIN
SYSTIN
CPUD-
PECISB
Vtt
PECI
NC
NC
AUXFANIN0
CPUFANIN0
SYSFANIN
SST
CPUFANOUT0
SYSFANOUT
(FAN_SET)PLED
BEEP/SO
GP21/CPUFANIN1
GP20/CPUFANOUT1
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DRVDEN0
GP23/SCK
INDEX#
MOA#
SMI#/OVT#
DSA#
AUXFANOUT
DIR#
STEP#
WD#
WE#
3VCC
TRAK0#
WP#
RDATA#
HEAD#
DSKCHG#
IOCLK
GP22/SCE
VSS
PCICLK
LDRQ#
SERIRQ
LAD3 LAD2 LAD1 LAD0
3VCC
LFRAME#
LRESET#
SLCT
PE
BUSY
ACK#
PD7 PD6 PD5 PD4
W83627DHG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVCC 3VSB 3VSB
3VCC
3VCC
3VCC
VTT
VBAT
Pin Layout for W83627DHG UBC version

W83627DHG
Publication Release Date: Aug, 22, 2007
-7- Version 1.4
GP37/SUSC#
KDAT/GP26
KCLK/GP27
3VSB
KBRST
GA20M
SI/AUXFANIN1
RIA#/GP60
DCDA#/GP61
VSS
SOUTA/GP62(PENKBC)
SINA/GP63
DTRA#/GP64(PENROM)
RTSA#/GP65(HEFRAS)
DSRA#/GP66
CTSA#/GP67
3VCC
STB#
AFD#
ERR#
INIT#
SLIN#
PD0
PD1
PD2
PD3
AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 AVCC RSTOUT0# RSTOUT1# GP30/PWROK2 GP31/VSBGATE# GP32/RSTOUT2#/SCL GP33/RSTOUT3#/SDA GP34/RSTOUT4# GP35/ATXPGD PME# GP40/RIB# GP41/DCDB# GP42/SOUTB/IRTX(FAN_SET2) GP43/SINB/IRRX GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# GP50/WDTO#(EN_GTL) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED(EN_ACPI) GP36/FTPRST# PSIN#/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25
CPUTIN
SYSTIN
CPUD-
PECISB
Vtt
PECI
NC
NC
AUXFANIN0
CPUFANIN0
SYSFANIN
SST
CPUFANOUT0
SYSFANOUT
(FAN_SET)PLED
BEEP/SO
GP21/CPUFANIN1
GP20/CPUFANOUT1
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DRVDEN0
GP23/SCK
INDEX#
MOA#
SMI#/OVT#
DSA#
AUXFANOUT
DIR#
STEP#
WD#
WE#
3VCC
TRAK0#
WP#
RDATA#
HEAD#
DSKCHG#
IOCLK
GP22/SCE
VSS
PCICLK
LDRQ#
SERIRQ
LAD3 LAD2 LAD1 LAD0
3VCC
LFRAME#
LRESET#
SLCT
PE
BUSY
ACK#
PD7 PD6 PD5 PD4
W83627DHG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AVCC 3VSB 3VSB
3VCC
3VCC
3VCC
VTT
VBAT
Pin Layout for W83627DHG UBE and UBF version

W83627DHG
Publication Release Date: Aug, 22, 2007
-8- Version 1.4
5. PIN DESCRIPTION
Note: Please refer to Section 21.2 DC CHARACTERISTICS for details.
AOUT - Analog output pin
AIN - Analog input pin
INcd - CMOS-level input pin with internal pull-down resistor
INcs - CMOS-level, Schmitt-trigger input pin
INcsu - CMOS-level, Schmitt-trigger input pin with internal pull-up resistor
INt- TTL-level input pin
INtd - TTL-level input pin with internal pull-down resistor
INts - TTL-level, Schmitt-trigger input pin
INtp3 - 3.3V, TTL-level input pin
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
INtu - TTL-level input pin with internal pull-up resistor
I/O8- bi-directional pin with 8-mA source-sink capability
I/O8t - TTL-level, bi-directional pin with 8-mA source-sink capability
I/O12 - bi-directional pin with 12-mA source-sink capability
I/O12t - TTL-level, bi-directional pin with 12-mA source-sink capability
I/O12ts - Schmitt-trigger, bi-directional pin with 12-mA source-sink capability
I/O12tp3 - 3.3V, TTL-level, bi-directional pin with 12-mA source-sink capability
I/OD8t - TTL-level, bi-directional pin. Open-drain output with 8-mA sink capability
I/OD12 - Bi-directional pin. Open-drain output with 12-mA sink capability
I/OD12t - TTL-level bi-directional pin. Open-drain output with 12-mA sink capability
I/OD12cs - CMOS-level, bi-directional, Schmitt-trigger pin. Open-drain output with 12-mA sink capability
I/OD12ts - TTL-level, bi-directional, Schmitt-trigger pin. Open-drain output with 12-mA sink capability
I/OD12tp3 - 3.3V, TTL-level, bi-directional pin. Open-drain output with 12-mA sink capability
I/OD16t - TTL-level, bi-directional pin. Open-drain output with 16-mA sink capability
I/OD16ts - Schmitt-trigger, bi-directional pin. Open-drain output with 16-mA sink capability
I/OD16cs - CMOS-level, Schmitt-trigger, bi-directional pin. Open-drain output with 16-mA sink capability
I/OD24t - TTL-level, bi-directional pin. Open-drain output with 24-mA sink capability
O12p3 - 3.3V output pin with 12-mA source-sink capability
O12tp3 - 3.3V, TTL-level output pin with 12-mA source-sink capability
O8- TTL-level output pin with 8-mA source-sink capability
O12 - TTL-level output pin with 12-mA source-sink capability
O24 - TTL-level output pin with 24-mA source-sink capability
OD8- Open-drain output pin with 8-mA sink capability
OD12 - Open-drain output pin with 12-mA sink capability
OD24 - Open-drain output pin with 24-mA sink capability
I/OV3 - Bi-direction pin with source capability of 6 mA and sink capability of 1 mA